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AJvYcCV70/mYvxsJILs2Zc6xCTwkJ2qwl7lsn4aZViMyjB12g7VUs3S7HOhZGb4qrsCCTcMuzBguXwp1PnvBFTSojsDBDRxnAzVEhe7+TQZaUEipa2RaALU= X-Gm-Message-State: AOJu0Yw81OrhCP/uGo1R7SPUb3ZNE0que2eBCa7Hei/HQxH4uCbSGD9U FA0wHKizmgUf0YeVfL0p4N8Vtwy4aTMAeQAcDhs+bSdA9vw+dlTV X-Google-Smtp-Source: AGHT+IFugrwths5qXmiGrpyWRGPLjxYN9ABKLPzyxBbke/9wB2mDHVVUMREeBtaM84xUj8get90c5A== X-Received: by 2002:a05:6830:3c05:b0:703:6a3e:d3ca with SMTP id 46e09a7af769-70940c61394mr3405364a34.26.1722085224394; Sat, 27 Jul 2024 06:00:24 -0700 (PDT) Received: from localhost.localdomain ([115.240.194.54]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cdb73b9b7dsm7231551a91.21.2024.07.27.06.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jul 2024 06:00:24 -0700 (PDT) From: Animesh Agarwal To: Cc: Animesh Agarwal , Daniel Baluta , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vladimir Zapolskiy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] dt-bindings: gpio: nxp,lpc3220-gpio: Convert to dtschema Date: Sat, 27 Jul 2024 18:30:03 +0530 Message-ID: <20240727130008.408772-1-animeshagarwal28@gmail.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240727_060026_360381_E0806B68 X-CRM114-Status: GOOD ( 17.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert the NXP LPC3220 SoC GPIO controller bindings to DT schema format. Cc: Daniel Baluta Signed-off-by: Animesh Agarwal --- Changes in v2: - Changed the file name to match the compatible string. - Removed optional from the description of '#gpio-cells' as it was wrongly present. --- .../devicetree/bindings/gpio/gpio_lpc32xx.txt | 43 --------------- .../bindings/gpio/nxp,lpc3220-gpio.yaml | 52 +++++++++++++++++++ 2 files changed, 52 insertions(+), 43 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt create mode 100644 Documentation/devicetree/bindings/gpio/nxp,lpc3220-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt b/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt deleted file mode 100644 index 49819367a011..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt +++ /dev/null @@ -1,43 +0,0 @@ -NXP LPC32xx SoC GPIO controller - -Required properties: -- compatible: must be "nxp,lpc3220-gpio" -- reg: Physical base address and length of the controller's registers. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be 3: - 1) bank: - 0: GPIO P0 - 1: GPIO P1 - 2: GPIO P2 - 3: GPIO P3 - 4: GPI P3 - 5: GPO P3 - 2) pin number - 3) optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) -- reg: Index of the GPIO group - -Example: - - gpio: gpio@40028000 { - compatible = "nxp,lpc3220-gpio"; - reg = <0x40028000 0x1000>; - gpio-controller; - #gpio-cells = <3>; /* bank, pin, flags */ - }; - - leds { - compatible = "gpio-leds"; - - led0 { - gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led1 { - gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */ - linux,default-trigger = "timer"; - default-state = "off"; - }; - }; diff --git a/Documentation/devicetree/bindings/gpio/nxp,lpc3220-gpio.yaml b/Documentation/devicetree/bindings/gpio/nxp,lpc3220-gpio.yaml new file mode 100644 index 000000000000..cea2f2bb2393 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nxp,lpc3220-gpio.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/nxp,lpc3220-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC3220 SoC GPIO controller + +maintainers: + - Animesh Agarwal + +properties: + compatible: + const: nxp,lpc3220-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 3 + description: | + 1) bank: + 0: GPIO P0 + 1: GPIO P1 + 2: GPIO P2 + 3: GPIO P3 + 4: GPI P3 + 5: GPO P3 + 2) pin number + 3) flags: + - bit 0 specifies polarity (0 for normal, 1 for inverted) + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + #include + + gpio@40028000 { + compatible = "nxp,lpc3220-gpio"; + reg = <0x40028000 0x1000>; + gpio-controller; + #gpio-cells = <3>; /* bank, pin, flags */ + };