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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cf28c7b0besm6969413a91.14.2024.07.28.09.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jul 2024 09:50:31 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v5 1/5] riscv: Extend exception handling support for interrupts Date: Mon, 29 Jul 2024 00:50:18 +0800 Message-ID: <20240728165022.30075-2-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240728165022.30075-1-jamestiotio@gmail.com> References: <20240728165022.30075-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Andrew Jones Add install_irq_handler() to enable tests to install interrupt handlers. Also add local_irq_enable() and local_irq_disable() to respectively enable and disable IRQs via the sstatus.SIE bit. Signed-off-by: Andrew Jones Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/csr.h | 2 ++ lib/riscv/asm/processor.h | 13 +++++++++++++ lib/riscv/processor.c | 27 +++++++++++++++++++++++---- 3 files changed, 38 insertions(+), 4 deletions(-) diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index 52608512..d6909d93 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -11,6 +11,8 @@ #define CSR_STVAL 0x143 #define CSR_SATP 0x180 +#define SR_SIE _AC(0x00000002, UL) + /* Exception cause high bit - is an interrupt if set */ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h index 32c499d0..6451adb5 100644 --- a/lib/riscv/asm/processor.h +++ b/lib/riscv/asm/processor.h @@ -5,6 +5,7 @@ #include #define EXCEPTION_CAUSE_MAX 16 +#define INTERRUPT_CAUSE_MAX 16 typedef void (*exception_fn)(struct pt_regs *); @@ -13,6 +14,7 @@ struct thread_info { unsigned long hartid; unsigned long isa[1]; exception_fn exception_handlers[EXCEPTION_CAUSE_MAX]; + exception_fn interrupt_handlers[INTERRUPT_CAUSE_MAX]; }; static inline struct thread_info *current_thread_info(void) @@ -20,7 +22,18 @@ static inline struct thread_info *current_thread_info(void) return (struct thread_info *)csr_read(CSR_SSCRATCH); } +static inline void local_irq_enable(void) +{ + csr_set(CSR_SSTATUS, SR_SIE); +} + +static inline void local_irq_disable(void) +{ + csr_clear(CSR_SSTATUS, SR_SIE); +} + void install_exception_handler(unsigned long cause, void (*handler)(struct pt_regs *)); +void install_irq_handler(unsigned long cause, void (*handler)(struct pt_regs *)); void do_handle_exception(struct pt_regs *regs); void thread_info_init(void); diff --git a/lib/riscv/processor.c b/lib/riscv/processor.c index ece7cbff..0dffadc7 100644 --- a/lib/riscv/processor.c +++ b/lib/riscv/processor.c @@ -36,10 +36,21 @@ void do_handle_exception(struct pt_regs *regs) { struct thread_info *info = current_thread_info(); - assert(regs->cause < EXCEPTION_CAUSE_MAX); - if (info->exception_handlers[regs->cause]) { - info->exception_handlers[regs->cause](regs); - return; + if (regs->cause & CAUSE_IRQ_FLAG) { + unsigned long irq_cause = regs->cause & ~CAUSE_IRQ_FLAG; + + assert(irq_cause < INTERRUPT_CAUSE_MAX); + if (info->interrupt_handlers[irq_cause]) { + info->interrupt_handlers[irq_cause](regs); + return; + } + } else { + assert(regs->cause < EXCEPTION_CAUSE_MAX); + + if (info->exception_handlers[regs->cause]) { + info->exception_handlers[regs->cause](regs); + return; + } } show_regs(regs); @@ -47,6 +58,14 @@ void do_handle_exception(struct pt_regs *regs) abort(); } +void install_irq_handler(unsigned long cause, void (*handler)(struct pt_regs *)) +{ + struct thread_info *info = current_thread_info(); + + assert(cause < INTERRUPT_CAUSE_MAX); + info->interrupt_handlers[cause] = handler; +} + void install_exception_handler(unsigned long cause, void (*handler)(struct pt_regs *)) { struct thread_info *info = current_thread_info(); From patchwork Sun Jul 28 16:50:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Raphael Tiovalen X-Patchwork-Id: 13744028 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6A216EB4A for ; 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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cf28c7b0besm6969413a91.14.2024.07.28.09.50.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jul 2024 09:50:33 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v5 2/5] riscv: Update exception cause list Date: Mon, 29 Jul 2024 00:50:19 +0800 Message-ID: <20240728165022.30075-3-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240728165022.30075-1-jamestiotio@gmail.com> References: <20240728165022.30075-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update the list of exception and interrupt causes to follow the latest RISC-V privileged ISA specification (version 20240411 section 18.6.1). Reviewed-by: Andrew Jones Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/csr.h | 10 ++++++++++ lib/riscv/asm/processor.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index d6909d93..ba810c9f 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -36,6 +36,16 @@ #define EXC_VIRTUAL_INST_FAULT 22 #define EXC_STORE_GUEST_PAGE_FAULT 23 +/* Interrupt causes */ +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h index 6451adb5..4c9ad968 100644 --- a/lib/riscv/asm/processor.h +++ b/lib/riscv/asm/processor.h @@ -4,7 +4,7 @@ #include #include -#define EXCEPTION_CAUSE_MAX 16 +#define EXCEPTION_CAUSE_MAX 24 #define INTERRUPT_CAUSE_MAX 16 typedef void (*exception_fn)(struct pt_regs *); From patchwork Sun Jul 28 16:50:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Raphael Tiovalen X-Patchwork-Id: 13744029 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C97A6F2E0 for ; Sun, 28 Jul 2024 16:50:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722185439; cv=none; b=AhoGYt/r19Fuoc8ZyhDRLYSp1ZwQjqm23Cq8MVwJqrgm3jNSv4O8Rru358RGMvnGLktwUNLdG+ZTXpTpJqmfflYWt3UtTHV6hn+YJK04+rKhEawm9CffW9/rfjbBDATrcw+DMmHAD99zyU4L0uBgqhwWTfrq98wSwWK8peL+NbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722185439; c=relaxed/simple; bh=XRJl/uPgbWvSt8YMeQOUC5JnzlykeY0IhpbgHZkzhCc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l2dTWOz4xde9ESy4fq4ESuk9UTbMQ/vFH8Af5fNfzGqTzZ9zqAKP9WdaEdnt4S+NuvsoDbCmd5qL6emOR7MEBaV6Ej07Z8U2Q5dRVZFqerOKcZkkXjSXF62fYj65FgUxaBeEWcLN3Hb8OAZNxk/mBcnL8AqSu9JmdFIfO6RHE5c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=e+vykUJi; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="e+vykUJi" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1fc569440e1so20722915ad.3 for ; Sun, 28 Jul 2024 09:50:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722185436; x=1722790236; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BEiXZ1Hftnd13V7cSXtmzxOOQFtbwN2az/SPk33hWyc=; b=e+vykUJiowodE0mz8UzFLoulH4q1PGD+90b1lRsvuOLoinYjJoExY8Y8skif3nN/0+ cP1U/PVejTriIWuLnws9GpZ15MQmNiqAuTVsD2wEtABa6ZJOauNMKoiVVc5Zwjh6hrEI lH7TsOcTvmFh0bhklEW2XTHe99Jsu/FrKFaBwG7Uu3NjDYOec6UtCnTHO2EbvniMGf36 CFxvV5ko16OzmggH3W7lf6tCsyGh1Noadln0yX+7AWqNrUi9QbYAcMZz/rzIKtctgEMt +CCfvXuHrpVB4LPusSYhhWLUpvfU8fOdQsh1goPWSow8XEEEvniQsO3oWc85e8zWRjTn auPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722185436; x=1722790236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BEiXZ1Hftnd13V7cSXtmzxOOQFtbwN2az/SPk33hWyc=; b=D5Yk9jQAM0Z9qY6kRQJ7gjXjZpySay+dvB+CS57/8wUP/cXgbtnn5RZZfWMvuaw+cP CkHF7dyBDC7IRqtVvxZL7q/+wz0YDEA6N/2Kz+NJFxlBg8KCDRsiYpXkAdaLfCiZoimU +eKoUDxEZtsPhbbE0JzTPAK1uuNkAqtwuoz00gzia/2jUZ9YpYW6Qha6tlXA6vOcCBd7 eqOO0/IBZY5iXyO0thxe4YqPsLo+l+smZz43AGhr0pkoML4pzgqhQf0WvOCLkW3GcKGT W5Ix3jzKTjPMye3yVIRtm+6s/m/FW2kCB7KI21OUx1PtRygMvdZC6fJXh30ZCLDLkvXT lbJA== X-Gm-Message-State: AOJu0YzeHSetaGQkyf5DcrkZGSXoGHMPA5b2+dXC6WVIPqwyNeVgXzFj mkfPrPXqVT3WFD43HjjKS3CnYKATAIqBFb5Qp6BslPEDxsIWsujaLoJK6zBWtio= X-Google-Smtp-Source: AGHT+IGEE725G2chsjeyL29DACmq+1GFpgRJnqRTT1ifMi62MPfDn9z5FD0POiYJZZ8jiOJUdwaa9Q== X-Received: by 2002:a17:903:190:b0:1fd:9420:1044 with SMTP id d9443c01a7336-1ff04817e13mr62739745ad.16.1722185436090; Sun, 28 Jul 2024 09:50:36 -0700 (PDT) Received: from JRT-PC.. ([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cf28c7b0besm6969413a91.14.2024.07.28.09.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jul 2024 09:50:35 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v5 3/5] riscv: Add method to probe for SBI extensions Date: Mon, 29 Jul 2024 00:50:20 +0800 Message-ID: <20240728165022.30075-4-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240728165022.30075-1-jamestiotio@gmail.com> References: <20240728165022.30075-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a `sbi_probe` helper method that can be used by SBI extension tests to check if a given extension is available. Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/sbi.h | 1 + lib/riscv/sbi.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h index d82a384d..5e1a674a 100644 --- a/lib/riscv/asm/sbi.h +++ b/lib/riscv/asm/sbi.h @@ -49,6 +49,7 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, void sbi_shutdown(void); struct sbiret sbi_hart_start(unsigned long hartid, unsigned long entry, unsigned long sp); +long sbi_probe(int ext); #endif /* !__ASSEMBLY__ */ #endif /* _ASMRISCV_SBI_H_ */ diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c index f39134c4..3d4236e5 100644 --- a/lib/riscv/sbi.c +++ b/lib/riscv/sbi.c @@ -38,3 +38,16 @@ struct sbiret sbi_hart_start(unsigned long hartid, unsigned long entry, unsigned { return sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_START, hartid, entry, sp, 0, 0, 0); } + +long sbi_probe(int ext) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 0, 0, 0, 0, 0); + assert(!ret.error && ret.value >= 2); + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, ext, 0, 0, 0, 0, 0); + assert(!ret.error); + + return ret.value; +} From patchwork Sun Jul 28 16:50:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Raphael Tiovalen X-Patchwork-Id: 13744030 Received: from mail-il1-f177.google.com (mail-il1-f177.google.com [209.85.166.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A81D26F303 for ; Sun, 28 Jul 2024 16:50:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722185441; cv=none; b=MvwEMLZvAelfShOlLnQ790U6fJ6jHOAfmmTVBcCqoB8WS8hfWfiRTbw6eS6VzqapkYzNtJeHuLDoj9IBFxV8HwyjK69FCJoThGDFiTXOIomUgrDLjeptKcHfwJncf7MpcgrfEwD/ykmoy+GuV5/r7bk7OyycmWnpDPz4pE1U4cY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722185441; c=relaxed/simple; bh=+agld4zlqbig1ojMy8W/4esTTSShlDdWhqY4xkhgWBE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bDfcc19xq5EHHh5ARr2AXtCjhSDc4bbU9Re9a5asoJ0fSGWrUPmBkkIx3Z6aYmM9oN2LwhnWiNvBLZJAiNLK8FMQ/0pNRwlXQlNFTboqJYjceqsDvVLQKwTynVElBbfosCP+rTKYRQX7y0SGZAplPA8SJJlC3UUbLuisy61vS5U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=aoal+dkx; arc=none smtp.client-ip=209.85.166.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aoal+dkx" Received: by mail-il1-f177.google.com with SMTP id e9e14a558f8ab-396db51d140so15699905ab.0 for ; Sun, 28 Jul 2024 09:50:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722185438; x=1722790238; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wwRnLnxZnIX7jpw6TVepgUUISRg5HGFY1cuRHhUH+u4=; b=aoal+dkxaOwPT5Vv4XRLH3d5M0/fzywkjkMIwWCP1+ILlSovwArC8xBo5n/NOaV6sX SGIhxtfcHB7Ww1sKU8zVAZmDP8DI1pToNJV3MPiL1v2/MKftzYRZaNWqAOG3amCvJGce zAxvEY1iqUaJpjqS+SHf/0av8h9PUp8tSRMWfqdwOMeYGfJhaS3SiGIq0Kj6+QTbqWIS qfSaUYsGpcwJ5fEWtQqb+JIMcm5QnLnt7WLFu8281stQJESNFcXdTrUOUKLcGPCEzfuS XZ/ANgS/eEzcbjnuP4Mtz/mbGZPzzj1SYdmaiwOnQL3mI+iibE4ogRDXq5rauHNDqO+r 7LMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722185438; x=1722790238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wwRnLnxZnIX7jpw6TVepgUUISRg5HGFY1cuRHhUH+u4=; b=HFe5LM9i/N3j1Npyb67LWovV3WOO/pv9AO+9tR/+KtoWm9GNiYgvVejZpZTKuFvfT/ iwngAFowUQUAervOXWohU2V7dW9o9g/mqEhwdHctfi4B94eLp6pxeNtL1JqrdqNyid9m q17yDIANZky0S9yUmVxn4awspTPwFTrcLileANewns6gENZFE0xAsIauZig6fmzREyrc QFtxNFCg1jY/NzXB7yFfsrnjnX+Lsti9sczanDqT45YzNnfOkpsGejw4lPQh/EfGpHwD ZWThDmE8qIvFYBx7k4vsYa3OKPG1DzmGfSDTo19ah+q8K8eqS00VCPn8SJzL8iGYxete 6o0A== X-Gm-Message-State: AOJu0YzqC34KwdqcMQoaRRuzIcLZZ78B9Wa32U2o7HZDxbyRyRR4FWNa Djfzcr7Oqv3wP0RJVEpZllUBjVv7uthnTjkWmMI2yGHcI9MMn59o0n/X76OE3Fk= X-Google-Smtp-Source: AGHT+IGDbgR1fW8w1fF/wiQe2wYgOqO26bcBkZACY1CmOXNlqWChY8wo2q1ubKE51A9uHwlZ5v7MLw== X-Received: by 2002:a05:6e02:1a4e:b0:383:873c:e2a4 with SMTP id e9e14a558f8ab-39aec400f39mr54849855ab.18.1722185438296; Sun, 28 Jul 2024 09:50:38 -0700 (PDT) Received: from JRT-PC.. ([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cf28c7b0besm6969413a91.14.2024.07.28.09.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jul 2024 09:50:37 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v5 4/5] riscv: Add some delay and timer routines Date: Mon, 29 Jul 2024 00:50:21 +0800 Message-ID: <20240728165022.30075-5-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240728165022.30075-1-jamestiotio@gmail.com> References: <20240728165022.30075-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a delay method that would allow tests to wait for some specified number of cycles. Also add a conversion helper method between microseconds and cycles. This conversion is done by using the timebase frequency, which is obtained during setup via the device tree. Reviewed-by: Andrew Jones Signed-off-by: James Raphael Tiovalen --- riscv/Makefile | 2 ++ lib/riscv/asm/csr.h | 1 + lib/riscv/asm/delay.h | 16 ++++++++++++++++ lib/riscv/asm/setup.h | 1 + lib/riscv/asm/timer.h | 14 ++++++++++++++ lib/riscv/delay.c | 21 +++++++++++++++++++++ lib/riscv/setup.c | 4 ++++ lib/riscv/timer.c | 28 ++++++++++++++++++++++++++++ 8 files changed, 87 insertions(+) create mode 100644 lib/riscv/asm/delay.h create mode 100644 lib/riscv/asm/timer.h create mode 100644 lib/riscv/delay.c create mode 100644 lib/riscv/timer.c diff --git a/riscv/Makefile b/riscv/Makefile index 919a3ebb..b0cd613f 100644 --- a/riscv/Makefile +++ b/riscv/Makefile @@ -30,6 +30,7 @@ cflatobjs += lib/memregions.o cflatobjs += lib/on-cpus.o cflatobjs += lib/vmalloc.o cflatobjs += lib/riscv/bitops.o +cflatobjs += lib/riscv/delay.o cflatobjs += lib/riscv/io.o cflatobjs += lib/riscv/isa.o cflatobjs += lib/riscv/mmu.o @@ -38,6 +39,7 @@ cflatobjs += lib/riscv/sbi.o cflatobjs += lib/riscv/setup.o cflatobjs += lib/riscv/smp.o cflatobjs += lib/riscv/stack.o +cflatobjs += lib/riscv/timer.o ifeq ($(ARCH),riscv32) cflatobjs += lib/ldiv32.o endif diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index ba810c9f..a9b1bd42 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -10,6 +10,7 @@ #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 #define CSR_SATP 0x180 +#define CSR_TIME 0xc01 #define SR_SIE _AC(0x00000002, UL) diff --git a/lib/riscv/asm/delay.h b/lib/riscv/asm/delay.h new file mode 100644 index 00000000..31379eac --- /dev/null +++ b/lib/riscv/asm/delay.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASMRISCV_DELAY_H_ +#define _ASMRISCV_DELAY_H_ + +#include +#include + +extern void delay(uint64_t cycles); +extern void udelay(unsigned long usecs); + +static inline uint64_t usec_to_cycles(uint64_t usec) +{ + return (timebase_frequency * usec) / 1000000; +} + +#endif /* _ASMRISCV_DELAY_H_ */ diff --git a/lib/riscv/asm/setup.h b/lib/riscv/asm/setup.h index 7f81a705..a13159bf 100644 --- a/lib/riscv/asm/setup.h +++ b/lib/riscv/asm/setup.h @@ -7,6 +7,7 @@ #define NR_CPUS 16 extern struct thread_info cpus[NR_CPUS]; extern int nr_cpus; +extern uint64_t timebase_frequency; int hartid_to_cpu(unsigned long hartid); void io_init(void); diff --git a/lib/riscv/asm/timer.h b/lib/riscv/asm/timer.h new file mode 100644 index 00000000..f7504f84 --- /dev/null +++ b/lib/riscv/asm/timer.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASMRISCV_TIMER_H_ +#define _ASMRISCV_TIMER_H_ + +#include + +extern void timer_get_frequency(void); + +static inline uint64_t timer_get_cycles(void) +{ + return csr_read(CSR_TIME); +} + +#endif /* _ASMRISCV_TIMER_H_ */ diff --git a/lib/riscv/delay.c b/lib/riscv/delay.c new file mode 100644 index 00000000..d4f76c29 --- /dev/null +++ b/lib/riscv/delay.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024, James Raphael Tiovalen + */ +#include +#include +#include +#include + +void delay(uint64_t cycles) +{ + uint64_t start = timer_get_cycles(); + + while ((timer_get_cycles() - start) < cycles) + cpu_relax(); +} + +void udelay(unsigned long usecs) +{ + delay(usec_to_cycles((uint64_t)usecs)); +} diff --git a/lib/riscv/setup.c b/lib/riscv/setup.c index 50ffb0d0..e0b5f6f7 100644 --- a/lib/riscv/setup.c +++ b/lib/riscv/setup.c @@ -20,6 +20,7 @@ #include #include #include +#include #define VA_BASE ((phys_addr_t)3 * SZ_1G) #if __riscv_xlen == 64 @@ -38,6 +39,7 @@ u32 initrd_size; struct thread_info cpus[NR_CPUS]; int nr_cpus; +uint64_t timebase_frequency; static struct mem_region riscv_mem_regions[NR_MEM_REGIONS + 1]; @@ -199,6 +201,7 @@ void setup(const void *fdt, phys_addr_t freemem_start) mem_init(PAGE_ALIGN(__pa(freemem))); cpu_init(); + timer_get_frequency(); thread_info_init(); io_init(); @@ -264,6 +267,7 @@ efi_status_t setup_efi(efi_bootinfo_t *efi_bootinfo) } cpu_init(); + timer_get_frequency(); thread_info_init(); io_init(); initrd_setup(); diff --git a/lib/riscv/timer.c b/lib/riscv/timer.c new file mode 100644 index 00000000..d78d254c --- /dev/null +++ b/lib/riscv/timer.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024, James Raphael Tiovalen + */ +#include +#include +#include +#include + +void timer_get_frequency(void) +{ + const struct fdt_property *prop; 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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cf28c7b0besm6969413a91.14.2024.07.28.09.50.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jul 2024 09:50:40 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v5 5/5] riscv: sbi: Add test for timer extension Date: Mon, 29 Jul 2024 00:50:22 +0800 Message-ID: <20240728165022.30075-6-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240728165022.30075-1-jamestiotio@gmail.com> References: <20240728165022.30075-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a test for the set_timer function of the time extension. The test checks that: - The time extension is available - The installed timer interrupt handler is called - The timer interrupt is received within a reasonable time interval - The timer interrupt pending bit is cleared after the set_timer SBI call is made - The timer interrupt can be cleared either by requesting a timer interrupt infinitely far into the future or by masking the timer interrupt The timer interrupt delay can be set using the TIMER_DELAY environment variable in microseconds. The default delay value is 200 milliseconds. Since the interrupt can arrive a little later than the specified delay, allow some margin of error. This margin of error can be specified via the TIMER_MARGIN environment variable in microseconds. The default margin of error is 200 milliseconds. Signed-off-by: James Raphael Tiovalen Reviewed-by: Andrew Jones --- lib/riscv/asm/csr.h | 8 +++ lib/riscv/asm/sbi.h | 5 ++ lib/riscv/asm/timer.h | 10 +++ riscv/sbi.c | 144 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 167 insertions(+) diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index a9b1bd42..24b333e0 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -4,11 +4,15 @@ #include #define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_STIMECMP 0x14d +#define CSR_STIMECMPH 0x15d #define CSR_SATP 0x180 #define CSR_TIME 0xc01 @@ -47,6 +51,10 @@ #define IRQ_S_GEXT 12 #define IRQ_PMU_OVF 13 +#define IE_TIE (_AC(0x1, UL) << IRQ_S_TIMER) + +#define IP_TIP IE_TIE + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h index 5e1a674a..73ab5438 100644 --- a/lib/riscv/asm/sbi.h +++ b/lib/riscv/asm/sbi.h @@ -16,6 +16,7 @@ enum sbi_ext_id { SBI_EXT_BASE = 0x10, + SBI_EXT_TIME = 0x54494d45, SBI_EXT_HSM = 0x48534d, SBI_EXT_SRST = 0x53525354, }; @@ -37,6 +38,10 @@ enum sbi_ext_hsm_fid { SBI_EXT_HSM_HART_SUSPEND, }; +enum sbi_ext_time_fid { + SBI_EXT_TIME_SET_TIMER = 0, +}; + struct sbiret { long error; long value; diff --git a/lib/riscv/asm/timer.h b/lib/riscv/asm/timer.h index f7504f84..b3514d3f 100644 --- a/lib/riscv/asm/timer.h +++ b/lib/riscv/asm/timer.h @@ -11,4 +11,14 @@ static inline uint64_t timer_get_cycles(void) return csr_read(CSR_TIME); } +static inline void timer_irq_enable(void) +{ + csr_set(CSR_SIE, IE_TIE); +} + +static inline void timer_irq_disable(void) +{ + csr_clear(CSR_SIE, IE_TIE); +} + #endif /* _ASMRISCV_TIMER_H_ */ diff --git a/riscv/sbi.c b/riscv/sbi.c index 762e9711..044258bb 100644 --- a/riscv/sbi.c +++ b/riscv/sbi.c @@ -6,7 +6,25 @@ */ #include #include +#include +#include +#include +#include +#include +#include #include +#include +#include + +struct timer_info { + bool timer_works; + bool mask_timer_irq; + bool timer_irq_set; + bool timer_irq_cleared; + unsigned long timer_irq_count; +}; + +static struct timer_info timer_info_; static void help(void) { @@ -19,6 +37,36 @@ static struct sbiret __base_sbi_ecall(int fid, unsigned long arg0) return sbi_ecall(SBI_EXT_BASE, fid, arg0, 0, 0, 0, 0, 0); } +static struct sbiret __time_sbi_ecall(unsigned long stime_value) +{ + return sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0); +} + +static bool timer_irq_pending(void) +{ + return csr_read(CSR_SIP) & IP_TIP; +} + +static void timer_irq_handler(struct pt_regs *regs) +{ + if (timer_info_.timer_irq_count < ULONG_MAX) + ++timer_info_.timer_irq_count; + + timer_info_.timer_works = true; + if (timer_irq_pending()) + timer_info_.timer_irq_set = true; + + if (timer_info_.mask_timer_irq) { + timer_irq_disable(); + __time_sbi_ecall(0); + } else { + __time_sbi_ecall(ULONG_MAX); + } + + if (!timer_irq_pending()) + timer_info_.timer_irq_cleared = true; +} + static bool env_or_skip(const char *env) { if (!getenv(env)) { @@ -112,6 +160,101 @@ static void check_base(void) report_prefix_pop(); } +static void check_time(void) +{ + struct sbiret ret; + unsigned long begin, end, duration; + unsigned long d = getenv("TIMER_DELAY") ? strtol(getenv("TIMER_DELAY"), NULL, 0) + : 200000; + unsigned long margin = getenv("TIMER_MARGIN") ? strtol(getenv("TIMER_MARGIN"), NULL, 0) + : 200000; + + d = usec_to_cycles(d); + margin = usec_to_cycles(margin); + + report_prefix_push("time"); + + if (!sbi_probe(SBI_EXT_TIME)) { + report_skip("time extension not available"); + report_prefix_pop(); + return; + } + + report_prefix_push("set_timer"); + + install_irq_handler(IRQ_S_TIMER, timer_irq_handler); + local_irq_enable(); + if (cpu_has_extension(smp_processor_id(), ISA_SSTC)) { + csr_write(CSR_STIMECMP, ULONG_MAX); +#if __riscv_xlen == 32 + csr_write(CSR_STIMECMPH, ULONG_MAX); +#endif + } + timer_irq_enable(); + + begin = timer_get_cycles(); + ret = __time_sbi_ecall(begin + d); + + report(!ret.error, "set timer"); + if (ret.error) + report_info("set timer failed with %ld\n", ret.error); + + report(!timer_irq_pending(), "pending timer interrupt bit cleared"); + + while ((end = timer_get_cycles()) <= (begin + d + margin) && !timer_info_.timer_works) + cpu_relax(); + + report(timer_info_.timer_works, "timer interrupt received"); + report(timer_info_.timer_irq_set, "pending timer interrupt bit set in irq handler"); + report(timer_info_.timer_irq_set && timer_info_.timer_irq_cleared, + "pending timer interrupt bit cleared by setting timer to -1"); + + if (timer_info_.timer_works) { + duration = end - begin; + report(duration >= d && duration <= (d + margin), "timer delay honored"); + } + + if (timer_info_.timer_irq_count > 1) + report_fail("timer interrupt received multiple times"); + + if (csr_read(CSR_SIE) & IE_TIE) { + timer_info_ = (struct timer_info){ .mask_timer_irq = true }; + begin = timer_get_cycles(); + ret = __time_sbi_ecall(begin + d); + + report(!ret.error, "set timer for mask irq test"); + if (ret.error) + report_info("set timer for mask irq test failed with %ld\n", ret.error); + + while ((end = timer_get_cycles()) <= (begin + d + margin) + && !timer_info_.timer_works) + cpu_relax(); + + report(timer_info_.timer_works, "timer interrupt received for mask irq test"); + report(timer_info_.timer_irq_set, + "pending timer interrupt bit set in irq handler for mask irq test"); + report(timer_info_.timer_irq_set && timer_info_.timer_irq_cleared, + "pending timer interrupt bit cleared by masking timer irq"); + + if (timer_info_.timer_works) { + duration = end - begin; + report(duration >= d && duration <= (d + margin), + "timer delay honored for mask irq test"); + } + + if (timer_info_.timer_irq_count > 1) + report_fail("timer interrupt received multiple times for mask irq test"); + } else { + report_skip("timer irq enable bit is not writable, skipping mask irq test"); + } + + local_irq_disable(); + install_irq_handler(IRQ_S_TIMER, NULL); + + report_prefix_pop(); + report_prefix_pop(); +} + int main(int argc, char **argv) { @@ -122,6 +265,7 @@ int main(int argc, char **argv) report_prefix_push("sbi"); check_base(); + check_time(); return report_summary(); }