From patchwork Mon Jul 29 01:56:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 13744171 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CAC42BD04 for ; Mon, 29 Jul 2024 02:15:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722219359; cv=none; b=SEKbBnIbyCpm5u7YXtRFaIbkBrOoBlRHYGDn3zLqHDXRkPPXFL/XOKRpWdVkPNa/S4JEC1TPy5RJvJw3nmO8wIkawyrJg1uedQy8oMcIVFbGb4jGkBJsT78dVith4jsuAeB+Cew6jVdgoUsbDOdIvCNeOtgW2uXurFFb5tHYPAQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722219359; c=relaxed/simple; bh=PBVxTpmzAj3S5x0cRCD2X+EpBUj60QIbx/qURLaqUjQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=nNfqyMRRjuGS3QR41aQWDhjKOl6N3HdS8BIF51fNAoLSBRw/+8BeVDgm+ktv77/8ngxekY5OPh3j2HW9FSpUF2F5CE8Cnbo8OiaUSRonZJ2ibQGT6k3juZKonhOesOlinjZTx4VPLvCegSpSwsLHUjsIV5GBvjMGJPeClFFxjAU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E5E032000FC; Mon, 29 Jul 2024 04:15:56 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id AC0FA2000C6; Mon, 29 Jul 2024 04:15:56 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 0AFDD183AD45; Mon, 29 Jul 2024 10:15:54 +0800 (+08) From: Richard Zhu To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, l.stach@pengutronix.de Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v4 1/4] dt-bindings: imx6q-pcie: Add reg-name "dbi2" and "atu" for i.MX8M PCIe Endpoint Date: Mon, 29 Jul 2024 09:56:42 +0800 Message-Id: <1722218205-10683-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1722218205-10683-1-git-send-email-hongxing.zhu@nxp.com> References: <1722218205-10683-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Add reg-name: "dbi2", "atu" for i.MX8M PCIe Endpoint. For i.MX8M PCIe EP, the dbi2 and atu addresses are pre-defined in the driver. This method is not good. In commit b7d67c6130ee ("PCI: imx6: Add iMX95 Endpoint (EP) support"), Frank suggests to fetch the dbi2 and atu from DT directly. This commit is preparation to do that for i.MX8M PCIe EP. These changes wouldn't break driver function. When "dbi2" and "atu" properties are present, i.MX PCIe driver would fetch the according base addresses from DT directly. If only two reg properties are provided, i.MX PCIe driver would fall back to the old method. Signed-off-by: Richard Zhu Reviewed-by: Frank Li Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml index a06f75df8458..84ca12e8b25b 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -65,12 +65,14 @@ allOf: then: properties: reg: - minItems: 2 - maxItems: 2 + minItems: 4 + maxItems: 4 reg-names: items: - const: dbi - const: addr_space + - const: dbi2 + - const: atu - if: properties: @@ -129,8 +131,11 @@ examples: pcie_ep: pcie-ep@33800000 { compatible = "fsl,imx8mp-pcie-ep"; - reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; - reg-names = "dbi", "addr_space"; + reg = <0x33800000 0x100000>, + <0x18000000 0x8000000>, + <0x33900000 0x100000>, + <0x33b00000 0x100000>; + reg-names = "dbi", "addr_space", "dbi2", "atu"; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_ROOT>; From patchwork Mon Jul 29 01:56:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 13744173 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 320A978C68 for ; Mon, 29 Jul 2024 02:15:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722219361; cv=none; b=qarzxVxxjGwjj6n6fUCg6iwaUTmF/wtTcv6o0a9GuanjjXxT+4WfeJwLP/B5dUh3KwiVGMrrdBOym1Xy5UlO7NDGStpBVsKkwevA/14qw6vlcuUoIUMcdlHYs+S3a/xl1eX99tFuSgIhf4BbV5w52b01CUaUxX/U1N1m071YAY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722219361; c=relaxed/simple; bh=ZFVhHkPTDo6FoZoGON2cwcym53yrgu8xxzROJaE3ohw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=tB8mpyzIFXw2KiKftekdD8+hjpUYS+VmeasAy93uoFgX0yH6LZSqcKQrjXKP4cfw7hF3dTTRfAaPhKZCZg3SJLufgh2yKnyHj4eO4nTrcngocql7+PNNNYE+7hOdrP6qnywq/g7kIjLte7uOZ9jXsf6f6GyYuW9QWL2gH8xZeqM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id B1A3C200CB4; Mon, 29 Jul 2024 04:15:57 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 7A1902000C6; Mon, 29 Jul 2024 04:15:57 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 3990E183AD44; Mon, 29 Jul 2024 10:15:56 +0800 (+08) From: Richard Zhu To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, l.stach@pengutronix.de Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v4 2/4] dts: arm64: imx8mq: Add dbi2 and atu reg for i.MX8MQ PCIe EP Date: Mon, 29 Jul 2024 09:56:43 +0800 Message-Id: <1722218205-10683-3-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1722218205-10683-1-git-send-email-hongxing.zhu@nxp.com> References: <1722218205-10683-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Add dbi2 and iatu reg for i.MX8MQ PCIe EP. For i.MX8M PCIe EP, the dbi2 and atu addresses are pre-defined in the driver. This method is not good. In commit b7d67c6130ee ("PCI: imx6: Add iMX95 Endpoint (EP) support"), Frank suggests to fetch the dbi2 and atu from DT directly. This commit is preparation to do that for i.MX8MQ PCIe EP. These changes wouldn't break driver function. When "dbi2" and "atu" properties are present, i.MX PCIe driver would fetch the according base addresses from DT directly. If only two reg properties are provided, i.MX PCIe driver would fall back to the old method. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index e03186bbc415..d51de8d899b2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1819,9 +1819,11 @@ pcie1: pcie@33c00000 { pcie1_ep: pcie-ep@33c00000 { compatible = "fsl,imx8mq-pcie-ep"; - reg = <0x33c00000 0x000400000>, - <0x20000000 0x08000000>; - reg-names = "dbi", "addr_space"; + reg = <0x33c00000 0x100000>, + <0x20000000 0x8000000>, + <0x33d00000 0x100000>, + <0x33f00000 0x100000>; + reg-names = "dbi", "addr_space", "dbi2", "atu"; num-lanes = <1>; interrupts = ; interrupt-names = "dma"; From patchwork Mon Jul 29 01:56:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 13744174 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB18A7BAF7 for ; Mon, 29 Jul 2024 02:16:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722219362; cv=none; b=gRhcKeU/ynIfge5ag+BNjiLmx9J3mc7C+1Am1+c7UWvUkS6Q3F79eqUtAgCHd1m2UhU1VtQEWEfepBGvcc3x1PnJBLdTGXjikpTK884vbparnRjZVIlqmt81DLaKgm6lvTpuL4xwOVOjB9a8HliLHHc+uza7bExf+PGEbIVQG58= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722219362; c=relaxed/simple; bh=jUz1JOh/2k7wU3uH9YIn6s6nrjSbpT25iIzTCuHpEHU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Wtnb2yiaPvflKiQw2oHegjjnIYNfUxHXK/ji3sASAqqsVRUgGejsHb1Lou41NYLK6VcJCXO9/AhQAPl9SbyjyvRQHHgx6iSb2+hLyHm0lTLBU44+82AWsIbMRoosWhOIaLl7Zj9sRWzn897wSQILlS3NfPzq8C6+SC+qRzrK1Es= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 46000200662; Mon, 29 Jul 2024 04:15:59 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 0E76C2000C6; Mon, 29 Jul 2024 04:15:59 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 5BD3C183AD45; Mon, 29 Jul 2024 10:15:57 +0800 (+08) From: Richard Zhu To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, l.stach@pengutronix.de Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v4 3/4] dts: arm64: imx8mp: Add dbi2 and atu reg for i.MX8MP PCIe EP Date: Mon, 29 Jul 2024 09:56:44 +0800 Message-Id: <1722218205-10683-4-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1722218205-10683-1-git-send-email-hongxing.zhu@nxp.com> References: <1722218205-10683-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Add dbi2 and iatu reg for i.MX8MP PCIe EP. For i.MX8M PCIe EP, the dbi2 and atu addresses are pre-defined in the driver. This method is not good. In commit b7d67c6130ee ("PCI: imx6: Add iMX95 Endpoint (EP) support"), Frank suggests to fetch the dbi2 and atu from DT directly. This commit is preparation to do that for i.MX8MP PCIe EP. These changes wouldn't break driver function. When "dbi2" and "atu" properties are present, i.MX PCIe driver would fetch the according base addresses from DT directly. If only two reg properties are provided, i.MX PCIe driver would fall back to the old method. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 603dfe80216f..53748227db10 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2125,8 +2125,11 @@ pcie: pcie@33800000 { pcie_ep: pcie-ep@33800000 { compatible = "fsl,imx8mp-pcie-ep"; - reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; - reg-names = "dbi", "addr_space"; + reg = <0x33800000 0x100000>, + <0x18000000 0x8000000>, + <0x33900000 0x100000>, + <0x33b00000 0x100000>; + reg-names = "dbi", "addr_space", "dbi2", "atu"; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_ROOT>; From patchwork Mon Jul 29 01:56:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 13744175 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4B147E0FF for ; Mon, 29 Jul 2024 02:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722219364; cv=none; b=VVexwU13Bnhc5mKx6T3+SaQ2N/dGdTauCSedvQ8TUT/6DAk5gMY0Wvj/a+KXE8R+/rGhngTCEZ1qpjDOH8d9DJCeBjDCWty4VG8l2G1bppSxIuv3Qm/lNEJz+z6UOQuZfvYru7seWRCsmGfAWdpyKhl6hjrKu2AFumN6Kl56l8g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722219364; c=relaxed/simple; bh=+pROoBrurakCGvGD6Blb+j4X0fhL0kJk1RxtcHF2TWU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=mQx0+76HV4NAUpdpLX+hJesYAXrp6kMq97QToqeRmOK+JQU2LJh0p7QZG294L52sQTSxbB5HFuNNw8BxeybrFzv93njku/vACKSInQmckWRg+ohSyn4CYoJzA2sjUVIGLJuoJVwrxMCJIo/dt87nU2WljHs5pb6zPZ8pgGB9O5g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 50986201274; Mon, 29 Jul 2024 04:16:00 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 212232019A4; Mon, 29 Jul 2024 04:16:00 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 81D30183AD44; Mon, 29 Jul 2024 10:15:58 +0800 (+08) From: Richard Zhu To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, l.stach@pengutronix.de Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v4 4/4] dts: arm64: imx8mm: Add dbi2 and atu reg for i.MX8MM PCIe EP Date: Mon, 29 Jul 2024 09:56:45 +0800 Message-Id: <1722218205-10683-5-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1722218205-10683-1-git-send-email-hongxing.zhu@nxp.com> References: <1722218205-10683-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Add dbi2 and iatu reg for i.MX8MM PCIe EP. For i.MX8M PCIe EP, the dbi2 and atu addresses are pre-defined in the driver. This method is not good. In commit b7d67c6130ee ("PCI: imx6: Add iMX95 Endpoint (EP) support"), Frank suggests to fetch the dbi2 and atu from DT directly. This commit is preparation to do that for i.MX8MM PCIe EP. These changes wouldn't break driver function. When "dbi2" and "atu" properties are present, i.MX PCIe driver would fetch the according base addresses from DT directly. If only two reg properties are provided, i.MX PCIe driver would fall back to the old method. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 9535dedcef59..4de3bf22902b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1375,9 +1375,11 @@ pcie0: pcie@33800000 { pcie0_ep: pcie-ep@33800000 { compatible = "fsl,imx8mm-pcie-ep"; - reg = <0x33800000 0x400000>, - <0x18000000 0x8000000>; - reg-names = "dbi", "addr_space"; + reg = <0x33800000 0x100000>, + <0x18000000 0x8000000>, + <0x33900000 0x100000>, + <0x33b00000 0x100000>; + reg-names = "dbi", "addr_space", "dbi2", "atu"; num-lanes = <1>; interrupts = ; interrupt-names = "dma";