From patchwork Mon Jul 29 12:37:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 13744849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B711FC3DA61 for ; Mon, 29 Jul 2024 12:39:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Message-ID:Date:Subject:Cc:To:From:Reply-To: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=+NZITpfAHD8JXe97iGR8siEXB5NDSsMSDkZ3Z4QQ/T4=; b=fNdhelJqF2lYijRqUghPaQaW0Y oVzKoqFiCZUYeQJp8nKSIiFGMoFThGXimoiYLGjqpWb0l/ep7TBB27hJVa6CTjk7Yoaubex7NjmKQ sHUm15C4NCg5KK0M0s171/5wYhFjqb4ZoMybhI/3jMM4n9s8LE2+wW2D84SG06XXaDQMS1aFNmL/N dlM/lpbdPer6GAl0pAYFLQphKg8YkEU8XM2TmKyOIWpOdYVPXgs1h/AASvUFjrJFAoaMZvyiP9aPg vJeRly67vUJ5T3qSuzspySiY/ZQup5aPyiEIHs6F65kvxLZ/S/2WR+y9O/txlf3iOQSJG1IuaOkxs qU0ATyeA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYPfB-0000000BGjT-3LdM; Mon, 29 Jul 2024 12:39:41 +0000 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYPd5-0000000BG9S-1mhW; Mon, 29 Jul 2024 12:37:32 +0000 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-75a6c290528so1977286a12.1; Mon, 29 Jul 2024 05:37:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722256650; x=1722861450; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=+NZITpfAHD8JXe97iGR8siEXB5NDSsMSDkZ3Z4QQ/T4=; b=ZCuNFYPaDOCGKvpsJm9GmdK4+UElaoPtEITw+hCT8KHRlUGlyBZaNYqYPIr3UBAUFG ar4bh66oYgbbMKSeiVdrIwdzmblE9MznQBGQNIli3cDN1kVzN4Od+XDbB/Yi/Wg1ErYz tV4B/8cdNw2enB3kpgFCrtmREPyv3Qmc/aX5H0K4f7yngKTmEGRasBs1yfXvQZ/WCQtd dSQTvrku5ZmyKIIDugqapRWtZ9kGCEws68ag0f25bN3pyuuOP1R7fEn5ovCCuX2sTRbr kpQHPFONoaBbesXBkm0IaukBKvvdkCuwsPFnMrMr8GIPD2d7I67Mq72dooAggRKe/SxJ XSoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722256650; x=1722861450; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=+NZITpfAHD8JXe97iGR8siEXB5NDSsMSDkZ3Z4QQ/T4=; b=oBN5nTppWk9A+Z0Ch2Vq/t8Jk3nHLpKuu7jw7ZdzQ9Xdr2kNhsQ/5H+kSuReyOHLwl uLma5TlhYelw3CJGLuK0585C/H03D6l2ypwsT6hIp066vazjny/u8NHB+uPXYqf8dHM4 1unwbZAyTx7sfqQQZAZwZEbycizHY9LF2qyXJp8s98ZKqYDfhtL9k9zjGsusNVplSOOy 5lJF45oFW69UHKrJpzZOVDP/vwZQFJ4YZXop5DzhUysQjs2hBYP3zMmjgMLDXxBE7pBP UQE8pdljr3vIwV0s3V2RKyNdfZbieiUAlGPYsOpGjOWKHuOBuAvcoZU/LrITq3Uv4ULO klWQ== X-Forwarded-Encrypted: i=1; AJvYcCU46u3abOAkEVbB9N0VF16TPserWcKEJzk3HTV5hl+R7oI3HYbXbvb9mtuDkWMCYbahbxoSUN4k/dDu21O5vYh+MROQFEMDXErhhJTipt8IdTjv0yC2gUZT1TuIxSBKW15tlScIoRVkV74jchpw/BFQStaGu7NlscI= X-Gm-Message-State: AOJu0YxYTkoL3sNa+SObvrvNjDQDKESlJmojwgJuZkuBZQYFCzkHmhot onQwEZvDjkFJ3nEXizqI8wxO6VPwG5eWqrBfIMPlDERp58tV+W+u X-Google-Smtp-Source: AGHT+IFyQ9DhUPSpERL815jrQzcyMO8O7mgJl28wdppTnye7TQwm3hhu4PhWWh7+rQJKr3HKhOfIqw== X-Received: by 2002:a17:90b:1282:b0:2c9:7e9d:8424 with SMTP id 98e67ed59e1d1-2cf7e5f50f8mr5046382a91.30.1722256649932; Mon, 29 Jul 2024 05:37:29 -0700 (PDT) Received: from localhost.localdomain ([113.30.217.222]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cdb738842bsm10569248a91.6.2024.07.29.05.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jul 2024 05:37:29 -0700 (PDT) From: Anand Moon To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Anand Moon , Jonas Karlman , Dragan Simic , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5] arm64: dts: rockchip: Add missing pinctrl wake and clkreq for PCIe node Date: Mon, 29 Jul 2024 18:07:07 +0530 Message-ID: <20240729123709.2981-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.44.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240729_053731_493366_921D8C7C X-CRM114-Status: GOOD ( 17.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add missing pinctrl settings WAKE and CLKREQ for PCIe 3.0 x4, PCIe 3.0 x1 and PCIe 2.1 x1 nodes. Each component of PCIe communication have the following control signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state. PERST# is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization. WAKE# signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state. CLKREQ# signal is also an active-low signal and is used to request the reference clock. L1 sub-states is providing a digital signal (CLKREQ#) for PHYs to use to wake up and resume normal operation. Signed-off-by: Anand Moon --- v5: Merged all 3 patch into single patch, reabse on master Fix the $subject and commit message. Drop the RK_FUNC_GPIO for WAKE and CLKREQ as these seignal are ment for was introduced to allow PCI Express devices to enter even deeper power savings states (“L1.1” and “L1.2”) while still appearing to legacy software to be in the “L1” state --- .../boot/dts/rockchip/rk3588-rock-5b.dts | 46 +++++++++++++------ 1 file changed, 33 insertions(+), 13 deletions(-) base-commit: dc1c8034e31b14a2e5e212104ec508aec44ce1b9 diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 966bbc582d89..a1e83546f1be 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -318,7 +318,7 @@ map2 { &pcie2x1l0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + pinctrl-0 = <&pcie30x1_pins>; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; status = "okay"; @@ -326,7 +326,7 @@ &pcie2x1l0 { &pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie20x12_pins>; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay"; @@ -338,7 +338,7 @@ &pcie30phy { &pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; + pinctrl-0 = <&pcie30x4_pins>; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; @@ -363,28 +363,48 @@ hp_detect: hp-detect { }; }; - pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + pcie20x1 { + pcie20x12_pins: pcie20x12-pins { + rockchip,pins = + /* PCIE20_1_2_CLKREQn_M1_L */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* PCIE_PERST_L */ + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + /* PCIE20_1_2_WAKEn_M1_L */ + <3 RK_PD0 4 &pcfg_pull_up>; }; + }; + pcie30x1 { pcie2_0_vcc3v3_en: pcie2-0-vcc-en { rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + pcie30x1_pins: pcie30x1-pins { + rockchip,pins = + /* PCIE30x1_0_CLKREQn_M1_L */ + <4 RK_PA3 4 &pcfg_pull_down>, + /* PCIE30x1_0_PERSTn_M1_L */ + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>, + /* PCIE30x1_0_WAKEn_M1_L */ + <4 RK_PA4 4 &pcfg_pull_down>; }; }; - pcie3 { - pcie3_rst: pcie3-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - + pcie30x4 { pcie3_vcc3v3_en: pcie3-vcc3v3-en { rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; + + pcie30x4_pins: pcie30x4-pins { + rockchip,pins = + /* PCIE30X4_CLKREQn_M1_L */ + <4 RK_PB4 4 &pcfg_pull_up>, + /* PCIE30X4_PERSTn_M1_L */ + <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>, + /* PCIE30X4_WAKEn_M1_L */ + <4 RK_PB5 4 &pcfg_pull_down>; + }; }; usb {