From patchwork Mon Jul 29 20:18:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745665 X-Patchwork-Delegate: kw@linux.com Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011063.outbound.protection.outlook.com [52.101.70.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DCE5189F32; Mon, 29 Jul 2024 20:18:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.70.63 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284335; cv=fail; b=VJ+58BeRcRl6KmEN4YhYoYEMRKHrFUmF8JwUvbHRese2hQDVW9WINNRQvvnBBujOD2EakXQ4Mg36H4MiLmRUrEHY02QkvamBZenoI3njkaeu/8AhBNhkv2ls1di3WNXKoowEqUwuxXdg1gZkUNayeLTW/DgNF0UO+e2lx2VaP28= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284335; c=relaxed/simple; bh=8GmiRwyjVCKueLmdifQiyf0cCBkDTU3PrvdlV3diL4g=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=T7ij5M1vkYQChLBDi4vINK8b7GpgjEkZwbtmEeK40JT9PuCA8ayKEpQZL6LvJp/8CY/YtBowwuSv0XEwEb6qToSLA3bxHhTOi9rzHVn8Df4V3yFqlxsZWZF+pglIBjIJpmQC/UBP8mEKG/+jQ4bOFJHnZZsVxUmeSiSWofAeSgw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=jRSoHEst; arc=fail smtp.client-ip=52.101.70.63 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="jRSoHEst" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OYNVVdVt52R4fLOL422Qei3Ep4ENW5xGR7nuIrHgPNvUJntoOWryLeGvh5cGRT1mJReN1FmtIlbETt4adI8F9UK/fI0BCSYQpAL8EkfylpCx3vD4oZnwCFXuq2MY0fKbT+UEvx7yF6xiVUWUtBva5XMZs2p+h6KmSPPnBO4/+V6U7vOCYxTwbJYlMbyqA2Vdkqgy/Q0VUk+7Mv51dCmlrIXrKU2+zxv9VkGVlIq+3IctdFuMF2JFXHIIYzu7igeJugFtGvHaaV5xB1jA711pwSoMJbAdg26EFwgqzCK5SGgFDe+ds8rRqNkCO5dztQ3hSC5QeXlXRJGUg0/Jt88zBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=wjsqd2/1ET0LWcoUSUdzjlUigoVzTd54MwQNnEHQLvs=; b=YZ8LZW40IeLmgHlNrZ0nkuD0xQavwQ18LpUaQRaa78EORdiWsXiU4FEn4UpF3JyjS9POBvk+jMPIlpW2dk2kTeXTbqOn3pesgm1KUQ5xPFcGOEdI4cknTV54f95VoXR4LOotmsW4B+5wT7gMUqGIpgbsN5wvMennxBH0oVxnidxxlsB1SegFe8E5b3eGz1LxSOOiHJVu5R+Vnr9VzbNzHzL9D7Bt6+7wdXGmYNi0KQHp4sYBp5Jzl6otiMtiYZJXUux5X4oJWvZ4oWcnE1uselR2euZ3bVSZKcrv1oW10LG+OTX0F+SU53LYzr8NA+8TDoubuh04zdhpzWY60FS2uQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wjsqd2/1ET0LWcoUSUdzjlUigoVzTd54MwQNnEHQLvs=; b=jRSoHEsttZ/9z30jf9MCcKAs8D7glUd6SlPupxfhdwz2Q9OCc3YUkrHWlcozBDTuIb6Nz304u6glNrKbrskwrll9WspWD0nl0mxn2JTPR7lM0ojmZfshbRTwpdoVKymjNbaXEVSQm7gNGIMnsaRgiFBDEEpGRCT3p82IKKMCWAfyvKSbD8gwfj5ZgwrHAPKv+XQA0tn2GR84EHYoHhFGW6hSbsVs0mfdL6K84dTi3snTRf4p+1wsoob30fQOgbJC0xeGCjr3Qso96tWkVEizM4ByJibwsB6zWtJwmJpWbFsxAPmy/3QFNL61Nmh82c8oH1woXXoA1oCkoqDAxg2yUQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by PA2PR04MB10240.eurprd04.prod.outlook.com (2603:10a6:102:410::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.28; Mon, 29 Jul 2024 20:18:49 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:18:49 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:08 -0400 Subject: [PATCH v8 01/11] PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP Message-Id: <20240729-pci2_upstream-v8-1-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=1527; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=4IHOi9CJvMn1ca5R2jW29usLRGHmger6EqZbIy6/Dbk=; b=KpWFGa26Bm1FnWL63CkuSxfnwAGRolWwm1eFMwWb0J0UAW1ZfWdWQKW1iszBgmvMiX7fKYxPz 1Hk50qhYXLdDIs7zbIpnnuweXVQwSa1x0Or+dslcT677FDmVOh6h4Tc X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|PA2PR04MB10240:EE_ X-MS-Office365-Filtering-Correlation-Id: 3cdf62e6-5fbf-4bba-1cab-08dcb00ba832 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|52116014|366016|921020|38350700014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?9YiwRLs1Fc2QmR0qYvsZ8kR+JBVohsN?= =?utf-8?q?ZMZYCSJC8lgZJUKB5pNxqs6TiMC9G7TA3Mo0dPonBcIxzrMFRIE/JRyDWEJpa88Xw?= =?utf-8?q?Yz3sOPtd3OLABLlh6cpJQ45oCWQpv4mZIe8x3095Qau3rAwugGDPaRW0vN2P9DfTT?= =?utf-8?q?DkVxqhfu1N87HTsReU1WfKaJCU+7wDWk0K9XSt30BXYfV4DQBmEGoXS1RBRdRES5F?= =?utf-8?q?CPklu2MvHuQNVEdtjgr1qqdcTOyKRKm3ZtlMV9orAql6J0cqsx3xPlDwzHVQm/Opw?= =?utf-8?q?l9SDFf+Wd2RWubMnxFa0pu9Yaa0fH7v/6W9G7PMRvti3s8GHsvYO5RnDmkbxIoVco?= =?utf-8?q?jbsXWI3vYNl/lZObKqGQgXaciHfFYwod6y3jlXsPnIYqIlmNR4S3XCtS+IMQtooEZ?= =?utf-8?q?CwwW322kkDdIy6JzzeJZx0hYqkSNHP0HDAtGssRhbo5nylo6PivXR8aidPhctg9pf?= =?utf-8?q?A1jhk1v3gOhL0pptV7mq3XVHiuCYsUFIQaNSuHbJJjKlUBotioI0y2ASshAYS2vpD?= =?utf-8?q?9kXcc97gCrf1maS1NMohAlS4LkI90y0Lqa1YgtlYHKSkyYyRO0imzEtMVMkGLJbty?= =?utf-8?q?LSnoSKAbGnh8M604BaUiu3ncQpvP/76HtHs2qc+/QXvbfb8kyTfahxgcbnJ+FNuh3?= =?utf-8?q?fOi63H3+TinKAr/sxuMpE14N/nLX7F1uV4v/EqlYMMdB2tAL0wjswYuI4zpXg7TQW?= =?utf-8?q?wPSpVxXfiTe7te0BJpvE7OHxQIebVCkrbRlCr1ZWhNCw3M85WDjc5yL98JkzwO+wW?= =?utf-8?q?B1VjZaohNVnehWfik5hc4RBB7RUeIwAyf72f0TR8aIcl2SwsmttESW6x02WT9UH3i?= =?utf-8?q?EdDSTZ4iVffjPVwfL57oWz0PWoMVQsYODKyAKAeJBcLTU/Eh61T61X5O40PPdFuWn?= =?utf-8?q?6320PVsCjPhmeQApsLAqZIZ1D/Ic6ahcHR1B0pzq4011LjUgjMQXvs+Y6i14krH9W?= =?utf-8?q?/U+jFqPU/p43/KnU/mCKQ6CcTZxlCikyAymbvdtA/wOsKTbwc9Le8BEc6XpyezlNY?= =?utf-8?q?PFouKrdSNUncsiUZR+hioDN/DSAsPLGH9ghyqQt6B2JRSW3bRfgXHoVG6tw+1VNDm?= =?utf-8?q?ZSClpkvwsKVLKlwLU4iCOGgvOJ0tOhw19Siak/sN6Q15wBqz2ef+ck8Kg4opUP8Tv?= =?utf-8?q?dZPuO5xHAxr4D6QlylJNgiu2aqaYEMBDLUInbWA5qPbx8zgDniP/If10aWdSKEyXR?= =?utf-8?q?IU8alnY7bDccDUmFumyyYo8UKZ4Rcl+WzUGt8vTnKO1MCwt++aqLVR+b3lvPyflqw?= =?utf-8?q?6Fv7WbK+TBO1qSbvZDu2HEYRCa7engFRkkKjADdlwWUCeMXfQCMukJgPFmOUfkzda?= =?utf-8?q?xkuC+lKqa7xXzrEBW2BTMtX5WdFRg/r1i+otaNseKMT6Uz5I4f3U+M8=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(52116014)(366016)(921020)(38350700014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?FO61CxZ+KQ5CviIGJAD7s+U1+WSB?= =?utf-8?q?HlI/QD+jj3W11cCXsesbQPP52UybwREBcuCq46S2Wor4f6bkhgg27zr+iW3BGcc4W?= =?utf-8?q?fNzP50WbQFHengqB0gUjs0YOZcic+8opEcyRao+B9I6FOBFf+LeJPB2cxMHPtR1vF?= =?utf-8?q?gNgOxNlcjVsQkVrClVJk6vKyvRS3t1AdM5HOW6i1C0VGTZtOrqDzeGEoKZnAuS/HK?= =?utf-8?q?R1J0JZRAGjO+bUn3R+1ACEAirA2coNq5pdJMPC03vzC0TiUo0QwPJyrbHudU4BomL?= =?utf-8?q?8ci9SbExKw0axRrL5brMawz4UrLVXUofi+bENwhskZ1iAKAH5EVgw1WqFnN11u2CP?= =?utf-8?q?RcZItzRZhP0R3UxJg/eSWhWwkY2KEJSROUunFabfLbfNrzRBu5qU3/FL/AI082V/5?= =?utf-8?q?yHwAEtMvJhQ4JzWkcsWXMSThsujSnCMSvF/D1zditeHiUI5uHiI48xElshPJoalmA?= =?utf-8?q?gnB03lEslvVvp1bi2/ZySLc8+l1iiBUbhnHbVY5oTHXW/Pwa/oUl7UvcKSW9QSETa?= =?utf-8?q?oAm8wyQQ8vdsIv2L9rgCVOGNd8PblkruDPuQ2wZNfJzbH4LW5H4Ggls1g/ZijIVP2?= =?utf-8?q?j+2uJgxDqY2w4R8QslwV3M0vTUSfsUU8Dw6b1nrmjLg8xAeZnbJocIkTUdISVZj4g?= =?utf-8?q?onPY2agugZrLv8dL4qrXUSatbiyGZR4F9d9NCQIx0D0pF942wGCvVizceRFV0mU+n?= =?utf-8?q?JTR358kU0Qccb5g1t56g/m4OryObdYIde+LXWYMrU7++X04WUZvYabtyffuEimDH6?= =?utf-8?q?bgnKBzZ0vDsC3PB7ORFkYBXRXGpAt5w/V318og+GwY03Cy2VYYFFZ/hx+j6ihNMHE?= =?utf-8?q?/Yy3KrDsoXddlHh2Q0nHMQTMegG0gsp83zVpFiyGk9DnsNtW/s1BM+zUBDEQfKhsJ?= =?utf-8?q?l+D2M6TZ9RU7ZVCRzNxd2HmZsBfahl7S71KyAtRBuc0yQf6LEp8CT96PhcW8L5lwd?= =?utf-8?q?TRhAp3weok/XUK48pOZWyLv17k8ikqTvaeuLOYwRPfI9ieXa6jhqxn6Ki40pBtAiQ?= =?utf-8?q?oS4/qhJlnHmgupFDeG95IarJSCIxfnznex/jEM1GWZDc9CrwfdVSrGp/i3ynPJJJ3?= =?utf-8?q?QkhMrz1zTlGqcI0SC9z5nqn/cSgrzjZF7kTUFxV0nCRQ0NSVZ7v87rS1AQZ7gEQd9?= =?utf-8?q?MfmMltAk5D5QaIVWXQjLgJQAtjCjLe9ORZk9GJRfRDwaOR0Qs9RAEEgGRjk+12xo2?= =?utf-8?q?mPUjiMc94E44aW3No1PnurH3qi0ZpTg1H6vfbpYtZDSFAEYUG6I/0+Ix4RKDva5tm?= =?utf-8?q?HUtsbf+zhWRq/mgzS/It+bVOqmVrcn4BCm5DnJc9Tn+uzoyDupKp992Xu6Z17AR0m?= =?utf-8?q?HBgeYeWFPXZTM+58N04T27tvNng3UIZhcW4Wr3/+d6lU4Y0uQ1SJBReAGpEYDLKp0?= =?utf-8?q?GUYzNWpWUR+B3k19jgjgr8/QrmcMv5bClZ8aRF8Na43co7RayV/MUDu4A7oZAl9bZ?= =?utf-8?q?seXOsWumC8CHaSvGq1PvOEyl6SjB6V3L3Egh0konTXETf7tJNiQM3UkeAMb43GaYa?= =?utf-8?q?OLy979FA5tSY?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3cdf62e6-5fbf-4bba-1cab-08dcb00ba832 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:18:49.3569 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZQ1hedcu9iJEB2yvToVH47p8jEcHCu7nIyVKlGuOgTFBe16vZVMAf0svY5jbQ+2QmNp2KKreB2QQhbe/OUTj0A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA2PR04MB10240 From: Richard Zhu Add IMX6_PCIE_FLAG_HAS_APP_RESET flag to IMX8MM_EP and IMX8MP_EP drvdata. This flag was overlooked during code restructuring. It is crucial to release the app-reset from the System Reset Controller before initiating LTSSM to rectify the issue Fixes: 0c9651c21f2a ("PCI: imx6: Simplify reset handling by using *_FLAG_HAS_*_RESET") Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 964d67756eb2b..42fd17fbadfa5 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1562,7 +1562,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM_EP] = { .variant = IMX8MM_EP, - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHYDRV, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = imx8mm_clks, @@ -1573,7 +1574,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MP_EP] = { .variant = IMX8MP_EP, - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHYDRV, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, From patchwork Mon Jul 29 20:18:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745666 X-Patchwork-Delegate: kw@linux.com Received: from DU2PR03CU002.outbound.protection.outlook.com (mail-northeuropeazon11012008.outbound.protection.outlook.com [52.101.66.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4CF518A955; Mon, 29 Jul 2024 20:18:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.66.8 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284340; cv=fail; b=Zpk8KiDPwnr6ScERhYvOPqbcpWyz5v6Co1a7zYg+a6nASKwc8bjHLMsntq5uQo0wbQhtCkWVwJvr4a04jq6GnXDA/2WblIfuw//KO3+hP7qBhcH/cnpJSjrUYWqy1EYgoOCb9dbRaddii+007h3lwdZbPjo0INLT88eJL7gDdHU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284340; c=relaxed/simple; bh=hpqdEP5Pgr9uYqW28LwRsva5OMhbbRtNGQBvj6M+tnI=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=BdTF5Pg7FA4Ee/EP2n9l378nEZvnRAsa9jcrAISP5X4/F2h8yd2qWDYPf/gtvIs/nBgLe48mkQafIh7ZqJkbDsnLQsbIHQZjSf9cjo3pwOYr9rHN0XlFUeecaYR4VgXPoipJVxWfA/hEyhCuZMA7474gUY/HBwGyI6EQYFkXIz0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=BDQXh7Br; arc=fail smtp.client-ip=52.101.66.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="BDQXh7Br" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=kCmn3G3K3bfAlEB1RDyL8Y2NfWl/ubgGotUXEy3Y+21Ou/W6YfWHxGXbC+E9gr7pUNryMZKPywfeEmFIWq7Qjx9sGC/lPwzswXucWAhcR4VaD81TMYe5eZezgMR0iU5eUwXEbdwx6yBbiVd35zKlEHFJbzN48HopktWsi/mp62EKKdN8pBj+6i0bTETMTXyNYjqhC+PmR7cKicXbF1e1qcAQ0ElhHhTIY4ZBFaFoerVBFUyx9P6sk+uq/1kXEIAJVB4qwkzio3389T7P5ZcUhhPouHAwPUEn6GmgoT1NQGyv1AGdl1wTOHKO6Bzbt7CtvOGRPPjW54/n8QCUbFIYMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5mXPAqxzgD3DfLhd10Jz2h/StlIoB396o6udlgnSLuQ=; b=ZQFtbSqCf7w05w5oND7Of1QEoc/0JH8+NkfiplHxXikM+qnSAUazFKGI4NsuHghLiSpVCuogjfJu64PZejqpsO4BVlYpmqRrrQnO/FS4EdlyMoNbL9MExklP86XDZXCufNw6dvqnz+F3UyYt8VtNNlFaLyOGJ/KFuigOGuNYAcIn5tvVqazOoJlf5D0oLfysipnCaQ4GOf4YmyfuTdHNXpRNkgmB/pKfzYI+VDaLzSSnxlTZtLWivdFvNvpn1WX7cG+mdUnn+TyKMxCrItzsfYhA7kYEw9q4F/CX88vtMuw9PxQ/nSIuIcfZnJ/vwmrskPL5n1SySqIe6dorHzL31w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5mXPAqxzgD3DfLhd10Jz2h/StlIoB396o6udlgnSLuQ=; b=BDQXh7BrglETCVkHbH/QDi9fsb8gKxPhPkdQULuwCXXQgDvuAWIPvz4ku/Fe8iqVSmaxEQuOe9Vx+4R8bYhtC8kS8IXspAY+4RHw3c4HEyhQP2w0HoMeYsFEGhU1ance+I5twl+OlqWoxLbXhiqRJ8QLx52GaPPzkLSfkDAP3ajFVs2C/Z34c6NgJGMkyrNPpC9pXM4r5/ronPHEvKyvtxO0r9EtafQ1sg2fhQDj4rVUbYQJNBLw0aZftn5vg9BV0nx5hNFi0JMKsGykzzc5valRsb1AYjlfTIpmPJJlc8NrnxOOvBLpeQ7P8Ib3J9U6SILgqvPKXn8gQzldmXePUg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by PA2PR04MB10240.eurprd04.prod.outlook.com (2603:10a6:102:410::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.28; Mon, 29 Jul 2024 20:18:55 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:18:55 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:09 -0400 Subject: [PATCH v8 02/11] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Message-Id: <20240729-pci2_upstream-v8-2-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li , Jason Liu X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=1387; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=M9wO2WI/42fd1UXuH4/xq4IS1t8W2AIoBjreaGqLJqo=; b=btyzVEu7eaMJllA91jP4QDpf7klL334SGxCNLum/F0kgX2SlLLsuNDQMFG+NJe+YA087prVZT UqcnjwRTM4UDkK7+igOUT/VELY8DefnOToZbQ+36udd6REe1zac1i+S X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|PA2PR04MB10240:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a63c99e-4139-4e55-ebd7-08dcb00babaf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|52116014|366016|921020|38350700014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?pkc1Nc98zPQAYWA+VxqouyyqiOK5ubt?= =?utf-8?q?DNfvOBRZi61CbVLtMP/aVz0D/SJW1UDvDCiEnGYPtUaw2vvUh18X5vHE59YXgJYCZ?= =?utf-8?q?iOURf+lHIu3hCX6vggjAB1TQtFA9OdMGYeFeVw19/MC9/NvGadZBDduJuvS9JVxUI?= =?utf-8?q?eQAUiye/Z9YamZCMKmqufbifh91T4Xlcm6Cj5El6V9ES5C230w1Uzp1vcuyX70K6S?= =?utf-8?q?MVnTAML+t0BrgC6gRHzuIKbcyQ8vZRsgWXxh/X+mtyoOGq34jieMjy8p2v8H4Q5MN?= =?utf-8?q?86AZEni4Twm/jMpMLF1rYWpJOl5hT1tkQHITzQH5nYGgBDbGd5jG4pT/g2sdtQlRU?= =?utf-8?q?n1SHh66d39cSreUAekItu+A4vZMxlGW1H27m1y/zOXBKy5U/IBaGh9g3UgwbFrNLr?= =?utf-8?q?6eOKWHLRHiLc1hgd5VbkEOEH0Nc0DkAdfLuisZXFaE/fw5S2xWa1uXC5y35TJju+q?= =?utf-8?q?z7gCdBd74hiaDi3ZhdwPNdwHLMtP3tQRjpiNXJmAJLRtBdKl6sntVOdDqo+9Irm5m?= =?utf-8?q?+/4Mt+fupIkbjdtQxlJbXZ3hQ6tLeN3jCYS276qDQ+8fNH2058k/rCDX5fs9CHzbU?= =?utf-8?q?zI+TNQFiOYwpIZd20ESMXwmt+zJT2baNgdlfiQ62B1fJFZKy24YAwOEX0kB91vFM+?= =?utf-8?q?MyHXnhgqOqqbL160aVPs81DOrK7o3W72jVmg3nZSVGkaBP2LVYrAVUzv6Lihy5rE3?= =?utf-8?q?E4zNuo7mfxuhfxsQ8I1LV3YRseteilfSyuqfW7UOenJ4ekePFB7k6z2SXnlq3wV+r?= =?utf-8?q?H+VTbMz0aAd/r16nvwisDnxAGmuJsSi+DqHJB/uqVbas/rGCUbzForBIgMMyBfBq1?= =?utf-8?q?XQkgihqH1IlWtMc6SLDDWudhWqA+unrdO+svJ/uE+nKWPnGCRYj06wL3pgnXzbIN9?= =?utf-8?q?/IhiLjfe15cTT/RowP2xnrfECLgOHOaLkmXcMjZ6YoK3jIA8d9oxfF+VIaLkGpPTx?= =?utf-8?q?mCrXVg8TlMsWu68ii+VS2HbW7tesVN0xHL5fcIfV9f0HZUfNNNci+SKw/JHoLl7PC?= =?utf-8?q?eSnOxCBRCwDu2IPsPkBmzIN2EbdIzMoIFDQG/n6X1EHuMvWQ3IQ+r+UEYTervco7e?= =?utf-8?q?6F5ngPxmuF2heuQPgHXFIngBJ3K71oBO0vI2TI9qa8/1WxRBH90OXdDdjvx1IyrMi?= =?utf-8?q?nTBgeCIiKI1jAy5ubpVdch3nbkiRL9/Quweyx1KQnM9gv4cj71suVryc3d4OYWjQo?= =?utf-8?q?gTfjyWY9ihKlFqbVTGb8bKhAWooJVCJqeBfnzne2PR4gvfNqCXPGV+vsvKeSjHBdn?= =?utf-8?q?U9HA3YestyVfu5gv44a+IEb7mtYWNjIwZOyZiH9ruZS8p9H3FuDHeEpoGywayVKpU?= =?utf-8?q?87oTgtFyDheFMFLdK9EfAu2bWCnPMOpm2HZHSSmWEvsk1h6Rs9WGN2Q=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(52116014)(366016)(921020)(38350700014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?NeJQ3K7p83o93+Q79l+6N4NDCSF6?= =?utf-8?q?hG8/EegQabWfgYzfyjf1hl4i6Q99YBYaKvC91IVKxFO9QvSIjuw0uhylnUbQYRKYG?= =?utf-8?q?3SjrM/+2XKDl7OnxPskVKE5laxIQbOKwa2C8CNCBUhadF3+Fcu+fuw/BqOkAC6sUP?= =?utf-8?q?0x/svywzXLh0HUaHXUESsAOeHhAoIYx0C4d7SKOO3STwG3vPfwiMNlqjWANWinfF1?= =?utf-8?q?WuwxfmzN4DsbnAfgG6VwsQ/LpxoO8VqghjJJiYWd//R/QIaU1G4rVZSrSi2gFUar4?= =?utf-8?q?BKQOxfPpXJ/C0VMKG2oBxuGyqhqEMFd2KW9kl4zWKDQv8w+RmKqRduXBptAKNX4cJ?= =?utf-8?q?xf+/87Tj+zULACDYiKIrmx1YtVcVL+yc/EAVYuL8OcfU6Wse+qoVA2B9G73+jF4HT?= =?utf-8?q?YvFnt8J8XEvzq+EPvExXT1ULX1VLN26rSnOIifmCKD0MpzE57rUxY5wGakTmWWsdC?= =?utf-8?q?zTCQwncf+dHXXCgbRy1I77+8z696sbMyGDfX0iz3mZoSedZ9BfrcMOOhFOnL+6SW2?= =?utf-8?q?GNKYBw4heWvdIHfB0tZ1PCBDdw5TdxcrdIfoFBqwO5gl753RP3PaLNbLoHdbmInbO?= =?utf-8?q?rzPbvn3lghz3bgNE4ylVtpLCl2fR9D4R63hMgiO7uM5q/3DH+n4idFbukqDtqnHL5?= =?utf-8?q?NbFvYdbekAKHaamuRSL+oeKD7O8tL1hfbwzOYWPbGHJd5QGy53WSS6D/trNQ2DcRj?= =?utf-8?q?pzcYvyyJgNWRch3fQWKW4He86G6pO28tvBkkb1jpiwG4XGNZ9RKcEIa8U9BgFqnCe?= =?utf-8?q?SmiYAzPWHaUV6yB1HAfDvsFVmh4p94oRVEYgh5P9bVjhN0AQ0rIMFASW/NLk75wFr?= =?utf-8?q?Nl8eOnnMEIpxEw2TNFBPjj47LYQE7WVfi48ojwJCI3o5R8cnybcX0z+SC8hdCbMFQ?= =?utf-8?q?KUpWUr7vRCe80O0PbJpaQcFLqm4prmRp3LLzs5qOQarEt3hqwMCbpecFMwfbOGv3k?= =?utf-8?q?9JdEAjwQOPUtycPM2QzGTHk2puvLbIYRcs2g3eyM36m+IFDIfQBK3neOQk1NIiipf?= =?utf-8?q?X8/bgbLTpe121z2Y015hfC5egtdKbFOqvUzbTBDmfx1n1dpeWXkYB57548dLFjQIX?= =?utf-8?q?dZMvBLH4il59s3k7yTsV98MFbw/ByE7vR6RR0PJPuhzyD5oZdp+VNxU3MuaNnkeQJ?= =?utf-8?q?bukI+oFrcuiEj1ifWuiCKIDynU3k+jbByUiLzuZIZKxqxqzOgItle0MwCgPZmyOWx?= =?utf-8?q?QsdZICWXu+I77VdF9r0utGA6OhALeISGmvvi/zT+hvdH97hSqQGDyszFXO6zzOWtX?= =?utf-8?q?JwaVXM1godr4VkIokaOnM8ZQnPx5o28jSkm+VA9Ih3P/mJOWVShPs6AEr5GtY76Xd?= =?utf-8?q?PaxzgsrEaE8yOjR/jSqWwQaj2+WCnhUjukLicmU6MdBEv26stfLV8EuSlnT/hp4Xz?= =?utf-8?q?8DLVEXuKqxgxgrPCszjX9/LCKFVlw2h7+odhoRyP9ctWWEftCQeBqoxRAnGjpp/Hp?= =?utf-8?q?WhK6y74VRGYMXO4Ma4wn/QqMTQBtc3m3817UuCYOUxGrI/RizaUxASj6p6KSV/g6d?= =?utf-8?q?teBcKT4sMhpa?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1a63c99e-4139-4e55-ebd7-08dcb00babaf X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:18:55.2355 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Zwchzj6z3QDQDnCAYqv5bPv7XPb8pPB9N6PMHxDFCagMKTfIOO8JtYjE4vKfTX05iqH7XTrOOuniE+DukQpU5w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA2PR04MB10240 From: Richard Zhu Correct occasional MSI triggering failures in i.MX8MP PCIe EP by applying the correct hardware outbound alignment requirement. The i.MX platform has a restriction about outbound address translation. The pci-epc-mem uses page_size to manage it. Set the correct page_size for i.MX platform to meet the hardware requirement, which is the same as inbound address alignment. Align it with epc_features::align. Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code") Signed-off-by: Richard Zhu Acked-by: Jason Liu Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 42fd17fbadfa5..3b739aa7c5166 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1113,6 +1113,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + ep->page_size = imx6_pcie->drvdata->epc_features->align; + ret = dw_pcie_ep_init(ep); if (ret) { dev_err(dev, "failed to initialize endpoint\n"); From patchwork Mon Jul 29 20:18:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745667 X-Patchwork-Delegate: kw@linux.com Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2069.outbound.protection.outlook.com [40.107.105.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDF94189F2B; Mon, 29 Jul 2024 20:19:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.105.69 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284347; cv=fail; b=NkRqhSb4BLiVH1GRt/dMt8NuH9xqzxMstNkZVRa+XqPQ72vXvq51ELaYZCVBTu0y32jtkOBEp6IZck8OuSndQJDiSaZLff+JYnjbH2Y39MuPI6y6ViMiZRh2uVmV5gx2ht7ZBNhBisybDUnTZFSl/LbX6RtWsbuLhKeFHp+oQHU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284347; c=relaxed/simple; bh=YJ3hjZthXXzphaK3hv8FaNx6snvHLN1pAh0ZRKuyMgY=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=e1BTjebrxRYA8YAjGJ2s9aK1O3KppZkxNQXrZiIk+1Nl52eV6xtq8/UqI9tX2Q+s8tAQxFPr4HLEwBctXoKBveSmgKwq03M2c+ijGgSy3jnJrpqgjwwil3ackLsRzUOPy4YsnnJY7DFMzk8GKqWPctE8/8j1eIPJv0oW1cEMBBU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=GYLbNRhv; arc=fail smtp.client-ip=40.107.105.69 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="GYLbNRhv" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=lTigqMGE2kJKAZ2EDGZnIcgCC8pOdeejKS5mr/DVDnAOJsT19rCsvK5fTvzxAYRjwNUdEeP3HVWQwiTTuaroRns0P4jff7UIupZdP4iBwhUklRdSj5VqtRDgVvU89YE6ME1rrsVRUpp+Z2QjFns3Xcyu2qJwM6ShNKSei//sIjyhxgoeJAGIhRO48lHM/9oCM0TmyzW+NQCy/sXxX5pvOBJedWyK42tjFx3afaAacl4QmI5zjCIM7awyu/Ya479I82F9+feIueCCQuXZ7iz+yEvWzhlBrjiB20aZdXdxjubgc29ij4SQ+wV5zJQim2LX9uVo+7T5JZfWc4Csu6mRpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=F/ED5YZ2FyvpBvvH5Xw7f4z7V/rcD3E2Y6xkiZJeXxg=; b=lY2CN+T2kknzAMnC4BBet42lL/LZcK0w1lKHyzN8d4jWhtqoX+y8PcG8bGMEdgRwzegmknyqfizZtULHjzKG6X+wlTAHxGBAWQn6KQ7dEtgOGJQJops0fVgZSpVejxcML2BJ6p5MBZMIxxZsjal6lUlQprUVdulrAQXiG8X2M9eRlYmRLCDPzMVyIwgny1McSHo8a05gHhoUvFcaOTPX3fGoK1q2ZmnjszgLSycgxbGi80KZBEow+gCzOySX+yenQcxUT6cLpzH6zw8eu07XjFbGB7dTv/yQp77vvSPLUfUnS1HDcGwiEXVYMpeZIVIWW+UNZ3JwEkFuMVOiKWVGjw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=F/ED5YZ2FyvpBvvH5Xw7f4z7V/rcD3E2Y6xkiZJeXxg=; b=GYLbNRhvIUfDH9vcyzzuT1Uwcw2jyqXRRL08PHsQsWVnH4XEjELDon0HndSeJaTL1rW9Zyxaro6MCB9F57HU3xBL/qfG/kcCZ4sQcGS42b/e/Uz8og4ttrN+r2PPWBCnDYU3S6G7AxOnpCkT9So2HsgoyqrhCe/5CUAoTR3lfScHoLiTZwX350JbVBCAL3bh+nblFIg3+Iy+66bNlVT9pCEei5jWK/j3e7G6btupkpU18ALy9Wytn6zb7A7009Y8BlLCLv+HzUKACnh9M3z9YX+K1xiHh13rsrEPCXD+S2yk9P2/oT5ta2qPBZzdkjsS8xB/FNaxI9X1lSuttMVTBQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DBAPR04MB7382.eurprd04.prod.outlook.com (2603:10a6:10:1ab::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.27; Mon, 29 Jul 2024 20:19:01 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:19:00 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:10 -0400 Subject: [PATCH v8 03/11] PCI: imx6: Fix missing call to phy_power_off() in error handling Message-Id: <20240729-pci2_upstream-v8-3-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=1233; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=YJ3hjZthXXzphaK3hv8FaNx6snvHLN1pAh0ZRKuyMgY=; b=McwapCnzcWGzLgj5Jo+5YVQ87aDIGv5Xv81/R+RT9HUykd0aR7XfeS2pm+/JR92l0g7J5y+jb CTKd58TtbD0Cr9MMJsrdTZ6PXgb8DFMzEVhb4WxJs62ox596YOHOMH/ X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DBAPR04MB7382:EE_ X-MS-Office365-Filtering-Correlation-Id: 3434539e-b732-4c7c-aead-08dcb00baf03 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|52116014|1800799024|38350700014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?q?Vkc8pM9Z2OUx+lMl7VsAZRCQ7+vaemL?= =?utf-8?q?XbPuJJqKLayBTt0hl7eZsg57BfwITE040rKxZjPe+f2Hzd6NLeu9nDlInnGUFGKdq?= =?utf-8?q?Qkdjesi3Ce4nP72eLGYoo7pakFoF89u7G6VBQRGqBJ1w/oK7NB3qPfBfa6xW/yvtd?= =?utf-8?q?RJOGIQv1rUQGMTH0YzkIJimOrs4XpgRcNdE4b39kIQdMTikTUKm8zHinhKQdRqKLu?= =?utf-8?q?PbOZJEwXmheXL7McdOuGRSqWFL2veIV7IuGN1EVORqe5yyZuZuZaHatYmXrjWCcfP?= =?utf-8?q?j3kkupnCjDQrAz37GI9wvkd9dyoVNzwqcixPgLzqVaqgasCSbRnsZj0t3Yl/snOcp?= =?utf-8?q?JX/R1fC/bwedPMV7VbNsTn9UWn8/pfLK+cQwjfc7BYfEu6EHl73sV/kLyna1yGvty?= =?utf-8?q?TYg0HagtwMfzrzFOWaGtufV/bXnNGgslHDzieZ2mF7YECzJp1CKnJM+ZWtzuve48M?= =?utf-8?q?/ZnSr6kYjTqIYxmnPpk4+rYQm103p+SuRRQ0NPEMJ8lVvnmLYq9ZYWL8PhYRT89Ia?= =?utf-8?q?GZOqhpRME+YiK2Utox9NW5ciw3tkchcpyPn9KfPJib5Aky/BQJeZ4ZCKNQbkmGtwX?= =?utf-8?q?392JgLdSD2+EcHUdpDGJJumyCAn6Mw5UecqknUumApASHm8p4lc1/1r61h2FSj6gx?= =?utf-8?q?iLS3ooBXu5+2RofJHPCS+txoUdO7t5BC6DyfAu8hxyqtp5zQytzXMO0L6XiBt/M1f?= =?utf-8?q?ZFpDTdqFxHS2S0N3JppFAIDv1rM9Np7Vck1u5ZwLRbXOHOngaPNxPwjEO4KXkDEt1?= =?utf-8?q?gXix+x4MHIQl0gpcIkOy9Uqt/sy9VKzEJVBKdSyCbKo1kZngthcXgXumQ2UOmho5O?= =?utf-8?q?Af8RbhhQmlsZroa8/hXaYcEdyvKnqvanqVtnLFenEYL8kuDM3iRiaT3F1eXcaznae?= =?utf-8?q?lP9DsNZLE9bwOHP/jFeM2WSa0pdYNBSZqNI2+0t3STh+Zt252s8pLUbsB2Cs9mTTQ?= =?utf-8?q?RRKGDPkhUc3wW6ChRevhKG+De798R6jt2OhX3wEiJKC59VSJTlNAGZnpeLKX523WD?= =?utf-8?q?yohx4DXO8lCv6MPX3NU1jkTzMKP+wAZXOddUcX65885v7m02VMLoCfv1twZhyYr8K?= =?utf-8?q?WppYToPYDPIjW0AcgsWZYQRGGD7gxIXx5OJRDKyC/QJnSyAGTvC5qrTlZweetECcv?= =?utf-8?q?v1pK1H9NWifZIp0PbEMxLMO5dcJFX+lDcNcHWtnMxWXaNYxGorhmpJjnp7RdSND4A?= =?utf-8?q?Ds1dnfKdm8nhEIUEJl1Wr/cWdUUSLCmA1GUclsuxtCo8iuOaN0HqmRyOxuVTtBz7a?= =?utf-8?q?7q8qZnri9WAUQRoWzEuxfMAV8qPksz91WmkapZgp+r8oBzKryGXmmgjuSt4PB8Yv1?= =?utf-8?q?884MrdIeZSQVXIhu7F8BU8t5kEi5ggwzOs5QZ6512kADQk7IU7p5pjs=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(52116014)(1800799024)(38350700014)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?lGH7fe/i3dHjQ+3xRm25INFZgG3D?= =?utf-8?q?RTTKWnG3abCgV948Lm4exzXW46deNduJtwvMo7wRrh2e5QTqo3M17ddz2dacpswzu?= =?utf-8?q?yDkGRDJSOSNNnQkfxXyc/s2ByrXOxFHYB/6dVyNMlp4TL5ebkZ0FpflARmT4JBrTJ?= =?utf-8?q?0cgv/2HeDkKjDdVtxUn+5eEdX+61DXcl4WNtvRztpB4ZAARzsfmfereqJ0upHBQ7a?= =?utf-8?q?lIncFrVQYNrKuN9RZ7HioY5p6wsof+VGNl3eFCBjRs2wz2QJOoXk9hvH8NX0hNUcS?= =?utf-8?q?1zRYl7KkFvUy5KkOZpg4NoXy3dxmaUfQuGw1dTNSWCAXrtCnQ5VTIYadiuqKw4X00?= =?utf-8?q?TMcnCdrHH0dSrfeejnF2XFpWUvjBRhp5flan2AXfzIV0NH5wLuzooov930JzV2GXL?= =?utf-8?q?a+FjkzcII9eYcqT9CYtLykHh70UTVweIfdJw5nAt5vaopGhb0oEuj6jG+USruH+oi?= =?utf-8?q?mdjlgjQ/0FXws3u+Wq90Cse8idsVT3qaknWqMdBMG/gUcGNd39gr6MPKcfPpR7lID?= =?utf-8?q?nmMiXaiaL25TN5PMYsFbMsw8KTO/h0cYQlHPVWqUHZYOYOcZGDGZpjAECu7z1xloJ?= =?utf-8?q?UOvkqzBxt8JQ0qOQHMaI4/qa6o7HMr1x+jB2xmcCjH1aJQba2IHKAHGboinJiPRMe?= =?utf-8?q?yqClLKRLtZh2XQw45QJi1rjIxduWAe2xrUvoKcIMw2XCt9nf7Yh1g8Vi1rPAR/oAU?= =?utf-8?q?HaqrZRovWtOyYrT8CWPSIDvhfP6zC2lkw/bAaeVpz+49WhsBJyRNPZI8hcMRmwZTQ?= =?utf-8?q?mtL+MFt33cRLLU0L1vqUALk5GZeTkflvhNqz4vhzWnspQtYltLBMU5BmWQBVFwLgT?= =?utf-8?q?oFrSAl5V3fhBojM7Xz5gtwhYbk9YHW9JVv2spDSDxwdT+bRCKF//QJ9Gt4rQOzoEf?= =?utf-8?q?pG7UzyDQDTukO6eI44eZO8cbBqr1i53c9MmOGsijdicIzQ/TSPWDvCGuUwFjxFU4N?= =?utf-8?q?Zqw2NkNZ0FAILKU82/jDrTVJhlWOhiwajpeT2Jzwn8T8411hHWF2efdaGgZB0ACi7?= =?utf-8?q?SvI9dZUGmN9hhIY+UZ5wwrhzAYeAVUOjeFc9PkYNMqauUG5LC/ciReDZlN2uKcXF0?= =?utf-8?q?JM0zTIPbIlrPOGfnZZxV0+lWw30eMd+jwbOeQ3LtvSiw7VYZkyydCGAessSG1wR5a?= =?utf-8?q?zlxsiRB1O1+8kZXqbekpBmf1yV6dsNuMC/y6cmjeu6U2e0oABdmDYt6dKvyN5KwaE?= =?utf-8?q?a1jGSXsVBJh/R07dNUbhuuSgVNkVViyQZfFfk4Aczd33mq6m40YdSe3FtYRF+Jrai?= =?utf-8?q?ELT9JC54Yi3vedMLszjxrYInCxl08G4bTKw3EgJhTcNK7oq8ppBKiPpCj6x07yuZ6?= =?utf-8?q?AcWhArsiv+gu39Ejwu0I7+5tST2Z3i0VrxK5uLhB3oQg7IfzN1WIc7R3+XdknTHqY?= =?utf-8?q?oRavBygdSkUyuOHclCbRwb+DZL0/MOcP2iCXcMGVOkuo4c8MSzZhrj258H1Tnom5L?= =?utf-8?q?TfTSfyEIrF0OOh/AkoyOa/XciPG5NuOKNLjJj/0paYlfkEbBl+Er5P2YDbf0OnCww?= =?utf-8?q?7Ia/Ga3cADrq?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3434539e-b732-4c7c-aead-08dcb00baf03 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:19:00.7840 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: E7lrulLe2I3WDatlV3ppcpSpUHxcEiV0np9iMSSJZ1NtHuqlmPPtWh0gKa5dpQvPp7dWszZ2jwd7+dYsjmqbHQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7382 Fix missing call to phy_power_off() in the error path of imx6_pcie_host_init(). Remove unnecessary check for imx6_pcie->phy as the PHY API already handles NULL pointers. Fixes: cbcf8722b523 ("phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on()") Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 3b739aa7c5166..eaec471c46234 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -953,7 +953,7 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp) ret = phy_power_on(imx6_pcie->phy); if (ret) { dev_err(dev, "waiting for PHY ready timeout!\n"); - goto err_phy_off; + goto err_phy_exit; } } @@ -968,8 +968,9 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp) return 0; err_phy_off: - if (imx6_pcie->phy) - phy_exit(imx6_pcie->phy); + phy_power_off(imx6_pcie->phy); +err_phy_exit: + phy_exit(imx6_pcie->phy); err_clk_disable: imx6_pcie_clk_disable(imx6_pcie); err_reg_disable: From patchwork Mon Jul 29 20:18:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745668 X-Patchwork-Delegate: kw@linux.com Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2082.outbound.protection.outlook.com [40.107.21.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BCC118D4C3; Mon, 29 Jul 2024 20:19:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.21.82 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284355; cv=fail; b=Cy48F2Y+UpYqE6jqmz9j6BjJAGzShyw8bt2KKiurjLd4ljrjM6+p9ageTHJ0j7bcDQabLQrG9EzGYWqyBQHIiSlL0cQ0tZIKlbsG2n38Vf1gxO6AJxmanL19m/NFF6q+l6dZEZbjYYKsFWAC0j/WjgQN1ZOBnnSTnvZJurKrwYw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284355; c=relaxed/simple; bh=6gE0KZLzZJ/K8LOa6mRvEFG2bepxNOaYVhv6blglIdo=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=to370PcKltGJ/tk7Yrq6+rFE/TfYMULZjVIo5lfzEIxFvNLM2xEPRLjDtJqDKbT6ApkIuuyV2qj2cTK/k/+hS/HYXYRtj1MSUfXLddPFz8qTLpQF1F4CrN9iczqrF4ft3TLvPGfKBgPuFqPr3kWDbFoVFxAGI9qQjotNGzeyqLM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=d6qzRRy0; arc=fail smtp.client-ip=40.107.21.82 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="d6qzRRy0" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=bPyvNWgIDzPF70Y0Sp8Hr4jD4piVUGt4qRRE5aCPSx9r5iPkkeR+RT0kU7tzonpZv6jiYljImqwtfO92OBmnI8ps8CDK76Aif6ES5gOtedeyL+B3up8WZ+1Agu0tJ1uNhMLom5q1w7lvFfHf68dbzANpuvFKbTOrU77M5jg/LyeGboqpfcUe1SKik6eBEWdA/+Tdf63XT/ewmlBlAw544A5bk1tjas/5KokUonHAaTzoW8qtV4N76Yzgw67Db7/frCcxo/aQSZi8+aPhYrG9+2kBMpfJsgV42yf+oyuR3mm2uK1gbaVPHcM7s/Hs2s3p9BiXB60eCMumuyIorPl39Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JrPwzF4xhQ0Yu7MB3SHIMxCetbC74aOZK6FPEPgSsYo=; b=RmnVOSUCGXxe0ad2S3JUUuZ6Mc2cgAeenQn/0RAA+q7ZBspL3V6RvMMgTwm+F/Nd6IukxXBK8qp7GnoA0M94snmqn4hCH7wWVPI84uT1pZ2+6tsCLNM4e8nU4SjQnVuotjz0NGZNNW8TKDEcerL5+3zQnq2SspqDrJy5MGbgNl/X48Hf6oF1T/8Sbu2jAtMkhufb1cJOEkxhMccBWZBPoIA3BW9j6ehKDSuH4ZeKq4Njjlp9IYC+fJCfKqhfC2VGLejVTxsUO/A2sqEj+IZJjHnmcOAae5ta9TCdoMSpimoPRI8DXzILD24zTmy5eeRGY6dZVZ14FKHWgdw6vNvtKA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JrPwzF4xhQ0Yu7MB3SHIMxCetbC74aOZK6FPEPgSsYo=; b=d6qzRRy0M6bb8kNHJj/mjcm3mKU9QRHQqlEFJIg2vQ9CVR2jL/DurpgP45+mP1H5oqQUJOkBuNDWkdyN4dI3Rfa6BEJwsne7m9pAqhASuxWvL5J59vZecexvBHdQQrCAfaRgtkoIvmpqJM4U6xGcOfUsUoJWlhMCnPmwDI7ky4pcfY2dhEu2I6k30q2koYYFLD44eYpAq912DARFCnx0SFEtWdRb9fZBto/ju+xr+gCUyL9s0HwqFzVutvJDtxS75E3TD/o+2dJrN29eQ1G6bctMBkQz8SeWjdkpACRvyM0ECaYq8nJoDY6+EE+5kVXVD85DsVXS2024DnnrMQLrMA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DBAPR04MB7382.eurprd04.prod.outlook.com (2603:10a6:10:1ab::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.27; Mon, 29 Jul 2024 20:19:06 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:19:06 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:11 -0400 Subject: [PATCH v8 04/11] PCI: imx6: Rename imx6_* with imx_* Message-Id: <20240729-pci2_upstream-v8-4-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=59275; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=6gE0KZLzZJ/K8LOa6mRvEFG2bepxNOaYVhv6blglIdo=; b=EyyEGkhWofTgRw7jfrvzm54OZ96eRG77+F4F7T1ArRwMQdxONoXAD0cqlezr8k8rmO/qxNrBo Redca4h2EsqDUc3ZOqSbMPQV2XGGUXGC7E+bLmvjaopTpSnzeroAeFW X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DBAPR04MB7382:EE_ X-MS-Office365-Filtering-Correlation-Id: 656e8336-bfd5-45e0-2613-08dcb00bb25f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|52116014|1800799024|38350700014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?q?39q+SqYjQpg8KSzmllmnnA7uw+8W9tw?= =?utf-8?q?Wvj67DbER3feERbiVFVWjjncBzTs6IcHN/rILF2CV/mssf+o4CRJwNfF5mB+OYEgG?= =?utf-8?q?pq0zlm1SbFbxSmxi6XPt2pFZPuDuUyrtD94+kU0mE1MQhgqiNKlEqDjFUY2tzsH85?= =?utf-8?q?he0+5y4/m3TcdqnZNh3pJjUFr+WmkHh2GcnBDd35gKSxlvxlmf0v1oUmDJQ4OQZXb?= =?utf-8?q?VtrVQrvJ0T6+gevIpJrDHF2O5BHqqlIQTbPOoPM8Bgg0RVQxYYoWOhVpdPrGEbg8h?= =?utf-8?q?2VH00hMSKe8qZQmhBX7gseTCoeMbdKOmk384mhQI26zbQzrmU+VCgsPSF/52O/+jj?= =?utf-8?q?qJEMv9c31BsVu/VGaB0z7ktTqXoO0cxmLZhUVVP8YYTjz7EnMvf0u6zDPVKv3M6YP?= =?utf-8?q?SZtVXN+2YsE4xhTtkeXC0Ip1lRuFyPX6hT6Ru04OkcxtPfCMLDarTTY3y+id66mvk?= =?utf-8?q?85Su55LTlZpil2LJrgxRIvvuRoz032n2cfDG0ImExTi3CRmp2Ju1985e+hMyqht4I?= =?utf-8?q?LKY4LG8m18zzUxmXNZydRNUIwd0YPD40Qv1QzCZ1wZrpAj4rpsWk8C0o1mHHYm2fr?= =?utf-8?q?kUk4ZF95cL9s5zy31imDWCeDQuqZgTlK15740EsiDzVJvabrYiPq96RVV2Zlib/GC?= =?utf-8?q?H9PD8mwYc0f8aOB/DudrRTVX+1OSaylKVOCn+ykswRMDkCeLP2w0y0OgCxzCLobYj?= =?utf-8?q?GgETeiS6/M+FwTKIxNezFKtVIduKP7vRjhN1s2Z5AIhyTMuvuDJctSh3ZnETX/XJw?= =?utf-8?q?7uXSaAkidyFcaliVgA2eDsvXExOnjkVWJPFfZq1QYnrdwjALjzR2Pw2pVvpeKjWv3?= =?utf-8?q?eC1mjtmQ84wJ275mib68+/+roxWm+K02cHLrBEd7JkYZSisHXTx6Q1YKrzNFyn883?= =?utf-8?q?guNlstXXdwUvdGrLi8aBCQwR1pqy+nMV5Hzewg3QVXGYSV/ZXAHr86svcxoAmbUuq?= =?utf-8?q?CyIvDZjRJZsraSzS3y6sqM64RJqWyyIF8xLefeoriYGpu3hWunnV+Ul7Kpl+jze/X?= =?utf-8?q?Tr33C6oau7Oq8jCxL6LwETLLQVw/4MLZTV1fEQhlNawUXTFhe5/dJsFRJfJb8aXmO?= =?utf-8?q?ErDdnmj6IWP6ZL5Xr/OaEx1XboKLxlKmTu2h9VHTF1TgXBgp4UW7qrtYiYUIlCKl9?= =?utf-8?q?8yInO4sk8EC00xwNT8nv4ZEsl5pYHsjj9KtRLze1T1m9XBxjplunA9ZhaMJVfYm9M?= =?utf-8?q?TrYvr8+j77tQYYWWjYL1NJ7BGwmdWKLHAeGD3Vitgh2IYkuVdttaZhPUWSDDbcXpv?= =?utf-8?q?vR3EVPo2fKXrpyLCVxbiPaEU2/Ivvob9srC1PAHeB4QOijjVvASdrT00GfcWpNLXo?= =?utf-8?q?sM5w54IMTb3Qvl6BYB4rBx4w3cki1ZcpwF4mY15PD5GBLgyskxSHNkk=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(52116014)(1800799024)(38350700014)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?n8Lo5mxh2bvaEC/JXxD2TcgaUnft?= =?utf-8?q?BCroPfZl34HeuyCjhuTe4NWhAQS6o68uQwT8T7GqQHsxiwT7XQmM9xcH07ieZc9ac?= =?utf-8?q?P2q83BElMpogdf8vEVxbKdghigcFGz4XpgEm1YZ9Kh1MDhlT5eMmKkyycCUZS0CVm?= =?utf-8?q?1xTWt33PmVxRFRbsREisJRZTc6hXYLZLxU5OMgNxI/Ur+GeVerPvcBkc6+bEmPmKa?= =?utf-8?q?LIx8N7jLuKykFMbk5TPRRDM9bSKLm/6QaP+GM36EWai69e7emdYGOIIs7bvayWfHB?= =?utf-8?q?nn5IVPc6MvHs7+CqWezXfGkH/W4ZTW/BLe/zMcz2xgHiE26H4IpfF0DMIIDZiIk7P?= =?utf-8?q?CelGMZxn3rxDYDw0D9wftPTqVKUquIhX6IY5LWOuB5Wubpy9KZ26bZhPpe5YVokMe?= =?utf-8?q?UsD7ztPV2x+0tmxe7+rk++Xa//6mxRt/UVNsnEasM7qTUpkC13th66Q3EWay9pD5Y?= =?utf-8?q?vhhHXkzO4mt/f9WLFFKYVaLIdgLZeeR3+JNjPJBW3n3F9ypLuUB7Mvds0DhBc6isR?= =?utf-8?q?cqPjwr8ovyWioazZcIlciPd1FWHlPcDsYHCRYJIgyMVA83bbX03faYU3jH+GtNMcl?= =?utf-8?q?09I8eB9Dvh3WopBHP3Ct8StKNmQcQ1x8zgUqGCW61t1A3a5+kO6MS9oxUADznpCBF?= =?utf-8?q?9R1rOO/aMxVvez4KyHjaEmvSk5Fi7tUL+tUpo0C9uTdRRSgITMgPOslAvWW83fXnw?= =?utf-8?q?ZF95OuJpb48IJ+Ku0y4zM4HGk0bsuBkPoisPpoon/qZEslkCAOsGWiVrIarLqs4QD?= =?utf-8?q?m8y7JTl+nEfM6VOpI3QHbic65vFcUgbfwEbOu/LFSiFOE0hraN8DY0RWmt8kzjlg9?= =?utf-8?q?XXruKMx4GVjGOA5V1K2IymRj9foQN2uxb49kBvjmaa/nwmIk+6XjsH2CBkGOFjOPi?= =?utf-8?q?LSIJ/HjIOf0F1086A5eEFzUJHDSATnniZl6F81Iwb13lgChtrfKoiihPUVF6WU7dK?= =?utf-8?q?3V+zmxD30woXjTbflnRU0ZHnr4cVpl7p5uLgWp3gHSsVBhfADN4mg4L15dMBfo5uq?= =?utf-8?q?/39M9PQEU9GgjSphFG3Pf+iMroZow0yZzd40Jtzo3RIaI2SXVkH3cnmIidQjJGb/S?= =?utf-8?q?NPfCGE6jgYJuBj84fPvnm5IGCiej0tft73fdz7/kk/wGs0RnFQYXrvYS1X8N+r8XV?= =?utf-8?q?b7XeGHGx0c7Zw1Y5c6O5qpovP+Xju3CUhKI8DSHejj4KZ6FBxDe0wnFk07SiI1TuI?= =?utf-8?q?/Qo3ymzbdiuXT+lIshvJWALkanvQMVHXk3f4L+9uH0eJnRs91w6IAmwJRolNYBqWL?= =?utf-8?q?Zi6Q8UjFFNxYK8Sj9XaIIMq5Sw8TPukBjeUwcfiBH0y2xZJcSaXRx54tcl1f044Zy?= =?utf-8?q?a8GL85toWVgRIhJr5e5iy/tDK0RzMrO2q3fxXiQKuUURiWL9k98jnO25qDV0pCW0I?= =?utf-8?q?oan1Aw/bvoCk1e6QByARxuT1uM+xSekO0yGMRv2jZvsCzKQjXJZSV1PUj2orlVwmn?= =?utf-8?q?YCFQzxSTbagYL8tbXNZgYQjK2BozEZiTj9aZaqlFZaw+za1+k9IHMu/N5Wh5xThbV?= =?utf-8?q?lVEn3gzriShG?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 656e8336-bfd5-45e0-2613-08dcb00bb25f X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:19:06.6450 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4neGh53ghXsZtsgVXZrfuRn0sn9k+UscLI8g7zUNwEfaLty6fhrEYDvGJwkJpnavDmPOsqu/+6NBphkeJwzzyg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7382 Since this driver has evolved to support other i.MX SoCs such as i.MX7/8/9, let's rename the 'imx6' prefix to 'imx' to avoid confusion. But the driver name is left unchanged to avoid breaking userspace scripts Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 748 +++++++++++++++++----------------- 1 file changed, 374 insertions(+), 374 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index eaec471c46234..443c7c75f2842 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -54,9 +54,9 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) -#define to_imx6_pcie(x) dev_get_drvdata((x)->dev) +#define to_imx_pcie(x) dev_get_drvdata((x)->dev) -enum imx6_pcie_variants { +enum imx_pcie_variants { IMX6Q, IMX6SX, IMX6QP, @@ -71,25 +71,25 @@ enum imx6_pcie_variants { IMX95_EP, }; -#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) -#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) -#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) -#define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3) -#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) -#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) -#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) -#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_IMX_PHY BIT(0) +#define IMX_PCIE_FLAG_IMX_SPEED_CHANGE BIT(1) +#define IMX_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) +#define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3) +#define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4) +#define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) +#define IMX_PCIE_FLAG_HAS_SERDES BIT(6) +#define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) -#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) +#define imx_check_flag(pci, val) (pci->drvdata->flags & val) -#define IMX6_PCIE_MAX_CLKS 6 +#define IMX_PCIE_MAX_CLKS 6 -#define IMX6_PCIE_MAX_INSTANCES 2 +#define IMX_PCIE_MAX_INSTANCES 2 -struct imx6_pcie; +struct imx_pcie; -struct imx6_pcie_drvdata { - enum imx6_pcie_variants variant; +struct imx_pcie_drvdata { + enum imx_pcie_variants variant; enum dw_pcie_device_mode mode; u32 flags; int dbi_length; @@ -98,17 +98,17 @@ struct imx6_pcie_drvdata { const u32 clks_cnt; const u32 ltssm_off; const u32 ltssm_mask; - const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; - const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; + const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; + const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; const struct pci_epc_features *epc_features; - int (*init_phy)(struct imx6_pcie *pcie); + int (*init_phy)(struct imx_pcie *pcie); }; -struct imx6_pcie { +struct imx_pcie { struct dw_pcie *pci; struct gpio_desc *reset_gpiod; bool link_is_up; - struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS]; + struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS]; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; @@ -129,7 +129,7 @@ struct imx6_pcie { /* power domain for pcie phy */ struct device *pd_pcie_phy; struct phy *phy; - const struct imx6_pcie_drvdata *drvdata; + const struct imx_pcie_drvdata *drvdata; }; /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -184,28 +184,28 @@ struct imx6_pcie { #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) -static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) +static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie) { - WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && - imx6_pcie->drvdata->variant != IMX8MQ_EP && - imx6_pcie->drvdata->variant != IMX8MM && - imx6_pcie->drvdata->variant != IMX8MM_EP && - imx6_pcie->drvdata->variant != IMX8MP && - imx6_pcie->drvdata->variant != IMX8MP_EP); - return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; + WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && + imx_pcie->drvdata->variant != IMX8MQ_EP && + imx_pcie->drvdata->variant != IMX8MM && + imx_pcie->drvdata->variant != IMX8MM_EP && + imx_pcie->drvdata->variant != IMX8MP && + imx_pcie->drvdata->variant != IMX8MP_EP); + return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } -static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0, IMX95_PCIE_PHY_CR_PARA_SEL, IMX95_PCIE_PHY_CR_PARA_SEL); - regmap_update_bits(imx6_pcie->iomuxc_gpr, + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL, IMX95_PCIE_REF_USE_PAD, 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0, IMX95_PCIE_REF_CLKEN, IMX95_PCIE_REF_CLKEN); @@ -213,9 +213,9 @@ static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) return 0; } -static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) +static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) { - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; unsigned int mask, val, mode, id; if (drvdata->mode == DW_PCIE_EP_TYPE) @@ -223,7 +223,7 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) else mode = PCI_EXP_TYPE_ROOT_PORT; - id = imx6_pcie->controller_id; + id = imx_pcie->controller_id; /* If mode_mask[id] is zero, means each controller have its individual gpr */ if (!drvdata->mode_mask[id]) @@ -232,12 +232,12 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) mask = drvdata->mode_mask[id]; val = mode << (ffs(mask) - 1); - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); } -static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) +static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, bool exp_val) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; bool val; u32 max_iterations = 10; u32 wait_counter = 0; @@ -256,9 +256,9 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) return -ETIMEDOUT; } -static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) +static int pcie_phy_wait_ack(struct imx_pcie *imx_pcie, int addr) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; u32 val; int ret; @@ -268,24 +268,24 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) val |= PCIE_PHY_CTRL_CAP_ADR; dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; val = PCIE_PHY_CTRL_DATA(addr); dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); - return pcie_phy_poll_ack(imx6_pcie, false); + return pcie_phy_poll_ack(imx_pcie, false); } /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ -static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) +static int pcie_phy_read(struct imx_pcie *imx_pcie, int addr, u16 *data) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; u32 phy_ctl; int ret; - ret = pcie_phy_wait_ack(imx6_pcie, addr); + ret = pcie_phy_wait_ack(imx_pcie, addr); if (ret) return ret; @@ -293,7 +293,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) phy_ctl = PCIE_PHY_CTRL_RD; dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; @@ -302,18 +302,18 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) /* deassert Read signal */ dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); - return pcie_phy_poll_ack(imx6_pcie, false); + return pcie_phy_poll_ack(imx_pcie, false); } -static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) +static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; u32 var; int ret; /* write addr */ /* cap addr */ - ret = pcie_phy_wait_ack(imx6_pcie, addr); + ret = pcie_phy_wait_ack(imx_pcie, addr); if (ret) return ret; @@ -324,7 +324,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) var |= PCIE_PHY_CTRL_CAP_DAT; dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; @@ -333,7 +333,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); /* wait for ack de-assertion */ - ret = pcie_phy_poll_ack(imx6_pcie, false); + ret = pcie_phy_poll_ack(imx_pcie, false); if (ret) return ret; @@ -342,7 +342,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); /* wait for ack */ - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; @@ -351,7 +351,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); /* wait for ack de-assertion */ - ret = pcie_phy_poll_ack(imx6_pcie, false); + ret = pcie_phy_poll_ack(imx_pcie, false); if (ret) return ret; @@ -360,74 +360,74 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) return 0; } -static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie) { /* TODO: Currently this code assumes external oscillator is being used */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, - imx6_pcie_grp_offset(imx6_pcie), + regmap_update_bits(imx_pcie->iomuxc_gpr, + imx_pcie_grp_offset(imx_pcie), IMX8MQ_GPR_PCIE_REF_USE_PAD, IMX8MQ_GPR_PCIE_REF_USE_PAD); /* * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is * supplied by 3.3V, the VREG_BYPASS should be cleared to zero. */ - if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000) - regmap_update_bits(imx6_pcie->iomuxc_gpr, - imx6_pcie_grp_offset(imx6_pcie), + if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000) + regmap_update_bits(imx_pcie->iomuxc_gpr, + imx_pcie_grp_offset(imx_pcie), IMX8MQ_GPR_PCIE_VREG_BYPASS, 0); return 0; } -static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); return 0; } -static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); /* configure constant input signal to the pcie ctrl and phy */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_LOS_LEVEL, 9 << 4); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN1, - imx6_pcie->tx_deemph_gen1 << 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_deemph_gen1 << 0); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, - imx6_pcie->tx_deemph_gen2_3p5db << 6); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_deemph_gen2_3p5db << 6); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, - imx6_pcie->tx_deemph_gen2_6db << 12); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_deemph_gen2_6db << 12); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_SWING_FULL, - imx6_pcie->tx_swing_full << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_swing_full << 18); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_SWING_LOW, - imx6_pcie->tx_swing_low << 25); + imx_pcie->tx_swing_low << 25); return 0; } -static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx6sx_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); - return imx6_pcie_init_phy(imx6_pcie); + return imx_pcie_init_phy(imx_pcie); } -static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) +static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie) { u32 val; - struct device *dev = imx6_pcie->pci->dev; + struct device *dev = imx_pcie->pci->dev; - if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, + if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr, IOMUXC_GPR22, val, val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, PHY_PLL_LOCK_WAIT_USLEEP_MAX, @@ -435,19 +435,19 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) dev_err(dev, "PCIe PLL lock timeout\n"); } -static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) +static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie) { unsigned long phy_rate = 0; int mult, div; u16 val; int i; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) return 0; - for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) - if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0) - phy_rate = clk_get_rate(imx6_pcie->clks[i].clk); + for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++) + if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0) + phy_rate = clk_get_rate(imx_pcie->clks[i].clk); switch (phy_rate) { case 125000000: @@ -465,46 +465,46 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) div = 1; break; default: - dev_err(imx6_pcie->pci->dev, + dev_err(imx_pcie->pci->dev, "Unsupported PHY reference clock rate %lu\n", phy_rate); return -EINVAL; } - pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); + pcie_phy_read(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << PCIE_PHY_MPLL_MULTIPLIER_SHIFT); val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; - pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); + pcie_phy_write(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); - pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); + pcie_phy_read(imx_pcie, PCIE_PHY_ATEOVRD, &val); val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; val |= PCIE_PHY_ATEOVRD_EN; - pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); + pcie_phy_write(imx_pcie, PCIE_PHY_ATEOVRD, val); return 0; } -static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) +static void imx_pcie_reset_phy(struct imx_pcie *imx_pcie) { u16 tmp; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) return; - pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); + pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp); tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); - pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); + pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp); usleep_range(2000, 3000); - pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); + pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp); tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); - pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); + pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp); } #ifdef CONFIG_ARM @@ -543,22 +543,22 @@ static int imx6q_pcie_abort_handler(unsigned long addr, } #endif -static int imx6_pcie_attach_pd(struct device *dev) +static int imx_pcie_attach_pd(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); struct device_link *link; /* Do nothing when in a single power domain */ if (dev->pm_domain) return 0; - imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); - if (IS_ERR(imx6_pcie->pd_pcie)) - return PTR_ERR(imx6_pcie->pd_pcie); + imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); + if (IS_ERR(imx_pcie->pd_pcie)) + return PTR_ERR(imx_pcie->pd_pcie); /* Do nothing when power domain missing */ - if (!imx6_pcie->pd_pcie) + if (!imx_pcie->pd_pcie) return 0; - link = device_link_add(dev, imx6_pcie->pd_pcie, + link = device_link_add(dev, imx_pcie->pd_pcie, DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); @@ -567,11 +567,11 @@ static int imx6_pcie_attach_pd(struct device *dev) return -EINVAL; } - imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); - if (IS_ERR(imx6_pcie->pd_pcie_phy)) - return PTR_ERR(imx6_pcie->pd_pcie_phy); + imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); + if (IS_ERR(imx_pcie->pd_pcie_phy)) + return PTR_ERR(imx_pcie->pd_pcie_phy); - link = device_link_add(dev, imx6_pcie->pd_pcie_phy, + link = device_link_add(dev, imx_pcie->pd_pcie_phy, DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); @@ -583,20 +583,20 @@ static int imx6_pcie_attach_pd(struct device *dev) return 0; } -static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) +static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) { unsigned int offset; int ret = 0; - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); break; case IMX6QP: case IMX6Q: /* power up core phy and enable ref clock */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); /* * the async reset input need ref clock to sync internally, @@ -605,7 +605,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) * add one ~10us delay here. */ usleep_range(10, 100); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); break; case IMX7D: @@ -618,15 +618,15 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) case IMX8MQ_EP: case IMX8MP: case IMX8MP_EP: - offset = imx6_pcie_grp_offset(imx6_pcie); + offset = imx_pcie_grp_offset(imx_pcie); /* * Set the over ride low and enabled * make sure that REF_CLK is turned on. */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); break; @@ -635,19 +635,19 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) return ret; } -static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) +static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) { - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6QP: case IMX6Q: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); break; case IMX7D: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); break; @@ -656,17 +656,17 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) } } -static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) +static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct device *dev = pci->dev; int ret; - ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); if (ret) return ret; - ret = imx6_pcie_enable_ref_clk(imx6_pcie); + ret = imx_pcie_enable_ref_clk(imx_pcie); if (ret) { dev_err(dev, "unable to enable pcie ref clock\n"); goto err_ref_clk; @@ -677,41 +677,41 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) return 0; err_ref_clk: - clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); return ret; } -static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) +static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) { - imx6_pcie_disable_ref_clk(imx6_pcie); - clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + imx_pcie_disable_ref_clk(imx_pcie); + clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } -static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) +static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) { - reset_control_assert(imx6_pcie->pciephy_reset); - reset_control_assert(imx6_pcie->apps_reset); + reset_control_assert(imx_pcie->pciephy_reset); + reset_control_assert(imx_pcie->apps_reset); - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, IMX6SX_GPR12_PCIE_TEST_POWERDOWN); /* Force PCIe PHY reset */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, IMX6SX_GPR5_PCIE_BTNRST_RESET); break; case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, IMX6Q_GPR1_PCIE_SW_RST); break; case IMX6Q: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; default: @@ -719,45 +719,45 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) } /* Some boards don't have PCIe reset GPIO. */ - gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 1); + gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1); } -static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) +static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct device *dev = pci->dev; - reset_control_deassert(imx6_pcie->pciephy_reset); + reset_control_deassert(imx_pcie->pciephy_reset); - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX7D: /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle * Corrector" and other mysterious undocumented things. */ - if (likely(imx6_pcie->phy_base)) { + if (likely(imx_pcie->phy_base)) { /* De-assert DCC_FB_EN */ writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); + imx_pcie->phy_base + PCIE_PHY_CMN_REG4); /* Assert RX_EQS and RX_EQS_SEL */ writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); + imx_pcie->phy_base + PCIE_PHY_CMN_REG24); /* Assert ATT_MODE */ writel(PCIE_PHY_CMN_REG26_ATT_MODE, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); + imx_pcie->phy_base + PCIE_PHY_CMN_REG26); } else { dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); } - imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); break; case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); break; case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, 0); usleep_range(200, 500); @@ -767,9 +767,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) } /* Some boards don't have PCIe reset GPIO. */ - if (imx6_pcie->reset_gpiod) { + if (imx_pcie->reset_gpiod) { msleep(100); - gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 0); + gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0); /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ msleep(100); } @@ -777,9 +777,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) return 0; } -static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) +static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct device *dev = pci->dev; u32 tmp; unsigned int retries; @@ -796,33 +796,33 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) return -ETIMEDOUT; } -static void imx6_pcie_ltssm_enable(struct device *dev) +static void imx_pcie_ltssm_enable(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; if (drvdata->ltssm_mask) - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, drvdata->ltssm_mask); - reset_control_deassert(imx6_pcie->apps_reset); + reset_control_deassert(imx_pcie->apps_reset); } -static void imx6_pcie_ltssm_disable(struct device *dev) +static void imx_pcie_ltssm_disable(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; if (drvdata->ltssm_mask) - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, 0); - reset_control_assert(imx6_pcie->apps_reset); + reset_control_assert(imx_pcie->apps_reset); } -static int imx6_pcie_start_link(struct dw_pcie *pci) +static int imx_pcie_start_link(struct dw_pcie *pci) { - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); struct device *dev = pci->dev; u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 tmp; @@ -841,7 +841,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dw_pcie_dbi_ro_wr_dis(pci); /* Start LTSSM. */ - imx6_pcie_ltssm_enable(dev); + imx_pcie_ltssm_enable(dev); ret = dw_pcie_wait_for_link(pci); if (ret) @@ -864,8 +864,8 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); dw_pcie_dbi_ro_wr_dis(pci); - if (imx6_pcie->drvdata->flags & - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { + if (imx_pcie->drvdata->flags & + IMX_PCIE_FLAG_IMX_SPEED_CHANGE) { /* * On i.MX7, DIRECT_SPEED_CHANGE behaves differently * from i.MX6 family when no link speed transition @@ -875,7 +875,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) * failure. */ - ret = imx6_pcie_wait_for_speed_change(imx6_pcie); + ret = imx_pcie_wait_for_speed_change(imx_pcie); if (ret) { dev_err(dev, "Failed to bring link up!\n"); goto err_reset_phy; @@ -890,37 +890,37 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dev_info(dev, "Link: Only Gen1 is enabled\n"); } - imx6_pcie->link_is_up = true; + imx_pcie->link_is_up = true; tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); return 0; err_reset_phy: - imx6_pcie->link_is_up = false; + imx_pcie->link_is_up = false; dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); - imx6_pcie_reset_phy(imx6_pcie); + imx_pcie_reset_phy(imx_pcie); return 0; } -static void imx6_pcie_stop_link(struct dw_pcie *pci) +static void imx_pcie_stop_link(struct dw_pcie *pci) { struct device *dev = pci->dev; /* Turn off PCIe LTSSM */ - imx6_pcie_ltssm_disable(dev); + imx_pcie_ltssm_disable(dev); } -static int imx6_pcie_host_init(struct dw_pcie_rp *pp) +static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct device *dev = pci->dev; - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); int ret; - if (imx6_pcie->vpcie) { - ret = regulator_enable(imx6_pcie->vpcie); + if (imx_pcie->vpcie) { + ret = regulator_enable(imx_pcie->vpcie); if (ret) { dev_err(dev, "failed to enable vpcie regulator: %d\n", ret); @@ -928,84 +928,84 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp) } } - imx6_pcie_assert_core_reset(imx6_pcie); + imx_pcie_assert_core_reset(imx_pcie); - if (imx6_pcie->drvdata->init_phy) - imx6_pcie->drvdata->init_phy(imx6_pcie); + if (imx_pcie->drvdata->init_phy) + imx_pcie->drvdata->init_phy(imx_pcie); - imx6_pcie_configure_type(imx6_pcie); + imx_pcie_configure_type(imx_pcie); - ret = imx6_pcie_clk_enable(imx6_pcie); + ret = imx_pcie_clk_enable(imx_pcie); if (ret) { dev_err(dev, "unable to enable pcie clocks: %d\n", ret); goto err_reg_disable; } - if (imx6_pcie->phy) { - ret = phy_init(imx6_pcie->phy); + if (imx_pcie->phy) { + ret = phy_init(imx_pcie->phy); if (ret) { dev_err(dev, "pcie PHY power up failed\n"); goto err_clk_disable; } } - if (imx6_pcie->phy) { - ret = phy_power_on(imx6_pcie->phy); + if (imx_pcie->phy) { + ret = phy_power_on(imx_pcie->phy); if (ret) { dev_err(dev, "waiting for PHY ready timeout!\n"); goto err_phy_exit; } } - ret = imx6_pcie_deassert_core_reset(imx6_pcie); + ret = imx_pcie_deassert_core_reset(imx_pcie); if (ret < 0) { dev_err(dev, "pcie deassert core reset failed: %d\n", ret); goto err_phy_off; } - imx6_setup_phy_mpll(imx6_pcie); + imx_setup_phy_mpll(imx_pcie); return 0; err_phy_off: - phy_power_off(imx6_pcie->phy); + phy_power_off(imx_pcie->phy); err_phy_exit: - phy_exit(imx6_pcie->phy); + phy_exit(imx_pcie->phy); err_clk_disable: - imx6_pcie_clk_disable(imx6_pcie); + imx_pcie_clk_disable(imx_pcie); err_reg_disable: - if (imx6_pcie->vpcie) - regulator_disable(imx6_pcie->vpcie); + if (imx_pcie->vpcie) + regulator_disable(imx_pcie->vpcie); return ret; } -static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) +static void imx_pcie_host_exit(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); - if (imx6_pcie->phy) { - if (phy_power_off(imx6_pcie->phy)) + if (imx_pcie->phy) { + if (phy_power_off(imx_pcie->phy)) dev_err(pci->dev, "unable to power off PHY\n"); - phy_exit(imx6_pcie->phy); + phy_exit(imx_pcie->phy); } - imx6_pcie_clk_disable(imx6_pcie); + imx_pcie_clk_disable(imx_pcie); - if (imx6_pcie->vpcie) - regulator_disable(imx6_pcie->vpcie); + if (imx_pcie->vpcie) + regulator_disable(imx_pcie->vpcie); } -static const struct dw_pcie_host_ops imx6_pcie_host_ops = { - .init = imx6_pcie_host_init, - .deinit = imx6_pcie_host_exit, +static const struct dw_pcie_host_ops imx_pcie_host_ops = { + .init = imx_pcie_host_init, + .deinit = imx_pcie_host_exit, }; static const struct dw_pcie_ops dw_pcie_ops = { - .start_link = imx6_pcie_start_link, - .stop_link = imx6_pcie_stop_link, + .start_link = imx_pcie_start_link, + .stop_link = imx_pcie_stop_link, }; -static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) +static void imx_pcie_ep_init(struct dw_pcie_ep *ep) { enum pci_barno bar; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -1014,7 +1014,7 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) dw_pcie_ep_reset_bar(pci, bar); } -static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, +static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, unsigned int type, u16 interrupt_num) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -1061,35 +1061,35 @@ static const struct pci_epc_features imx95_pcie_epc_features = { }; static const struct pci_epc_features* -imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) +imx_pcie_ep_get_features(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); - return imx6_pcie->drvdata->epc_features; + return imx_pcie->drvdata->epc_features; } static const struct dw_pcie_ep_ops pcie_ep_ops = { - .init = imx6_pcie_ep_init, - .raise_irq = imx6_pcie_ep_raise_irq, - .get_features = imx6_pcie_ep_get_features, + .init = imx_pcie_ep_init, + .raise_irq = imx_pcie_ep_raise_irq, + .get_features = imx_pcie_ep_get_features, }; -static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, +static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, struct platform_device *pdev) { int ret; unsigned int pcie_dbi2_offset; struct dw_pcie_ep *ep; - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct dw_pcie_rp *pp = &pci->pp; struct device *dev = pci->dev; - imx6_pcie_host_init(pp); + imx_pcie_host_init(pp); ep = &pci->ep; ep->ops = &pcie_ep_ops; - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX8MQ_EP: case IMX8MM_EP: case IMX8MP_EP: @@ -1111,10 +1111,10 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, if (device_property_match_string(dev, "reg-names", "dbi2") >= 0) pci->dbi_base2 = NULL; - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_SUPPORT_64BIT)) dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); - ep->page_size = imx6_pcie->drvdata->epc_features->align; + ep->page_size = imx_pcie->drvdata->epc_features->align; ret = dw_pcie_ep_init(ep); if (ret) { @@ -1132,30 +1132,30 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, pci_epc_init_notify(ep->epc); /* Start LTSSM. */ - imx6_pcie_ltssm_enable(dev); + imx_pcie_ltssm_enable(dev); return 0; } -static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) +static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie) { - struct device *dev = imx6_pcie->pci->dev; + struct device *dev = imx_pcie->pci->dev; /* Some variants have a turnoff reset in DT */ - if (imx6_pcie->turnoff_reset) { - reset_control_assert(imx6_pcie->turnoff_reset); - reset_control_deassert(imx6_pcie->turnoff_reset); + if (imx_pcie->turnoff_reset) { + reset_control_assert(imx_pcie->turnoff_reset); + reset_control_deassert(imx_pcie->turnoff_reset); goto pm_turnoff_sleep; } /* Others poke directly at IOMUXC registers */ - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6SX: case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF, IMX6SX_GPR12_PCIE_PM_TURN_OFF); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); break; default: @@ -1174,73 +1174,73 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) usleep_range(1000, 10000); } -static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save) +static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save) { u8 offset; u16 val; - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; if (pci_msi_enabled()) { offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); if (save) { val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); - imx6_pcie->msi_ctrl = val; + imx_pcie->msi_ctrl = val; } else { dw_pcie_dbi_ro_wr_en(pci); - val = imx6_pcie->msi_ctrl; + val = imx_pcie->msi_ctrl; dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); dw_pcie_dbi_ro_wr_dis(pci); } } } -static int imx6_pcie_suspend_noirq(struct device *dev) +static int imx_pcie_suspend_noirq(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + struct dw_pcie_rp *pp = &imx_pcie->pci->pp; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; - imx6_pcie_msi_save_restore(imx6_pcie, true); - imx6_pcie_pm_turnoff(imx6_pcie); - imx6_pcie_stop_link(imx6_pcie->pci); - imx6_pcie_host_exit(pp); + imx_pcie_msi_save_restore(imx_pcie, true); + imx_pcie_pm_turnoff(imx_pcie); + imx_pcie_stop_link(imx_pcie->pci); + imx_pcie_host_exit(pp); return 0; } -static int imx6_pcie_resume_noirq(struct device *dev) +static int imx_pcie_resume_noirq(struct device *dev) { int ret; - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + struct dw_pcie_rp *pp = &imx_pcie->pci->pp; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; - ret = imx6_pcie_host_init(pp); + ret = imx_pcie_host_init(pp); if (ret) return ret; - imx6_pcie_msi_save_restore(imx6_pcie, false); + imx_pcie_msi_save_restore(imx_pcie, false); dw_pcie_setup_rc(pp); - if (imx6_pcie->link_is_up) - imx6_pcie_start_link(imx6_pcie->pci); + if (imx_pcie->link_is_up) + imx_pcie_start_link(imx_pcie->pci); return 0; } -static const struct dev_pm_ops imx6_pcie_pm_ops = { - NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, - imx6_pcie_resume_noirq) +static const struct dev_pm_ops imx_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_pcie_suspend_noirq, + imx_pcie_resume_noirq) }; -static int imx6_pcie_probe(struct platform_device *pdev) +static int imx_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct dw_pcie *pci; - struct imx6_pcie *imx6_pcie; + struct imx_pcie *imx_pcie; struct device_node *np; struct resource *dbi_base; struct device_node *node = dev->of_node; @@ -1248,8 +1248,8 @@ static int imx6_pcie_probe(struct platform_device *pdev) u16 val; int i; - imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); - if (!imx6_pcie) + imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL); + if (!imx_pcie) return -ENOMEM; pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); @@ -1258,10 +1258,10 @@ static int imx6_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &dw_pcie_ops; - pci->pp.ops = &imx6_pcie_host_ops; + pci->pp.ops = &imx_pcie_host_ops; - imx6_pcie->pci = pci; - imx6_pcie->drvdata = of_device_get_match_data(dev); + imx_pcie->pci = pci; + imx_pcie->drvdata = of_device_get_match_data(dev); /* Find the PHY if one is defined, only imx7d uses it */ np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); @@ -1273,9 +1273,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) dev_err(dev, "Unable to map PCIe PHY\n"); return ret; } - imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); - if (IS_ERR(imx6_pcie->phy_base)) - return PTR_ERR(imx6_pcie->phy_base); + imx_pcie->phy_base = devm_ioremap_resource(dev, &res); + if (IS_ERR(imx_pcie->phy_base)) + return PTR_ERR(imx_pcie->phy_base); } pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); @@ -1283,72 +1283,72 @@ static int imx6_pcie_probe(struct platform_device *pdev) return PTR_ERR(pci->dbi_base); /* Fetch GPIOs */ - imx6_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); - if (IS_ERR(imx6_pcie->reset_gpiod)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod), + imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(imx_pcie->reset_gpiod)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod), "unable to get reset gpio\n"); - gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset"); + gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset"); - if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS) + if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS) return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n"); - for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) - imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i]; + for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++) + imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i]; /* Fetch clocks */ - ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks); if (ret) return ret; - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) { - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); - if (IS_ERR(imx6_pcie->phy)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) { + imx_pcie->phy = devm_phy_get(dev, "pcie-phy"); + if (IS_ERR(imx_pcie->phy)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->phy), "failed to get pcie phy\n"); } - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); - if (IS_ERR(imx6_pcie->apps_reset)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_APP_RESET)) { + imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); + if (IS_ERR(imx_pcie->apps_reset)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset), "failed to get pcie apps reset control\n"); } - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); - if (IS_ERR(imx6_pcie->pciephy_reset)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHY_RESET)) { + imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx_pcie->pciephy_reset)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset), "Failed to get PCIEPHY reset control\n"); } - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX8MQ: case IMX8MQ_EP: case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; + imx_pcie->controller_id = 1; break; default: break; } /* Grab turnoff reset */ - imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); - if (IS_ERR(imx6_pcie->turnoff_reset)) { + imx_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); + if (IS_ERR(imx_pcie->turnoff_reset)) { dev_err(dev, "Failed to get TURNOFF reset control\n"); - return PTR_ERR(imx6_pcie->turnoff_reset); + return PTR_ERR(imx_pcie->turnoff_reset); } - if (imx6_pcie->drvdata->gpr) { + if (imx_pcie->drvdata->gpr) { /* Grab GPR config register range */ - imx6_pcie->iomuxc_gpr = - syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); - if (IS_ERR(imx6_pcie->iomuxc_gpr)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + imx_pcie->iomuxc_gpr = + syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr); + if (IS_ERR(imx_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), "unable to find iomuxc registers\n"); } - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) { + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_SERDES)) { void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app"); if (IS_ERR(off)) @@ -1361,59 +1361,59 @@ static int imx6_pcie_probe(struct platform_device *pdev) .reg_stride = 4, }; - imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); - if (IS_ERR(imx6_pcie->iomuxc_gpr)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); + if (IS_ERR(imx_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), "unable to find iomuxc registers\n"); } /* Grab PCIe PHY Tx Settings */ if (of_property_read_u32(node, "fsl,tx-deemph-gen1", - &imx6_pcie->tx_deemph_gen1)) - imx6_pcie->tx_deemph_gen1 = 0; + &imx_pcie->tx_deemph_gen1)) + imx_pcie->tx_deemph_gen1 = 0; if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", - &imx6_pcie->tx_deemph_gen2_3p5db)) - imx6_pcie->tx_deemph_gen2_3p5db = 0; + &imx_pcie->tx_deemph_gen2_3p5db)) + imx_pcie->tx_deemph_gen2_3p5db = 0; if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", - &imx6_pcie->tx_deemph_gen2_6db)) - imx6_pcie->tx_deemph_gen2_6db = 20; + &imx_pcie->tx_deemph_gen2_6db)) + imx_pcie->tx_deemph_gen2_6db = 20; if (of_property_read_u32(node, "fsl,tx-swing-full", - &imx6_pcie->tx_swing_full)) - imx6_pcie->tx_swing_full = 127; + &imx_pcie->tx_swing_full)) + imx_pcie->tx_swing_full = 127; if (of_property_read_u32(node, "fsl,tx-swing-low", - &imx6_pcie->tx_swing_low)) - imx6_pcie->tx_swing_low = 127; + &imx_pcie->tx_swing_low)) + imx_pcie->tx_swing_low = 127; /* Limit link speed */ pci->link_gen = 1; of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); - imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); - if (IS_ERR(imx6_pcie->vpcie)) { - if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) - return PTR_ERR(imx6_pcie->vpcie); - imx6_pcie->vpcie = NULL; + imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); + if (IS_ERR(imx_pcie->vpcie)) { + if (PTR_ERR(imx_pcie->vpcie) != -ENODEV) + return PTR_ERR(imx_pcie->vpcie); + imx_pcie->vpcie = NULL; } - imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); - if (IS_ERR(imx6_pcie->vph)) { - if (PTR_ERR(imx6_pcie->vph) != -ENODEV) - return PTR_ERR(imx6_pcie->vph); - imx6_pcie->vph = NULL; + imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); + if (IS_ERR(imx_pcie->vph)) { + if (PTR_ERR(imx_pcie->vph) != -ENODEV) + return PTR_ERR(imx_pcie->vph); + imx_pcie->vph = NULL; } - platform_set_drvdata(pdev, imx6_pcie); + platform_set_drvdata(pdev, imx_pcie); - ret = imx6_pcie_attach_pd(dev); + ret = imx_pcie_attach_pd(dev); if (ret) return ret; - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { - ret = imx6_add_pcie_ep(imx6_pcie, pdev); + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { + ret = imx_add_pcie_ep(imx_pcie, pdev); if (ret < 0) return ret; } else { @@ -1433,12 +1433,12 @@ static int imx6_pcie_probe(struct platform_device *pdev) return 0; } -static void imx6_pcie_shutdown(struct platform_device *pdev) +static void imx_pcie_shutdown(struct platform_device *pdev) { - struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); + struct imx_pcie *imx_pcie = platform_get_drvdata(pdev); /* bring down link, so bootloader gets clean state in case of reboot */ - imx6_pcie_assert_core_reset(imx6_pcie); + imx_pcie_assert_core_reset(imx_pcie); } static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"}; @@ -1446,11 +1446,11 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; -static const struct imx6_pcie_drvdata drvdata[] = { +static const struct imx_pcie_drvdata drvdata[] = { [IMX6Q] = { .variant = IMX6Q, - .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, + .flags = IMX_PCIE_FLAG_IMX_PHY | + IMX_PCIE_FLAG_IMX_SPEED_CHANGE, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = imx6q_clks, @@ -1459,13 +1459,13 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, - .init_phy = imx6_pcie_init_phy, + .init_phy = imx_pcie_init_phy, }, [IMX6SX] = { .variant = IMX6SX, - .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX_PCIE_FLAG_IMX_PHY | + IMX_PCIE_FLAG_IMX_SPEED_CHANGE | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = imx6sx_clks, .clks_cnt = ARRAY_SIZE(imx6sx_clks), @@ -1477,9 +1477,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX6QP] = { .variant = IMX6QP, - .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX_PCIE_FLAG_IMX_PHY | + IMX_PCIE_FLAG_IMX_SPEED_CHANGE | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = imx6q_clks, @@ -1488,13 +1488,13 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, - .init_phy = imx6_pcie_init_phy, + .init_phy = imx_pcie_init_phy, }, [IMX7D] = { .variant = IMX7D, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHY_RESET, + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = imx6q_clks, .clks_cnt = ARRAY_SIZE(imx6q_clks), @@ -1504,8 +1504,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MQ] = { .variant = IMX8MQ, - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHY_RESET, + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), @@ -1517,9 +1517,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM] = { .variant = IMX8MM, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHYDRV | - IMX6_PCIE_FLAG_HAS_APP_RESET, + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), @@ -1528,9 +1528,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MP] = { .variant = IMX8MP, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHYDRV | - IMX6_PCIE_FLAG_HAS_APP_RESET, + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), @@ -1539,7 +1539,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX95] = { .variant = IMX95, - .flags = IMX6_PCIE_FLAG_HAS_SERDES, + .flags = IMX_PCIE_FLAG_HAS_SERDES, .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3, @@ -1550,8 +1550,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHY_RESET, + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks, @@ -1565,8 +1565,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM_EP] = { .variant = IMX8MM_EP, - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHYDRV, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = imx8mm_clks, @@ -1577,8 +1577,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MP_EP] = { .variant = IMX8MP_EP, - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHYDRV, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, @@ -1589,8 +1589,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX95_EP] = { .variant = IMX95_EP, - .flags = IMX6_PCIE_FLAG_HAS_SERDES | - IMX6_PCIE_FLAG_SUPPORT_64BIT, + .flags = IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_SUPPORT_64BIT, .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3, @@ -1603,7 +1603,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, }; -static const struct of_device_id imx6_pcie_of_match[] = { +static const struct of_device_id imx_pcie_of_match[] = { { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, @@ -1619,19 +1619,19 @@ static const struct of_device_id imx6_pcie_of_match[] = { {}, }; -static struct platform_driver imx6_pcie_driver = { +static struct platform_driver imx_pcie_driver = { .driver = { .name = "imx6q-pcie", - .of_match_table = imx6_pcie_of_match, + .of_match_table = imx_pcie_of_match, .suppress_bind_attrs = true, - .pm = &imx6_pcie_pm_ops, + .pm = &imx_pcie_pm_ops, .probe_type = PROBE_PREFER_ASYNCHRONOUS, }, - .probe = imx6_pcie_probe, - .shutdown = imx6_pcie_shutdown, + .probe = imx_pcie_probe, + .shutdown = imx_pcie_shutdown, }; -static void imx6_pcie_quirk(struct pci_dev *dev) +static void imx_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; struct dw_pcie_rp *pp = bus->sysdata; @@ -1641,33 +1641,33 @@ static void imx6_pcie_quirk(struct pci_dev *dev) return; /* Make sure we only quirk devices associated with this driver */ - if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) + if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver) return; if (pci_is_root_bus(bus)) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); /* * Limit config length to avoid the kernel reading beyond * the register set and causing an abort on i.MX 6Quad */ - if (imx6_pcie->drvdata->dbi_length) { - dev->cfg_size = imx6_pcie->drvdata->dbi_length; + if (imx_pcie->drvdata->dbi_length) { + dev->cfg_size = imx_pcie->drvdata->dbi_length; dev_info(&dev->dev, "Limiting cfg_size to %d\n", dev->cfg_size); } } } DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, - PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); + PCI_CLASS_BRIDGE_PCI, 8, imx_pcie_quirk); -static int __init imx6_pcie_init(void) +static int __init imx_pcie_init(void) { #ifdef CONFIG_ARM struct device_node *np; - np = of_find_matching_node(NULL, imx6_pcie_of_match); + np = of_find_matching_node(NULL, imx_pcie_of_match); if (!np) return -ENODEV; of_node_put(np); @@ -1683,6 +1683,6 @@ static int __init imx6_pcie_init(void) "external abort on non-linefetch"); #endif - return platform_driver_register(&imx6_pcie_driver); + return platform_driver_register(&imx_pcie_driver); } -device_initcall(imx6_pcie_init); +device_initcall(imx_pcie_init); From patchwork Mon Jul 29 20:18:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745669 X-Patchwork-Delegate: kw@linux.com Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2082.outbound.protection.outlook.com [40.107.21.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70B5918D4D4; Mon, 29 Jul 2024 20:19:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.21.82 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284358; cv=fail; b=V3K5sy81BoTCZsp3cPUeeZUp7n+0UdXZrfWBPq8hq3EZawjf07DLyxnbdfpbroG/+ivPpg9iq+BivJQ2GuLsFAaz++3/mZbaeiu8aykBl4J+ErkDyPvzjXOHTPkA8Y/47Quxbp98NCeytvZCwrmNA3CN8EDb0ry29KtFWTK/CLQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284358; c=relaxed/simple; bh=5Evp9ziK4xKXtiMCIUDV8Eu+6RTJQAatje71eLFFOgM=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=p8l6VCrezzvZi4ZgVO6sMGSa8G+yUlQcMqNRAQR43Sfr0XArbozmBbb9dCF82sC2vKVmrkWLOdU7RoRS/OpKqqL/6KxRZJDmXRiV5OlDRO+C4YXrX+omW7kfMw28kaEmGxDqpNB304iFitipc3tM4oi+te5vMUWXNfgU7cyZP4Q= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=d3M+Silf; arc=fail smtp.client-ip=40.107.21.82 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="d3M+Silf" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=gU017VpOfcaIzgKfzUbHtNloKgimrFpeKPW1/GVhJTdXusOZ2pgy1YH4E5cM69ft4Pk/ur9xktRL2nWOLZe94qlN62dSA4BJ3xmhldKXcMiprdiE/f9ljPxV5tte9rXPjDqi/miRK8I4lqan0no9Gb4pHe/5YD/yWV+lsA9idllpSQPFmum8IJDUZb772z1e2V3P1PTVejJydspQFgZzx0F4p9ELMoFmRseaKNEg7MNUwkH+F9xG3sPXumSbz4tPKPgtjJLXYS/W3+8pvSL4jmqqnkeOMPmfhjagBMPBNth/4HSE4oVph5EryCQgrLuySoDLWCZUf2wHka/Hb3lEig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IsJJOmwynhIuDvRKjtQeHGM+tPXYlKvgSIKyn7vsea4=; b=wyDXPQVv/JLTSrYlc7r3ltDtFtEO8XYWXFCOqQgbFM+Lb4Rt5WcRdXe/Emil9s8RDPwbrNkZESJDcXOyUo46/v4HogQFOmRYRWxMuYNc5n/9zsNVuzyi0rnGDGJga6pVWvjWEXCzUv8Y48YRYtI8gaWecH5SYJxGDgdxJzoRDHG9ovBi0BD34Ddj1/m7hHU6ds0R6Ln56puDurh8s77mKZ07i6wE6E9Frq6e0/snpSx90YBuwR0sx2prCYEuQgm3+SNtLxWkEMYyOR8TYtTpTgczlkumXk808ZwiX7dmTkN6TnZFstLKXV26cQTw6MAFbJsKobzl7UBuiP1CDc3SYA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IsJJOmwynhIuDvRKjtQeHGM+tPXYlKvgSIKyn7vsea4=; b=d3M+SilfZunZYr+q/ak/IRy+Tq3LevbKm1VxYyu1onOIY7NbOlGoaayLS64ZT/kVL3f+wfF4R+1uNBii6c9Y1LDqKHKAwTZy+KQtXYexAJGNCLBDyUpF7DEl9G3XMLprP9angrr0f53ulv7BGxmjPOL41ymXx2cBSnMUMyDJ94AaB9G4wuaFfQVq0LkWNpZMFyomQuPoztluRZOe+DLU56ZIV/uzYhi9cZOEQCT27wdifu4C4WnYLolfC1ydzwOrkv6wVEyocY1ntO/N7ANDcf5zeAhSBru1WxjdD1iOD2hZdl5Q3Km1UGpybSPghYW0eIsng5PAUSzhBfjTgOMgtg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DBAPR04MB7382.eurprd04.prod.outlook.com (2603:10a6:10:1ab::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.27; Mon, 29 Jul 2024 20:19:12 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:19:12 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:12 -0400 Subject: [PATCH v8 05/11] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Message-Id: <20240729-pci2_upstream-v8-5-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=8140; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=5Evp9ziK4xKXtiMCIUDV8Eu+6RTJQAatje71eLFFOgM=; b=oMuCrSj1c6X64c6fycFt1hs9EWif3NHWbQGySfIbz8otS19MrLFWamFei1nWPmeHjz+0F/CMA D8kJTLl8n+FD3slBN6r+NR/jhs9yzhgWg+m3fYJDKcyjKIbaCVyYYhC X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DBAPR04MB7382:EE_ X-MS-Office365-Filtering-Correlation-Id: fa3f4afd-7fb4-4451-b7fc-08dcb00bb5d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|52116014|1800799024|38350700014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?q?vAeM/WWITL80QIs+7S+ogdUST+9ZrIq?= =?utf-8?q?ySk6dC+WClSyj/JMqOSr7Sxt8WfYfHHMkdow1JBEY3L9jA1InMieQyeswrWS17xY4?= =?utf-8?q?Li3J5o5daSSHEE7nRyzESeLm+lrGh60RxMTRqll91LD+uvdAhDshGH2uAZLgXJ7z4?= =?utf-8?q?y4UaCkgInBcblvnWwLYmWbZQkopBF2pENRsM74YTHSdwctc/DG3g0QljQ41o3y07d?= =?utf-8?q?frXibUZtWYEGkL/lRpXBFhwQSzLzW58XGij+XfM8vU7LezM2aZ+Ofz2ZhFmY4LZ3t?= =?utf-8?q?QiK7QErf2d6cGyYRRUo8QcuqkRCeCiUtlSlMhC5pldW2EajHNUUFzQIZqH7iPUy9v?= =?utf-8?q?TMPX6Oa/WpziAl38kzMNJErUZj1HrGi0nbgKwrZy5raa+dULCIXux4RajiVBFuaBX?= =?utf-8?q?gxZ4NSMkMWXxoy2KPa9MwHryYyULxRcZCV6dgPI9urubGvzRbJO6GKMIx/Hbw1HRo?= =?utf-8?q?sHDiJSkQvsLkY+y2VuzAki63/1wMp3ZGbIBY4rASad9kfmI6uxpsCKy3knIm+B3j3?= =?utf-8?q?ucPqEs+nFrNgDUQja1lmkvzAssF5GQggPX6idxRFlMM1WsWGpY1uM56i0R1JhqU3W?= =?utf-8?q?THzDxC/cGqueb3t209zvmkBUizFWmCh4HAx3v4SnPdO2MIgnObpe38p9i6/NpyX/z?= =?utf-8?q?PAaQ5OtPMwR6zfDdBRu8S8KLlSzV/d+KYjqEwFdoellya+L/hRfDyu7xpeDMbDCze?= =?utf-8?q?1QVjA34Fa59VnYwdPCucXruENRN6311HRktqF32r6tCGXuJV/2ISOqp1rJMZaOltb?= =?utf-8?q?4ntytcaqrJwriIA9UXzRPVDl0TmiXIigFZT2/AoanhtEYQ9fx3wzXSP1ErwzfKspk?= =?utf-8?q?0/2/fJ+xclFBgpq3MK4/h0aN8hbBv1ndVf5+bejjRIwJAwp7H2XFAOeKs6ve+Ed+m?= =?utf-8?q?bFMLaK95sXebx48PQny/vzFXpYm97teDbDlAx+NeDQqZH73kynhTO2fmDYWQIHJ6b?= =?utf-8?q?QmpMStMPZkNqNQLUal2F3bW9SrJzZVKNwp3HsgEhC2ZccGpNrV/2zepFdGfcMzeuw?= =?utf-8?q?ohO2TJBMPTu/VxKyRVfmdhMUnnq3rv1TKxEucLUXK/snp4LqZ4wdJQ3rS9rSVaJMN?= =?utf-8?q?HGS/uvb6KuzWV3zlMS90Ly51I4rz5KCG60X2eGrO0HdEfLfohH9Ic94eVH1qZtv+u?= =?utf-8?q?qhb/5mDY9BQwI4JALPr8JRSJpQF4DDRF1yjkXM89HuEII8Ujug/IQS/5TE0OYquHS?= =?utf-8?q?aYKuIBox0fYrci9I6qm3ICnpKAxDRRrY4pEgbCFTDoZykPCwig43KYRpnCHGxXwJD?= =?utf-8?q?CHoVMtRIVaWtANn9tRL9a17R7Trj8LWxkdXV24K2hLgZFHACLsnB2AYM9VTDRrknw?= =?utf-8?q?M4EbN1OecJ7GyXHhEgsYF+RA/oLvB9H85PSxtlgMGwqVZPADXwaJKxk=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(52116014)(1800799024)(38350700014)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?fT4z5UjHLt63ZQiZTPcw36GzFdLe?= =?utf-8?q?P3hQenbh2gf0jwKtmh3Rpshzvcgf/rjsQh3L0lKnBarIJkbzf0CPgqOVGlfW+Yv55?= =?utf-8?q?+EIcksSAEkthMx7l7Z9dmy9UJZZWxAOVnMBpTy2lHGjOroGBeYTvMqk9tzM9X+atT?= =?utf-8?q?4xX7MBUhMHI2U6IMy1MFHzKChGGLJAKUuJ5sIxyECbs5iRe3fWc/7RC8M+BUViIPr?= =?utf-8?q?0Jl8TL5sIlH/x4LqQklUSPmEA4Jv28XNbIcvNFr0DPLv0Vapxi0vzgOfgB1icWp9X?= =?utf-8?q?Lp+gh5R7Wai+4dWG8s4Hf1eVuAUEDn3ntX4YHfCToxlezCEAhNUKV3cQdls9+ySyD?= =?utf-8?q?MFbn55XbLCz2WMhK278iT6JGsOO1Wa/T31/xmdbD+kyT1PObweL51I+f1E4jrW9J3?= =?utf-8?q?/pzHs6OtFkV5HMLlywGNKLWeurDyCPiuS/VGWJFhRDnzj4fPgjOhuC944OVYD8Fmc?= =?utf-8?q?suI6u6axKDsHvSNcE1ZCqUYlbQ/PEzShWpwQRFcCEn7JeyIje4cYij2RK4mJQ3Zkm?= =?utf-8?q?oznqXAbohYnJjDRG+aM68/3touwcMlEtgmwS64yUtosw5+1YMgXJj2t0JpAORz9Rq?= =?utf-8?q?03YzNSWY3+9190ViEAtbG8oKHGPEXKaSXdcdQJt9NTn1Z0fEtSVb8QANsVzSU+9yg?= =?utf-8?q?JpxShAQ+FqFdU6KEK4oc9CmpNYY2BiZ/SkdyX45gEAU/taXtt9mGukQCdQMoJW/sA?= =?utf-8?q?7PVSET2SpKhfPggrIbs6wpNK82wK+OONTqq+SPtv+j08SCQ3AKwcUWLXOsKFKu2hV?= =?utf-8?q?VJU3l4o1TD/VwrRbTprpIuaSMR0BVIKksT4wTaR3YNx/RHr1bCbSK/or3L3bxi9KJ?= =?utf-8?q?y8MBwrtY3juik8Mxn59gGKogXlsTeRZRv52J78v0y3Zu72uSlRbly0REWSiSq3PiD?= =?utf-8?q?yMXGIqpNFrqGtQWm9muo4Qz98TnBD17mNBW9RZbwqkjuNmrTWc9nyAolRySAl3CC7?= =?utf-8?q?cFGD5qsluBnjNqWQNiNrvfbxlHwS92I6DTdypkU6lp6Np2v0pffF+5fhuCidlD1dh?= =?utf-8?q?8nBRZEDYdSX4JnZGxgZEF83/44RNrBUBGIBDYoeoAlOWaMUSLIbIrB9DK8lxzZyNB?= =?utf-8?q?HZnVrElarKzurGneN//330ax+QQrck4uijrXQQimDMAkaO5x1IBsXm+CnjPsv7hcF?= =?utf-8?q?szGa2CLW+6UCrMp7VTardIlENpb+JkYbvpCgDr1oq93UgFV0wjt5nfAho9ARh7Wpn?= =?utf-8?q?MB4j/fVDwifqtRMxirbxVKvcoONAiB5sDXsOdxGnH/Bdsv73nT11vTSKmBAOhJ4Gz?= =?utf-8?q?00a8253pRUQ0Ka1pkFu0WXMMODdpEXYErvZKdxXQumofGojjobX3oKUYdOM/ialGL?= =?utf-8?q?AD1YIhIXuwb+RAejdj9Sk35k/DOjBbNPPM0B1ucCxarZX2GuId2vRTi59b6ISuZCH?= =?utf-8?q?KkRK94ABVwlIA61s6XSaGOTUwBvFiZqfsgeqKs51lYYO8d/kzg2msNqM6fJe8fYww?= =?utf-8?q?jENZNo6ele5zqSHy/9SiP9nIQ+rmQlamrW6AiiXamPTIQpw8Yov/FawvUvXdRe1v2?= =?utf-8?q?13ZZbW3yLn2t?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: fa3f4afd-7fb4-4451-b7fc-08dcb00bb5d1 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:19:12.2021 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: heAMAOzR/MBjS08ZSPg6Q8QoUS1+HQoXFVwqqViTESu1DSf8SQr/lwAtbzHWLtcEz3W9ieo6kF7beoy247CN9Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7382 Instead of using the switch case statement to enable/disable the reference clock handled by this driver itself, let's introduce a new callback enable_ref_clk() and define it for platforms that require it. This simplifies the code. Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 111 ++++++++++++++++------------------ 1 file changed, 51 insertions(+), 60 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 443c7c75f2842..b68a817ccc86b 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -102,6 +102,7 @@ struct imx_pcie_drvdata { const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; const struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); + int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); }; struct imx_pcie { @@ -583,21 +584,20 @@ static int imx_pcie_attach_pd(struct device *dev) return 0; } -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) +static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) { - unsigned int offset; - int ret = 0; + if (enable) + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); - break; - case IMX6QP: - case IMX6Q: + return 0; +} + +static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) +{ + if (enable) { /* power up core phy and enable ref clock */ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); /* * the async reset input need ref clock to sync internally, * when the ref clock comes after reset, internal synced @@ -605,55 +605,33 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) * add one ~10us delay here. */ usleep_range(10, 100); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); - break; - case IMX7D: - case IMX95: - case IMX95_EP: - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MP: - case IMX8MP_EP: - offset = imx_pcie_grp_offset(imx_pcie); - /* - * Set the over ride low and enabled - * make sure that REF_CLK is turned on. - */ - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, - 0); - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); - break; + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); + } else { + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); } - return ret; + return 0; } -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) +static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) { - switch (imx_pcie->drvdata->variant) { - case IMX6QP: - case IMX6Q: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, - IMX6Q_GPR1_PCIE_TEST_PD); - break; - case IMX7D: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); - break; - default: - break; + int offset = imx_pcie_grp_offset(imx_pcie); + + if (enable) { + regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); + regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); } + + return 0; +} + +static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) +{ + if (!enable) + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); + return 0; } static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) @@ -666,10 +644,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) if (ret) return ret; - ret = imx_pcie_enable_ref_clk(imx_pcie); - if (ret) { - dev_err(dev, "unable to enable pcie ref clock\n"); - goto err_ref_clk; + if (imx_pcie->drvdata->enable_ref_clk) { + ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true); + if (ret) { + dev_err(dev, "Failed to enable PCIe REFCLK\n"); + goto err_ref_clk; + } } /* allow the clocks to stabilize */ @@ -684,7 +664,8 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) { - imx_pcie_disable_ref_clk(imx_pcie); + if (imx_pcie->drvdata->enable_ref_clk) + imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } @@ -1460,6 +1441,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, + .enable_ref_clk = imx6q_pcie_enable_ref_clk, }, [IMX6SX] = { .variant = IMX6SX, @@ -1474,6 +1456,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx6sx_pcie_init_phy, + .enable_ref_clk = imx6sx_pcie_enable_ref_clk, }, [IMX6QP] = { .variant = IMX6QP, @@ -1489,6 +1472,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, + .enable_ref_clk = imx6q_pcie_enable_ref_clk, }, [IMX7D] = { .variant = IMX7D, @@ -1501,6 +1485,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx7d_pcie_init_phy, + .enable_ref_clk = imx7d_pcie_enable_ref_clk, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1514,6 +1499,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, .init_phy = imx8mq_pcie_init_phy, + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, }, [IMX8MM] = { .variant = IMX8MM, @@ -1525,6 +1511,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx8mm_clks), .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, }, [IMX8MP] = { .variant = IMX8MP, @@ -1536,6 +1523,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx8mm_clks), .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, }, [IMX95] = { .variant = IMX95, @@ -1562,6 +1550,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, .init_phy = imx8mq_pcie_init_phy, + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, @@ -1574,6 +1563,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, @@ -1586,6 +1576,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, }, [IMX95_EP] = { .variant = IMX95_EP, From patchwork Mon Jul 29 20:18:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745670 X-Patchwork-Delegate: kw@linux.com Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2048.outbound.protection.outlook.com [40.107.104.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 686E318E75A; Mon, 29 Jul 2024 20:19:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.104.48 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284363; cv=fail; b=cx1WIaDgEs7ozPwwaqKgKvBEfswQ+4iLutr5XhSimj/xvB16ystale50aDZ1slRssPsog2r7ojmv39qiIsAcBxgPLjoPhVS8ntRk2qh4zr8XeeAkM+voaqiqdpA6mRC5M5IS6i0Kqfs9ALzJrq8eWR93+dW+w4XlyDQTk3CyQRA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284363; c=relaxed/simple; bh=l6u7V1/pCtBjFxMkz39fZGAw07dHKSYZdHO4bMuhkdo=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=BFpAyJrXJM5mRHHQUFQyiaqPCta158cj4a83qGbn/JOjmc9qB6BiA/JjQGnK04RBbxcQFyVVQHmISL2OPJ++UiEcfnSsih4vLGiEqXIaNQh7gxp+rfadnaxNHm47PoB8gm9iRc2/sa2/b/0xwZn0WL2rYoZDEBw23McQx7ysTow= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=ADpsCdEh; arc=fail smtp.client-ip=40.107.104.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="ADpsCdEh" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=cUoYVuMzLeUeS8/wTLpFIjTj1c8Jh0gmEpoK3YuRYUoUnHzPgxER26lBZt7drN+VZRCU69DZ7QYBohEZflTINbF8zyhLIA1iEPh1N3oSzVlvrkTZhSu7qJQXB0F4ugOBOAoyQ3yH8OonTy//KHc81Sp9fv36buTE9JT3uvw7TXWRxaznXQXGblPtGrd1ysgksKSkOA1u48oeIiehsAEdCj/BweO6C0N0BVjO+0RIKfn8t5FUHxKsz5XkNg5GHM/KtPhIuSHTXn8sW5L3GkcwkUh1hr7TTLIhLoloNxR5s4o7TmE56Osqd+ZnhHbcLmsSuqxlbuGKSjGNhiM6N4+pBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=N/QA2uinC+ZPsfCdu0G7gGvjslyL0frrBFiMN/7ouRQ=; b=jH7OLSRiWm7hdopfZzEbvnxFBU3AoT4hSXmf/PnyIirNhXjAjS7npvCU20dW5xQK4QYhykjRZwOSIDmR8yrAHIzZSZkHTYcdHNO+Bb6KbGLdAaHklJReGeAtnV5xteeNYPrAZTEtcO8TiEbl8LxKP9gLBDJoNgEukaeE2eUCLHWj/yO/o4blujrkLuLOfiQm0fWcTG9WneL9sQ2RMFIgX5yl9uOOwZfb/FRebkb4y/ddaF6NZ8vBKA4ua3y74qqOmdDkdxJMo0jPJDCo06HRxNsDSsnU5PXNpOMQnVd53O4w+NzOjY81dlKnVgNdgV6plLT7ORZMCther1G9uoACDg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=N/QA2uinC+ZPsfCdu0G7gGvjslyL0frrBFiMN/7ouRQ=; b=ADpsCdEhgeEgoK9xs6zg8CN3dafWFBc2Wx6WRWaJO8ftrugc4c0Sz0TsRZ0/73o+1eB3N7AEvk9ndfNeHDBHnJeK3NOTFlSE0hk7L4kiuc+aX9AxHb/OaDo9/i9y+dQ71Yi8Vutux2CSsd2M8cxtTP612Hb5x+eKFKV4SbfYQbp3dA1ePUfO93OQ2IU10N00bmDt9q8XRlpdp2tm2VWA3H6CA7xiyQZwPjZ+ckteEV/wDGbtNLLKdJb9PoGzF88rTp3UY8P/Qe5BzqMHjnhNhqoiUy+4BigrJMcuxgbeUU2YPd3ffiVIcTnTWp8dvDr0J1NR3ffGfOhZXHhW9lo3Jw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DBAPR04MB7382.eurprd04.prod.outlook.com (2603:10a6:10:1ab::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.27; Mon, 29 Jul 2024 20:19:17 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:19:17 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:13 -0400 Subject: [PATCH v8 06/11] PCI: imx6: Simplify switch-case logic by involve core_reset callback Message-Id: <20240729-pci2_upstream-v8-6-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=7122; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=l6u7V1/pCtBjFxMkz39fZGAw07dHKSYZdHO4bMuhkdo=; b=shKot/hisTnDMqzj/nvUxxC3nka7UotQLVSp9NCqGWdCD0iEENfuye2ecoH5KncI9ZHLCkcXp Ga72Mrepd+eDxdMWVnED9n845fcBwWNlzd1I7IiESWzWjM4sGU/CPZ1 X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DBAPR04MB7382:EE_ X-MS-Office365-Filtering-Correlation-Id: 02e66897-25c3-4081-e513-08dcb00bb91f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|52116014|1800799024|38350700014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?q?BbF5aMEINXga4Fsz2OMg8o/W8DIr/Ns?= =?utf-8?q?vuh/t1YI8mZQ0/fvg7vIgIx7Kp5i5zKH26iox60QxXMScUP8bOGI38k7O/g776Wao?= =?utf-8?q?fAMPS5mSfFRlTOpWSGMjWs9+iL45WlnAyHOv4NfBY0Yfq506ZucaFxrwd2PlIj+GC?= =?utf-8?q?THhp30l0AgRCkq6LXJddSQSXdymZY+smghIC6MsP5gd+U+tag6nxlrvj36AA1Kz6/?= =?utf-8?q?R1fJeG8O/t+kv12RKK9R4F4jfAXevC9scCjoNHQ1jgIjW7pkDd8InYCg/M+Aj880a?= =?utf-8?q?tvTkvNU/i1PxPgldox5wBRh8s0MBG2ogSjoomcRZndnz657/wXcuB9yVuR5s4Ji00?= =?utf-8?q?MERsJ6n3vHW+awAPoT2SR0fYe+WINx5TKEXUV3Yw3dDmIdftdhQZoTPPoZp8p2wFB?= =?utf-8?q?FwumIs6Etx7jY5QVGg66IN8WGJ3QMqkzY0ktpxM50x6dXR+woG8WeHT5GDcXtZ0Cu?= =?utf-8?q?saEV0+zrWyLKNJhtw7io3RRQ+2kVqUVhzNhFiK9MNUrXUMLKi1psrli1X8I3cO1nB?= =?utf-8?q?zTbAmqlZsqHsoKXnN5f8pYn5s/YnM2wGNHsSXCUEruC0oEl+T0EYLnzb6+s2GHHOX?= =?utf-8?q?igf+qda9uFt1lxbsykfUK2RYFguS8+D+XFiCHsB93VMdjWqmWY3ROvTsJHO+Q8Fl6?= =?utf-8?q?Js/ndoKaKFeN2Rro1WfcojOdODDLfaSkS1ajTX3x4we/8FUlDGoUVDCjitg2at/Ow?= =?utf-8?q?k6e3tmLHnGHKWlNY1KOg8YOs/htYC5IXcO/TLQMP7y6sqYonuWVHLF0SFiakA0lPa?= =?utf-8?q?4iD2ly/Z0UUgFfi5188VT0NONctjgh3AuatlI/GyFvrq/cqeLlrWkbk4RJ4CMMmFi?= =?utf-8?q?hMBGYIiqiGWxUpvUqsMbvHMja7p1rAOOXGAohAa5bwbvAhFgdVhMtEYqCao3VwJwb?= =?utf-8?q?WsjlVSIz5jAAS2GWMrZS5wyUTw/uq8twWr3Mz+1yuHQvabacL7JMq5szzVKP71qb2?= =?utf-8?q?YofGF2WFMLgPUaqyRpYYXSWkdXSDbIzsXP/NbkpSSwFJntQjZJFDFaShG8I5GwHsi?= =?utf-8?q?zHdOURldAApO/S85x8eB7I3EvINCrDiEGCDrp0L00tdTIb83QkEBaaPtKrc5m4Kc9?= =?utf-8?q?d9w6DZO2pydLdVVVguhrBsQA8uOP1YO9RIvvTj6hRDfud9Fl9lkxQ8tMAPfciwn5n?= =?utf-8?q?X2XoD7yNS4sxaijcvTtYTBhYFKSWG3IVgtBcAm+wYrM5wxNyFlAzB/6BjL9Rr9bKC?= =?utf-8?q?AWH8nfO2eD035d6xs3gQjr1eFsYG/7jwOIlaVrosVfIVkEePo+MY7doR4+SnK2nM0?= =?utf-8?q?8k2jmclDTAnJU8ODE/QwtKOe9jN7CYHGUycPnS5eLpWT+kt1k8Qf2Zi7X0iXusej4?= =?utf-8?q?PHfM/1TKDOJ8UsXWTVWPRXCnHD7Uh73mWCWDfQxt8k/VYfxJVGf1658=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(52116014)(1800799024)(38350700014)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?sxGhGkBIRmdPgepQbYpxlANtYz/v?= =?utf-8?q?Wc9kHTnsYY6Hzp1ZzuDSjEFS+JAFhsIOEf0mYTCD6PC9Zmfowrf3WLyjP3FN6KolJ?= =?utf-8?q?9lzh6U2ApstJYLMZRmFfyyZrJgZ3qSEOdBdBmhT9HJoTFmPTlLx7u/u/DWQto1rfu?= =?utf-8?q?HM/B5TZ615vZ+gW7pbcFfB2fINUc1vxrerTZ5FsrsbJ49TYNPG0iwM+YPtzELVmvS?= =?utf-8?q?VNtNgqgFbWI89lC8CQziqpaIPUWacURHwXXKxY7KgFV5ylwMf1RkfRt8qHQqA/NjK?= =?utf-8?q?XvA4m69UrpamTuTWlLTtrfOMs2Ix43+q4jcYeApDrAc74CH0KSzsg/LZqS7ahey34?= =?utf-8?q?c5YFXwUWKNnEImdnulIeQ+1VU9FxAR2HuuXsU1Dy8vXrgez19I682oWCAmQVGyizp?= =?utf-8?q?snarl6n/fERhuRH/GW0xlYBrNOgSxs7Um7s8PhHPnhlJIGXJ7ZVXiOkT4LfsxURIb?= =?utf-8?q?HwSx1eK9u2WOqpRpYFWLZtjN7nAOceIaT1DvxYUCjPHjbuMeM9BzSrWwSOo26/vxp?= =?utf-8?q?gXkhGZhO53e9802od6oPvZiPFhFLxmY0f1Po7yDI8jcq54htxWWXeNwFYDHYmUEPF?= =?utf-8?q?1C4fHwkg2fDofG3lHbsTu7EAtiIwl+RPaXYi1tdhr3wZsoCltB9CBKyHSgXwKpNtP?= =?utf-8?q?FcQkSpp7iW0owp+P4xcZ4iWT/Y86qlwvkuG40dYvGSuvLVOBQvMTgFu+wdeRH8FYU?= =?utf-8?q?gGorH7TZUCDgJ55SfZ2RUK7mbi4ydfPFdLmiPgJKUmcnvkmqlwWlwiy9vWqAKOK5a?= =?utf-8?q?ER5UHA6ebvduBijiQO7ejHHr52wFMzZdS7sbFRdPNEF2k5ywWx4EcW/xAk6rp8/a4?= =?utf-8?q?wSthT1W2QVp/3pFiLsqEU4qdyV4BqwzJapxrB6ppOJmYEg0ny9GaJJWJu60nmMt+m?= =?utf-8?q?fP58zH/ewIotbZshMS4GuIIo8vNdNhNBhdXZnsFAQPm2kT/8ugOfTnHU94jrsz7fZ?= =?utf-8?q?hmYJZYlfZS82fLARMKU2wpJdLglnIEvPddU8kPp/phYeGF6uP6qXwauHNuFZYbIGz?= =?utf-8?q?Hn42hnOPAqkahNnZy9pqXztlVi5AtLiXfwqBsB3dO0cCVZ3uW+rKKSPX9kRaeb/aU?= =?utf-8?q?BnJv6J3WCadGaP0Lp8o9geiRKYtVX5HuUSeYpIiy6KfCp3pySd9YRIRF44fx8GF/P?= =?utf-8?q?FNq9wYxWs2ykjr1cLS+Q8y90iAYZp+mGC8NG6OAUOv56kIfQvdOtQ6aNGxP0I+H+I?= =?utf-8?q?VxzL29eXjU/Iq8PZAJpxDW9xQBxBwJHH1geSnqzs2G0XOS7jO1bE4kOvRNtPw/HMt?= =?utf-8?q?Wp6yYqCcffd1Wkk3o+cbGHOHvNbzA5ijUCAsE7HcsAkKohB6eBMEfLjbADV1uOYjd?= =?utf-8?q?pJThkWja9jZf0Nmi7b81eiA+QeXYNgZes/YYbegaEuaYHQeIMUnQsB1qCC69EonGt?= =?utf-8?q?YHf9+sPhZsI5SDUlA+ek8Lt/H6ONqqA8iqQ7X1N+f6cWXuF67yEpt13GBa37vX0ve?= =?utf-8?q?y3eyd+noWz14bnklIAFBzpYkv54GV3qJf5dqgzZnOhekYV2kizFHvJYsGApqhI0dj?= =?utf-8?q?/m3V9m6l2S0/?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 02e66897-25c3-4081-e513-08dcb00bb91f X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:19:17.7571 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gWxpp4qvgSUqeio8xku9qDPoYWvIn0ylanWSLKy9/9uNmDtPQ9F+P1s3kWeUnsZd85c/fyMGV6sFu89jfdyPug== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7382 Instead of using the switch case statement to assert/dassert the core reset handled by this driver itself, let's introduce a new callback core_reset() and define it for platforms that require it. This simplifies the code. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 134 ++++++++++++++++++---------------- 1 file changed, 71 insertions(+), 63 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index b68a817ccc86b..e295c7bef732e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { const struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); + int (*core_reset)(struct imx_pcie *pcie, bool assert); }; struct imx_pcie { @@ -669,35 +670,75 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } +static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + if (assert) + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_TEST_POWERDOWN); + + /* Force PCIe PHY reset */ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, + assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0); + return 0; +} + +static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, + assert ? IMX6Q_GPR1_PCIE_SW_RST : 0); + if (!assert) + usleep_range(200, 500); + + return 0; +} + +static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + if (!assert) + return 0; + + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); + + return 0; +} + +static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + + if (assert) + return 0; + + /* + * Workaround for ERR010728, failure of PCI-e PLL VCO to + * oscillate, especially when cold. This turns off "Duty-cycle + * Corrector" and other mysterious undocumented things. + */ + + if (likely(imx_pcie->phy_base)) { + /* De-assert DCC_FB_EN */ + writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4); + /* Assert RX_EQS and RX_EQS_SEL */ + writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ, + imx_pcie->phy_base + PCIE_PHY_CMN_REG24); + /* Assert ATT_MODE */ + writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26); + } else { + dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); + } + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); + return 0; +} + static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) { reset_control_assert(imx_pcie->pciephy_reset); reset_control_assert(imx_pcie->apps_reset); - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - /* Force PCIe PHY reset */ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, - IMX6SX_GPR5_PCIE_BTNRST_RESET, - IMX6SX_GPR5_PCIE_BTNRST_RESET); - break; - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_SW_RST, - IMX6Q_GPR1_PCIE_SW_RST); - break; - case IMX6Q: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); - break; - default: - break; - } + if (imx_pcie->drvdata->core_reset) + imx_pcie->drvdata->core_reset(imx_pcie, true); /* Some boards don't have PCIe reset GPIO. */ gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1); @@ -705,47 +746,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx_pcie->pci; - struct device *dev = pci->dev; - reset_control_deassert(imx_pcie->pciephy_reset); - switch (imx_pcie->drvdata->variant) { - case IMX7D: - /* Workaround for ERR010728, failure of PCI-e PLL VCO to - * oscillate, especially when cold. This turns off "Duty-cycle - * Corrector" and other mysterious undocumented things. - */ - if (likely(imx_pcie->phy_base)) { - /* De-assert DCC_FB_EN */ - writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, - imx_pcie->phy_base + PCIE_PHY_CMN_REG4); - /* Assert RX_EQS and RX_EQS_SEL */ - writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL - | PCIE_PHY_CMN_REG24_RX_EQ, - imx_pcie->phy_base + PCIE_PHY_CMN_REG24); - /* Assert ATT_MODE */ - writel(PCIE_PHY_CMN_REG26_ATT_MODE, - imx_pcie->phy_base + PCIE_PHY_CMN_REG26); - } else { - dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); - } - - imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); - break; - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, - IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); - break; - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_SW_RST, 0); - - usleep_range(200, 500); - break; - default: - break; - } + if (imx_pcie->drvdata->core_reset) + imx_pcie->drvdata->core_reset(imx_pcie, false); /* Some boards don't have PCIe reset GPIO. */ if (imx_pcie->reset_gpiod) { @@ -1442,6 +1446,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, .enable_ref_clk = imx6q_pcie_enable_ref_clk, + .core_reset = imx6q_pcie_core_reset, }, [IMX6SX] = { .variant = IMX6SX, @@ -1457,6 +1462,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx6sx_pcie_init_phy, .enable_ref_clk = imx6sx_pcie_enable_ref_clk, + .core_reset = imx6sx_pcie_core_reset, }, [IMX6QP] = { .variant = IMX6QP, @@ -1473,6 +1479,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, .enable_ref_clk = imx6q_pcie_enable_ref_clk, + .core_reset = imx6qp_pcie_core_reset, }, [IMX7D] = { .variant = IMX7D, @@ -1486,6 +1493,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx7d_pcie_init_phy, .enable_ref_clk = imx7d_pcie_enable_ref_clk, + .core_reset = imx7d_pcie_core_reset, }, [IMX8MQ] = { .variant = IMX8MQ, From patchwork Mon Jul 29 20:18:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745671 X-Patchwork-Delegate: kw@linux.com Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2057.outbound.protection.outlook.com [40.107.21.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D30F18EFCF; Mon, 29 Jul 2024 20:19:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.21.57 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284369; cv=fail; b=q0G/HTzTX+cvS9NKZZLvvisxSCZ7mfRFK34qbYhR8OwedMYUxAZSk1lX5es4un7GfAPnefjbp0QIxQ00Cj+0MrH3f4rHhlDKrLOBi8p9wmRq3KgOc5TUhAh9kFJqQHK7VPehYfl0Dkh4qtZeydDcX3neVaRzFVafNPA06i+vl/I= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284369; c=relaxed/simple; bh=TNSd+b5y2IdUI30Q9idwzdMxK5IHuQjkFajPvbPUy8I=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=gNwEYFCcgzq+jRfO9WjmmEA22NcclTtuUSsss3dgrjZUB1RDVRXZKCD9VqCTNYDSdO8BB420xFxsxqXjPtC6gx1XNV5iwR9wTKrK7H77ehRQ84TaLh+gxEO+pLiTx+wtMaId8CDFnNdtZVKSEOanMaP3Ph3RU7gxSPngJEhuwYk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=GoOyB+GZ; arc=fail smtp.client-ip=40.107.21.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="GoOyB+GZ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Btr5xMXflJ2MxvcJzeLsNR96hHd90NQceLYel/LqyMm/iqj0bjwMJJrYJ5vvDKA7zDZiuLfqOElIQMWY+BAdtGwtv5IxQxIKbX8SP2yIyKttsMgBLgLIlN+yEBwelcYxBbaqHIJF9gyVSJEexiO3yF+rziQUN3wuCymkXmYBKAE/LZ1oPgRuaJrgpLbhCNnWXBt0gFPE6vXERYTHsvum9OtbzKsGaK7QzZlSAwCV7doRkoKyq30GuOz4PFRRgBS0v6w7eX2vbRFxKSQjyjJ3qSwGxHQgHztOcgFuOQksCxdAJ343xEmoM1knw05KRy3DkPoi+wZC964dUlSB5FOLvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JgP2ZgQ8Y17baGCLCTwEGc6nED28+XLD9ppoSRJTCow=; b=LEGfBer9sHSNb/cEq2W5fd3QX0WKR4PS2mIColnSqZNcFjE1nPdn2/L+H3QiEr/xh7IkH67wilteZ53dU4Tlc07On1Txsa846tXFEzFBKpAtU+svj7vfILRW3gVRR8mE4AxxrSqWXDiav7fjHEHDWQ8VHJw+rNA/hOlba6cpWJujV+KIdcWK0TdGtVPBoEQIHdxeJ9VuxXR51ilBx+47Yd70R2G8ZUM30VcWyDSoCHP1raN9wxb/9k6UZeAVfmQGNl4Pl8QLbsjEcQbcVVeQ+EZ77RwlNOqUF36o+JN+gAhj8Ii7Fw3q+ymHAFMXHo4SE6TFC4dHZxIvhASnuCMIZA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JgP2ZgQ8Y17baGCLCTwEGc6nED28+XLD9ppoSRJTCow=; b=GoOyB+GZnh2W1lzYSBhGSmIHK+RkbpQml8lMK9tVWsBBQVcO+YlC4QGz/E1D+0hPfM5vQBjLdpX+sohllHGcaTMKzxRvSuKoTsvXJ5/Z/Lnu+LS7MhIRrZUtc1T9nP9y4DisXL/GUQraIhCz7FOVv8YCtPiqxj3opZDFt1eT2Fo9bNYQhfxqBdyzbcAZpORmhLPBFrsZGb3E9a2mHpesuuczYL7a9vUZiOkzH2zT86t2+quqUZ4vLiEPHAwAGoZE+5sNOCp2sW/9PpmHhDhs0/CXJBnKxMxrmY+FwCb/JpbVSfTlud7ufR9LsVoXB0tZwpuJrRRWyjOx3anu62zMzA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DBAPR04MB7382.eurprd04.prod.outlook.com (2603:10a6:10:1ab::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.27; Mon, 29 Jul 2024 20:19:23 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:19:23 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:14 -0400 Subject: [PATCH v8 07/11] PCI: imx6: Improve comment for workaround ERR010728 Message-Id: <20240729-pci2_upstream-v8-7-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=1916; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=TNSd+b5y2IdUI30Q9idwzdMxK5IHuQjkFajPvbPUy8I=; b=2MBJzBHUD0rNYMpINkM4Y3v8wUZKNpvtaW8d0qIWkN1T2SYEBFFQQJEbWnGdhd4uB3RgEuskl QemHbccpzCQBj2PGMJqqAoe9Mc6+KLkpq7LUVe+GiDcwBVm1inVpGev X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DBAPR04MB7382:EE_ X-MS-Office365-Filtering-Correlation-Id: 58f17378-a150-4e66-5bca-08dcb00bbc71 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|52116014|1800799024|38350700014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?q?8FztPn7O1qVkIogtuqWV/ucCw/hLLV0?= =?utf-8?q?Rpj5+Jq+uZsxQpyRUTQ69dzT8jMijS+gTPLiVKlInnjLDi5hSgGRVHNISo1fimZZJ?= =?utf-8?q?TsJ3V3Z8488vTeAU3AcaAR6kyCKmKDNloIfyxAdxv2sKXWWisOyClkqPcUzZjkQA0?= =?utf-8?q?gJpplUlPU/+4gk27LPnESB+iRZnbMqPPZ9PbQyjZsfmEkZrcb8/2ATXYtO8BJW4vk?= =?utf-8?q?+DCNPKUbDkgb8znVZxUEchtbY8ZqNxyFEMjMXu1XNP1tscg48v8uXCoT6vU8LiZvO?= =?utf-8?q?F6IxGSztoORE9TiaHbLWkJGsgrih36kgQyfnl01z7aD8NLkcRey7z6Hl/QLnY4PRh?= =?utf-8?q?V/+vw5maMEojlpcpk+dWIJook4HMUigYD5/lZTz8iYkYCYajI6pj0emFfvKZR6jRB?= =?utf-8?q?biPakOso/LobTTSqk5BvqOXUxaVzfXzq2UeAX1xyheeLpQlbWz4SEdkjJAt5PgK8V?= =?utf-8?q?RnK8nIp9bkv50JMvcEvt/UmaBU+2Jj8hoWh/m+AgNJIjRc897K6wa8oxjsOE8bip2?= =?utf-8?q?ks/phEpUlVP12RzuyGx7yN76Fq+cY/GQAMF9IldBLT0bZ099IWnbbqrhRG5b9P6cv?= =?utf-8?q?2YF1MNyT90kvDVPt3waofEgzh3Q9+0xsR2UQbDr3X9EsCHIeSgGq0tWxQehnU/K/S?= =?utf-8?q?OgKaTRcoJ2Y3ez8pRCAiQxqYG21+8iSffEJqhcl56Pa3EpsGqexPsKmlR2gNjOekz?= =?utf-8?q?mhhAjMtANnc4teRV50EfavSesrFbm6Qbi86WpYzt443arIKorzOaCW11urMVcTOC2?= =?utf-8?q?vGQhOULuZZ5USwMWa1FQ+uHHemDjHMnJKW4EQY50WEiuRaFTCQv2uS59FDXveyj3Q?= =?utf-8?q?Ab1ic6jlUy/3z7RqsQYIGePEQOYqrNNVE0a25JgAWDwCw/oOpliQfHHFavV86h/w5?= =?utf-8?q?twzp8hfZWZZ/K3dAgEq/gMRZioEebk5mbNqMfzi5Yi0Um081IrqjrgjAxmsV/stPJ?= =?utf-8?q?aNyIrYXERJuCfjL5IuqbvlZz/UIlCFejons1MYPMaM/6XHvmawyYs82kfsZrDqBoo?= =?utf-8?q?dip5UPJr7sDmi2beAOOgQZLE+ezyp0sQxfbItyQmxUN5rVHPDsHFB8sKZhpSiKGwu?= =?utf-8?q?NTzO7TE5IrEcvzty1HNM1ao9c0pweSfvLlPxfo2WYUfUTyb575CCet2zrdEzz40qd?= =?utf-8?q?sTEZ+sh/xfPdjmGBHMlQy5Ml30zoY19tg12edi5Ne1E5wtw+250HyC9v5ZNqObt7R?= =?utf-8?q?rDR0aZojkGiVz3m0dVJvyHqsLxZ5B6Rc/Cyw8vPqLI5ZwHCi9IuFyMd0MFSHSQcEk?= =?utf-8?q?rFFj9gaOshZa69WaG0EUJokQ+4KVzMQT51zKcFXaHiUwhi2QjAqxOQpCLlG03pIxY?= =?utf-8?q?zcwuBA6h2Jtox1HiTGyGNZibeIRUCzrlh9EpzE1MDNV3aB5wQvEC1Xs=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(52116014)(1800799024)(38350700014)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?4FK4H4Sgcu6HRuahXJjMLaA0uMs3?= =?utf-8?q?N39n30iY5zE+SZOVrrAn4t97IUxQuegwlqWR9qhycEZxPqXsJn8FSWEk2twSH3D+F?= =?utf-8?q?CVj5PymaSEdU0M5dkQKni5heFtcMYlc03al64o+vNToz2n3ZiNkQREYxzpnuA5uf3?= =?utf-8?q?OfGiDDIzqR7G/1EMmVwBkoZF+JOuSNSmy2F7pSdNdh77pxzRXlVfHO8RSRscooW04?= =?utf-8?q?TptjPpAIdSiRizMthIQNhKa6Aww+KdNt53LZKCVLLULgZ4ivH1eXU3x2HgK8DnLER?= =?utf-8?q?U39zKuNUNkU/KEl2jGnquqaL8crK+laah553+x3ACpfPRjuOAjMxuk38aqvnSxekt?= =?utf-8?q?C0pMA8Kcw5VCeWIECHHhuLgFASdh34q86yG46BW8Oah8Z60yPj5Q2rWaT9vKAMt6b?= =?utf-8?q?HRlONTl750BIvp0r75u7+HLAA8YaSaB3wftu02f7I7mKVHVW+qB9vy65kVytJdD07?= =?utf-8?q?wmELexevhu3+YRoI3/g8W53KBC7ytEXC9zqMrpzW1ZDhK6I1S4+pcu9eSSjkkveuB?= =?utf-8?q?mzU4JjLNoQTDYyJgb1iZxkzRMKefykH7svwz/7SiXnrJNGIuzUZVtJxFewhaKLNmi?= =?utf-8?q?fN03G8EkUK5dI7c1QjbVB90J8glXdODYxTUGsHazQ8cSLullTu/y3+z2W+jE4drxH?= =?utf-8?q?JzkUU1ojnLD1QGVK89QuUgb/waod+p00+sPsWwiy3kypNVN8aqz9CB1S2Kwob8P1D?= =?utf-8?q?ke7AGf5quvgOxpgz4AkYKWR9DrhtnShTgLWFwm1CftmYz4rFJUKcJXSnEUk2f228l?= =?utf-8?q?RIbq/pwjYyYmCj9BbZpqVXUe4HwIAAT7sHHHkDEpIblk3IEVa1Mz1rt412pn+JgDK?= =?utf-8?q?WpvGzUZSkXoiWwLg3TzM46Xb0uehG50LBcal+eLVSmuP0zIqgGAFqGdUJVSTWLwDf?= =?utf-8?q?juNqJtACRzukR8tqs0UVxKoqwacHJkEx8izc4mdvwKgb5mXNfIUh5Lvh7NP2MhfT/?= =?utf-8?q?w2KC0t/2LhJNUss5tQUCHUKcOzOPfPBTjfJmKexhDGdLRs+nFyB4IoGNxU7JUed3P?= =?utf-8?q?GNDvhjlxYSdvYUQE+SB9F6JlGNmrUGcutlGkobh1efZi9zDnrgU/Nmr53fFL20d8u?= =?utf-8?q?aTT4Up1rpqffPQ6z4aHaa3sdGS99BcqdfrXgoVaqti4e/O+gFRj0ah4Jy3w4fXknL?= =?utf-8?q?6+QWUbh9vJGeUKnB7MctsqLKz5LtAfPsmzxz2He+A6Doh2o21IPLgmZQaGNFH+jvK?= =?utf-8?q?Tca2PgtWxF4nIxtDENSsXX6U2qJkG8OpfI2+S3RTp4KN0GZahQllBVvRQo24L6M+R?= =?utf-8?q?vZba4/ukgNQftlqzTX8dxK4EOLwFSJUPASWCtQkcoUClnbedKzKgwa1yhkpQEbFRA?= =?utf-8?q?pHPnRsmQb0n9vHl0gHkCQiskVLeDLYpdp2P6pTAn/lQ1NBdfercmeHsFb7gHn6L/2?= =?utf-8?q?fbgNPv4RWqUhmEzhpU0Odagg32UDfoF2sKVWMOZmVyYfAENFXVQG7eDkkSS+Vmp00?= =?utf-8?q?EDuNYjgn3ZkMd57sYaTQk6G1MHjVrtTEmT5bVs/CGuHCp+IhLrp7ydCYXKu0DIIii?= =?utf-8?q?tWFiWfTlCxQm?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 58f17378-a150-4e66-5bca-08dcb00bbc71 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:19:23.3174 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: a4wvPqwygIKYoOHyV8bbpWKTjbjMxN5x7tY/jqhKhbX+IhDyCSdSSoF0iFCljTTfecZsx6aim46SOe7Os0YhOA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7382 Improve comment about workaround ERR010728 by using official errata document content(https://www.nxp.com/webapp/Download?colCode=IMX7DS_2N09P). Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index e295c7bef732e..6be32a93411b6 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -712,9 +712,26 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) return 0; /* - * Workaround for ERR010728, failure of PCI-e PLL VCO to - * oscillate, especially when cold. This turns off "Duty-cycle - * Corrector" and other mysterious undocumented things. + * Workaround for ERR010728 (IMX7DS_2N09P, Rev. 1.1, 4/2023): + * + * PCIe: PLL may fail to lock under corner conditions. + * + * Initial VCO oscillation may fail under corner conditions such as + * cold temperature which will cause the PCIe PLL fail to lock in the + * initialization phase. + * + * The Duty-cycle Corrector calibration must be disabled. + * + * 1. De-assert the G_RST signal by clearing + * SRC_PCIEPHY_RCR[PCIEPHY_G_RST]. + * 2. De-assert DCC_FB_EN by writing data “0x29” to the register + * address 0x306d0014 (PCIE_PHY_CMN_REG4). + * 3. Assert RX_EQS, RX_EQ_SEL by writing data “0x48” to the register + * address 0x306d0090 (PCIE_PHY_CMN_REG24). + * 4. Assert ATT_MODE by writing data “0xbc” to the register + * address 0x306d0098 (PCIE_PHY_CMN_REG26). + * 5. De-assert the CMN_RST signal by clearing register bit + * SRC_PCIEPHY_RCR[PCIEPHY_BTN] */ if (likely(imx_pcie->phy_base)) { From patchwork Mon Jul 29 20:18:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745672 X-Patchwork-Delegate: kw@linux.com Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2067.outbound.protection.outlook.com [40.107.104.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97195188CBC; Mon, 29 Jul 2024 20:19:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.104.67 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284374; cv=fail; b=fvpmuvEGkMNLKx8Chn6FRnqCENHt+gjMrbifVDGQDcQ84hN5YcxjSP7yOt96C2YJLBufjBU0KHwsZh1af891GoghMU575lCB5wWpfW34eHlT2TnyLTSAsnb8xCAMpTKjXkowYFLzSjPJXrXfoqAFU1eDN5HWxJLDXgM+fdAmjLw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284374; c=relaxed/simple; bh=Sz4wSH9fJRxSuOtKT4ii9bZq5wdfSH0QeE8uwN+gSOA=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=Zl5VXWUrEk6JMiz6CV3v6+nawDL4jouFNh90/rJLWF2O8KC07NhAbQ3ah4eu0nx+BC0WyLBlVH4OTD8b8HaNbW83XzeIGIIIy6Sk53S/jsLaMJqDByCdh4ieyGM592uXn/yglUyyZa0pN8zys4HlcjVuOe4Q8u3pCQmpD0voYdM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=a92F3iMz; arc=fail smtp.client-ip=40.107.104.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="a92F3iMz" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=osuSUH8dhrs+eQInmpCwxHGoy75n+KZADa8X+qPB8ubrr/q+iPqYzbdxWJFOtIhGO/n6Pn3KT5GhZSpfoSA3LBjz0NnXCmReMV7Lj5fhAOZKHO8qNl8vopWcR/CowZoEXNs8zV9hLD2otW/wHNIXT8kyiS7Ag6blMcI88efkjEnbBUGKc7OIN20umDfnNawq5ZvvgOFS/2JqAxqSNS11v0q47/fSUdUJQNT1N5Lvpn/fwOAKmB4O4+t3Rz/TWuVSv3VmPNwjjxg7tXiAU87M/edrMvGOd2zEd8OhG5p3sOhtzczMEn13ppYy4tnaHO0vhusI5PZNBYTaYDSmzhiBNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YMwEaN6yeCcLphdNMKFyLxeCWmsveowSNo0XAum9u3A=; b=FgMkMZcHdwUSF3o5Iz7urnfICyVuoEeg8eZ7NxRGJw1ddjh2JLnucqDQRSxCHsK+Y2X+rkJDVDt0B8p1SudJ4smpaOnskPRJEEHHU91wJtqLX0/0aSI1mfbJm7TLET5SLJU+EdsDU30hJk8nnz7NrFAvTFF2jKrXzL5BipuKyncaOTQkeWFItTt6uXMrOD2BG4Lm7AhBFqc/mah6nmXoIdiVtMeyvmPU0sIsojNvSCH/PhI9Qn4i8tq+yKGPdmwQ23BMpevNHPboUIXfQjczlOThGCELNQETsQLHbEJO0eex8Kx/Zr9t84o8quPms5hQLKyyO/WDU6+UI+4mKa3mQA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YMwEaN6yeCcLphdNMKFyLxeCWmsveowSNo0XAum9u3A=; b=a92F3iMzm2cWftEO95qj+MEIsvQPaHwHwvLuhKX1URZ/+00tOTzS7IMKLyaVfRiCRQV4+9fl7VZVDJOoGGEqOEQIGSp4p2+DhngpGy+PwUHmcWWk/jR5r9vIh37gZfDZF9FBVcgmH2cEZ6hGQvOaAhZxgd0RclQ8FQ6NTALVbUPaEkiirLxIhULv7f9p015H9SsxR44833W2jzsXxAQpsJBl5zlvTKQp6auIz0AErOzeEf7y4fckjwWwgisv2dwzj/aCSx7M85DFTG87HVjE4Is24dkhL5L93whaKkUo/SLm1SIgfrPDpTDtk2dXgxnMC0n3p4eCaRLZTqpUyGbwIg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DBAPR04MB7382.eurprd04.prod.outlook.com (2603:10a6:10:1ab::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.27; Mon, 29 Jul 2024 20:19:29 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:19:29 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:15 -0400 Subject: [PATCH v8 08/11] PCI: imx6: Consolidate redundant if-checks Message-Id: <20240729-pci2_upstream-v8-8-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=1048; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=Sz4wSH9fJRxSuOtKT4ii9bZq5wdfSH0QeE8uwN+gSOA=; b=otQ/qzidAqYKVhiDPLASOsMjdg1AE4Xdv1KHAq/GPRkWZV0hbxj3xmDagbjVAYFjGZMjm4Wl6 OA/fMROuLhpAjkqgLlZ0XgDQPDVSus1fcPcRFd6WbrE1+CUWOf+B3+A X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DBAPR04MB7382:EE_ X-MS-Office365-Filtering-Correlation-Id: c552c389-46aa-4994-0ef1-08dcb00bbfc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|52116014|1800799024|38350700014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?q?b843YccISZjQy4Wq79kil4auaP7RXGw?= =?utf-8?q?gY/JCMjrD+2lJVE0hchfMz990059VAIk/ZWtt4Z8rCELPii2zj8U0BbJjPvoTLjxh?= =?utf-8?q?JeJf1qgbrChVC1KMxMBmMqjzOnQ5mBNO7P76TcQIMneWeV2MNgxE6j/rtOsc7zNK4?= =?utf-8?q?eQpqCAmD1/TaWu+AKoJVznFFjO43hIDna8Z5+vAjftLLeiwbLCNzjx+KNn4Lhx7gE?= =?utf-8?q?jPts9zZDK923b9UkN9k3UYM52ixVQiXppq1V6Zdc2v644kYyZmUOFHcWZFUnegv6P?= =?utf-8?q?Qwh1VgEPBfc5Y0rr4zjXb89uiBNdyKJci+gbz5RWshjshBytw6ZSMplj8LRpzn/sq?= =?utf-8?q?s+q+X7VsYeNsYGt4fC5LSXtVtnw73FgJuiYix6yV5lHS6OL8VUVPz0vXCdRmFTRj0?= =?utf-8?q?cu9G9CrL3YBXhgNL6JHMQvjAGhjrXDBn5dE/M3INsxqL9Y6iSikVAH67eVAy2aYE0?= =?utf-8?q?lbs/78m8GHF1aE/WoP3Faj7K42FR792RLDiyb8RSKRYHL4Jc8e8nrYbVhzJ4tK7is?= =?utf-8?q?RbjH6+iPQdu7QTO+2NNG492CYLa7zis8a45QILYZf/bE1ux7uvy1JwdIiZ8vDYB9l?= =?utf-8?q?WtOZmu8ow0uZ5+ICjmTLI5/3wT8Ukv8Rxv4mcrkronkLG6DwjnIxnXND7f32TL33w?= =?utf-8?q?wDe9JzcG7ryoaFpCKIdu2/cHeXLHnP+XO8rotkCNPTfYWvG84Zuqfh6rCoa3F2NPY?= =?utf-8?q?OtDxveOdNN+yPPb9XJMQhdAeYSNH5irA/rkMg0Ix372kRvhugjf3/9aA3IgyEsAPz?= =?utf-8?q?9TsaygWHCS6edbCin8igzIIr1rR/OhqcZHS2aMafIouGPi8aZQ+JR5TuWFS+JiMx6?= =?utf-8?q?bqCQ6hwqbH3Y0Ss77I7wR/CT63cGpDkAH1u4xA+wrBpuljym/Kcfwv69NiJRDZRwI?= =?utf-8?q?zcap6nxbZKCcKkuFoEZYa9HPh319NvQoZYYeDcNyYZUISHc7JRqDAziTvmupycBl9?= =?utf-8?q?ypMsmDNaWHr9dIDleX9MtuDOm9Y3lj+YZ3NsoBG6ERps74IIPDIhe6tocxJddUgoF?= =?utf-8?q?OTjloI1fvwPvnGdB7XJNGanyNQcibAtOS7JMKU3Unzilnpv33jmSKfne905MXw22h?= =?utf-8?q?VOhSfQiLvvzd4AlLsoPIbMer1jbyIFgJn84k0N9y70DjHL9GBKbfrIwvOzTjlnblo?= =?utf-8?q?VIljcv/22ET59WVIrcfbd2t8xbeBDsLsCPUa71u+m44ZMuhMs/M+CXkomuDJHUu9h?= =?utf-8?q?ZBnliwviVfPLRmbcoFI8UbN0SJLJJ42ZX2eU3njX8FZ2viNNdq01wQzreValqyQF/?= =?utf-8?q?cYnQJ0QtpWbV5msJ0N2saJmqmXI7qcIAlkd9N9AyOLILEqYIAjOwnfgZA8o0Np1Cx?= =?utf-8?q?bDjAiZRQuPR4oeTXq9om5tqn8zIOSAiZBSuXrUcmjzwJcEDDbpgucfA=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(52116014)(1800799024)(38350700014)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?0CaenXoqsnFKTeuxVdQQS7gD/xcB?= =?utf-8?q?2U1vBMB3/OpjOKsHkBVN/26S73+AmxouX5DPylqq/Qgxc2ZDxCVanS72uKDQu8Qv0?= =?utf-8?q?Ia3pXHRrB7G+Wy1duaJRhK569p09AtMTl276t8GKRNxre5qyayJOAfXZ1/hb1uo6m?= =?utf-8?q?G7TvpeTuP5oEuel03E13ychSvif3D7gbMHeSM8mqtTVKJ9gIDhTapcwcgr/6ziCdc?= =?utf-8?q?6O/5ohDJEPbEjtvILxBBnwkdhKp2aPjkCocy0yJkwu/eUYX/P/umgPqNXEm7vpOYL?= =?utf-8?q?hkiJ6D/3yDxP0uy5n58cMOlOjmghYx7qY9vEAFIeg5mV/1slYlG1YmmawTmcWSr/H?= =?utf-8?q?J2U89epoPK3tHTaMEoLEJg0SV+0UvDw73kL9UBfoccEXX1Rp3mwdLbTHRoxWx/PIP?= =?utf-8?q?76E37r1xCR+5n+A8ovgO6ipT14NN9L+5lURdSZc589ucOkEJiAoGUO1ojGwz4rujh?= =?utf-8?q?2nrua9FLHsrWqaFdUgPNrHxg5Wvvr9DWPoHf48jMnAo03QtykFPwKTYzu1xO7BRt0?= =?utf-8?q?l1Yritm5LwIF15IOUjax0lS0DW5atsIM5ZlecyLX8gm3jSt6QSJbJrMG76o5pVi0A?= =?utf-8?q?eQAxU/kEma5pF5hrt7rTJJig9ogisTa7uCFWTwopjle2BmqOtwW5vsPoj9qy4wZN3?= =?utf-8?q?rx8V/6i9mxew2b+9BxjkjqZkkxWq29IwLscgRgyPIOKNVervj9fHEf4NGGUocrM+a?= =?utf-8?q?KXQKiITHoYbuMlMHB/XDtDsWmfdQgyk822Bb3rdI9PBQLVPRvuzSf9nkNmPU547U6?= =?utf-8?q?fQ0I4u8yHhw0UDzp14xCQPGqkRJGCiAKIKV5MUrAXygXk1gYPVSE1iV8MCtTd6/7k?= =?utf-8?q?A5XE1AxPySc2NKdbSlKNRTj7uKn8bkG+f/crRf3DYLZacbZsSebyW4/UsvK8NmfYZ?= =?utf-8?q?WCcRG8dorx3JlpDzr36Qkej1FLbDR1mfwa2GV/8BzRCM4ZPi6sadFM9z92HESDMK0?= =?utf-8?q?Ov8qUM0tp75oy/cG5kKWVoVNRSr2540IyBoe6DlxN8f2GvsZMeIS7R4rgmUZrRfGR?= =?utf-8?q?6PR1H4pLaDQTWRCNgZ+HFmCCT+Ek3Tq9fv6pWm6Dz+eu9FMbBVX+kYDBr4A1dZoyM?= =?utf-8?q?z7Ej5jh5+KqecCyKLMnSZI3WTxjaJu9vW+q3sgbXE9SAtcV1785nCw8p4YBaQ9E7/?= =?utf-8?q?AsVVBjmVbiy4Hlrq9L1QdMquH3FM4PhudaP+5MuxewcZdl6Z1bbGwA6LPwG5AaZq1?= =?utf-8?q?ecQFmuzlV/NDKrKNJe4WhrjGyAkUUa2gMZpdH4ezoKUqnQWBKEw5UaqdZDL/4yxNr?= =?utf-8?q?NoXc/3okqKVGODn8/srSvmVKRvRWpbe7M80/0bx3wCYuImFRj2iLuULWz/1eZuZL7?= =?utf-8?q?V9HRnD89pYVhVHYDLFNgMwQK44yPmkIj+FucNWOS7jqij4l2VXVyYfeieBqHrL381?= =?utf-8?q?g77cvJ6DEuFG7hwec4pwcobGTS+LVNwTO1tYNnLZcpT6dwZ2W5EiIsFqsvgFnzhtY?= =?utf-8?q?rUPJ7mXPAYYrKTmmxV83GMhtJ1br4DKyi/Zg96B1niwZu7g64ctf6Gr00UTOaZA9K?= =?utf-8?q?kO1LIW246d1q?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c552c389-46aa-4994-0ef1-08dcb00bbfc8 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:19:28.9188 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LG8Ets+4KUHaackq1yrkcliH+uKsJWIHL6bIexKc7Neie0E4CUYm9q3xLYc4fZ+yeWL+AMOwHEvVSX+YX/srIw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7382 Consolidated redundant if-checks pertaining to imx_pcie->phy. Instead of two separate checks, merged them into one to improve code readability. if (imx_pcie->phy) { ... code 1 } if (imx_pcie->phy) { ... code 2 } Merge into one if block. if (imx_pcie->phy) { ... code 1 ... code 2 } Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 6be32a93411b6..ccb7cdae32756 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -949,9 +949,7 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) dev_err(dev, "pcie PHY power up failed\n"); goto err_clk_disable; } - } - if (imx_pcie->phy) { ret = phy_power_on(imx_pcie->phy); if (ret) { dev_err(dev, "waiting for PHY ready timeout!\n"); From patchwork Mon Jul 29 20:18:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745673 X-Patchwork-Delegate: kw@linux.com Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2084.outbound.protection.outlook.com [40.107.21.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C99D918F2E8; Mon, 29 Jul 2024 20:19:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.21.84 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284380; cv=fail; b=X/9MEgAvEZIQqJG/knd9QAWv74JMeXnW8uYc+xXhWACWipxnPpNENKiYHVojJmKB4XsPi3fO4UI4N6vI7lteEoSvdupV7xl/4vR115ijvjmNyckTMAGoOgoK3nRLzgVzNvTM31pcyAhullHPPzHN33crIeLCu/3oP+Lc0aorkJ4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284380; c=relaxed/simple; bh=Oi+O5DWRmBU/2zRPk+Ym6Fw5V6Zsw9Kds2smM2X+BaI=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=umK/j1xtjB+geV5Bl6mm/8xNCb6gjQPKoB+z6XffXknsf79vR8Or3zqM/yC5khDKwipTZhJtZ2iq5tt/KxPq4FaZYidyGxB/Wzequzaw35qg7MemmKJqsM5vgddgeqNV4rhzgEG2USPGFO1CQMgx+pzVqkk49WwnkSLfqx+Yfdc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=RvhfKkGe; arc=fail smtp.client-ip=40.107.21.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="RvhfKkGe" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=JnQihyrfsYD0G2PxFv0iRF91LFXjHWx4Zqr6+CEhfzX/v8rTikAJZgXM0DDuvkhlC+tFJzBOXzFirUHGk2ISVj9xnk9WoJnHo2GJrGZTPM99UyXwF5sR7HzsuCqP1yS3heb0AiP/29sDC6/XxJUSO+0FKS6zrr1Ulqa3JPBMGO11eurtm2cq/eoxSYYqUpHnMzd+4eXjNjPaOyoF9j1Eg8mDHFpjtdVLD1Nk9Xx6UY+cekhOsGoVJlxAzq16bOiLJxj/DMh0FhCK4RtL4Z3hNA+ypUakVWVCfXN2dBy93J7zPwbGqm11KenvywFnldbelDNX6qRspXVtDcLxiL2tXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PWGOx5vCfCxn7WgB/8DuSXhHQZCIIY3Ww2nV6/gA1sI=; b=yubfl4x7LRvKcNwcKZ2LuT01M2iicLiPFdClf4gdRgdnDS09jH05Zm/c9XqKR1bPE1EcXzsFq1tQwoPo19HjbfRo/W6vhZU4UOsPhgLOhf8E+gkzcXXRl2+gVwcbqn93C9s23AhSp+6pZOKnI7eIsQthmNf3DCsKxd4fSXFNlPHQX29oiTfcWrCyiLfyrCp3ca0oSWiAnB0aMfV5vrdHfLpj632ZeR+5URZbYmPXjTV0nW6az7moJH3+QHFp8bRvIWjN+j+MUy4yF3oib46o571TYZPRsgu9BSlXtr9iy3F6YRznr1n78Omp3jyCp/Z5+LCOYHUnHHgXr8giqQr1Aw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PWGOx5vCfCxn7WgB/8DuSXhHQZCIIY3Ww2nV6/gA1sI=; b=RvhfKkGe5EEYBSS3fCb+QqPbWjNBHpbync1fyDLaY+v4HDsssslYZqxinBHB07SPJAKGJyd54HyF8A97NV4GqmlorWyzgxAE9+0ZxP/rVDeSKrcwNlghgnIK0+b+42Cv9LiJ+f8h+gQedF1khAcaTG2f36lZSfS1xf3WBrAwVjoi7iM8mJf6M6QaTCa0yNBMfhq931OKR1nt4pOiZia5nt55Vfj93RNny7xDnGDDJ2jixko5PdBWRwHMKLX07p+pUhp9joudNaXWXMj1Fyoz/LVYnK7W8aL0pqDXUZYdC46J9KgT6rRS5E0+4XMW3Q4+ZJTytUgR/z8iokbsu9gyfQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DBAPR04MB7382.eurprd04.prod.outlook.com (2603:10a6:10:1ab::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.27; Mon, 29 Jul 2024 20:19:34 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:19:34 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:16 -0400 Subject: [PATCH v8 09/11] dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string Message-Id: <20240729-pci2_upstream-v8-9-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li , Conor Dooley X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=1424; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=12Cbbiu9BR34/GLddVOaZuBe4oG4iPR7q4gdUQjxKJ8=; b=45QXLun5CqPuBggVcPv0o+7DIUMg0Cp5T8psvYuguwhDz0Dh5D426ZYU6argSivtHqLXPgy/4 dhMd99llr/JBuDMXGLpSYWN+38aNu59ROGnHyJbEn+alfdyQNn9lU1Y X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DBAPR04MB7382:EE_ X-MS-Office365-Filtering-Correlation-Id: ffcb3906-f421-4dbf-99dc-08dcb00bc333 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|52116014|1800799024|38350700014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?q?7QJBjzGmRAzt+WAzLO/eNpFvh6BSpRW?= =?utf-8?q?7rlMZA5Ug8ZAqwUf3sUWLC3qyutmrCW6icHq1ahOl4604w4tg1m+mRAmmA2TyhmWk?= =?utf-8?q?QezEw9T3F+W54yLI4P26Xdq1aeWX2IXTUjST9QfFOOeSagsDao+sIicU7kYxdc3OI?= =?utf-8?q?V/2NIAxDh8pW0G/ov/+rdAgTc2WiF8skB7fcRDDhe+qHL6KDGWOnkcQqsLeFgw9X0?= =?utf-8?q?iz1lKfwZcxFuzoLD9gA2jKAuQPyI3DQTX32pIFnWdTDkMO009pPcr4LZ5lyuYjPB7?= =?utf-8?q?QHgWut+m65HTV1CpFKmdFIcWqMeuqQyc4BtbFWDDPYEb3Ov4bXWDlWn51d5phAEa9?= =?utf-8?q?j5hexYV5ZW/R4gI0AScCzESN46KYcIp4oK2VZ3rLP62ohCzA3Rf8DS0ZIhPpfM4mz?= =?utf-8?q?cIaOSWChX/OyQd5elulD2iJEGUde1KPla5zH57mMbWI0eHY0Xt/hVaXBANvqGZza7?= =?utf-8?q?jMaVWFdhFTJ8FVYaK4HYC3Y06V2A4EcpcXWR7ys5F8JqnwpC0hofp5J0oG1Rl5xcc?= =?utf-8?q?gynZvCU2DNofxJ3uF3Q8hhVrdElcdY2+XdIhRbllIlyDFRdZzBEitHtejC8Na1Bq1?= =?utf-8?q?z2BwXKk7P7AqEE/HDKDaGXZ9Whg/Q9Ub9BWrYXUuDV3SFQ4DTrAH+mASIsHaMA3ZG?= =?utf-8?q?FAL+J8QW+2GYjYp1RgZGlsVE7+pNExMqwA+UnRiGThDKle6ghHe5mELkBAQuUsILE?= =?utf-8?q?HQOd5F1Gbl90q9UQyNFzIvgHzdYiWSBvWF92OqbN27ldviqPimR3TA25eON4vXUmG?= =?utf-8?q?ZI50NotYWCa/RK4dLsBk0Ym2XfEjvz8ZqHbThy+W7hWMtoHl8zot2nkyCvVBSCj8Q?= =?utf-8?q?FAC1PlMDxCw/IugBvQfUxT6UPEP/439vYI79guScfNOPpRnXbw6CZ3003mZgVh2Zh?= =?utf-8?q?yg/Kpq8og9RmA8e1wFuVK7HUL4r++bmwqP3MF7dooAJY1czDEcpA5DYDkM42XEgt0?= =?utf-8?q?MHoQzAfzPgtEOxx0IYWGGtieiG04Sgix3VRxP8lvA1A6gH0Kk9NnPnMZw8lRET5iL?= =?utf-8?q?khgwUdS7OaHZDVBI7hZcKD6k8obdqs9MW7qdmNcrLs4M59wu8uxQhWSgKkT1ltG0a?= =?utf-8?q?ZNuy/FZVmy+os42pneVsJN1rs8Wpt5Xgg+e5YXQBdILzmfElMaL3aJZi4z2gS4/xp?= =?utf-8?q?4ARA8ox7zkqaqr6+cE5NVJnyOpDdWLexajr4LLky2jSYILpBAPHIm1wW/uVhkGDXL?= =?utf-8?q?MtcoZtyPi56hhI/v4KXHf4m52MYpdZ1x70rR3DPN/chKMhb2vaqecfBxiK50oRykw?= =?utf-8?q?9Iw9v+ubfkQDTdVXE9wiy2ulu7YFAANk9PhhQMf+RvUuh5gh3s4Fe9Rbj+4NDqh0j?= =?utf-8?q?UIEqc5+nQOWffXkWl3/+imZJYB+TGs0kaFIzWIriyBnQqeFGA6KCiJw=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(52116014)(1800799024)(38350700014)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?ZbRL1KnKxK4RRwggWfsolvT7nMWb?= =?utf-8?q?2WQMxei5t/TVif6YvJLohAI6Cyo4LjLp8phHDvDaTUZxycccwVK8VJOxnCIB/jMmg?= =?utf-8?q?adayr3DNUiecOPIIwTjd7CSaL4slgNB/YWK/LkK/VQ1LBYr94RFVVuk5BvrPc0cmi?= =?utf-8?q?FgnRTj5ic1fta5LLvy+TYOe1YiEJqg028oqiwlxI1LFfro+h5ECUQzibmJgt9n0jD?= =?utf-8?q?GF9A5CG+fNjw19CTELgfBrZDfDR32LaRpywhc59Z8fpyuYwe/q0KfvpKMqfAq0Anw?= =?utf-8?q?22OXW+0rJ7NvUg1TFZ3x/QhP4LwbhI8E67NCE6BpwBNSPcGC+Hx07dBRFX9i8bezD?= =?utf-8?q?Elf+6n3qIjW/rR7/dl/Jf+d3C7yV9J6FH8plk3UfcVvlp/QXxpK0WZPWkhJKfA+ZV?= =?utf-8?q?uwlh1bJDcPgM1nhaNAk5JrrJdxbAEs/ou2i2g+t92BSn72wTHZSs7nbk38UM2HEv4?= =?utf-8?q?Nf/ec8GcVzpJw/nAd+KD6d4r5FU+n+4/j4bivxIBvCBSr6n9i+nWaUnGyY3kJmefL?= =?utf-8?q?bMTs+b+PDnmyO1jNP5SZngo9sIQsHmaRFEtnhKjoMktnqAUEtv3cSFrpxLX3FAzD8?= =?utf-8?q?LEKNQhzvwRjVFNH4RaWhbVdwXAzf8dwyGkRfC9H3LdJCcCmleh/NLCvkABJ6YOcYe?= =?utf-8?q?1RNcmTSbw+N9jWZFNf1LL/9BMbrVL6kiFluvEkeOwkAXcI9qN9j19C+B3FMZJNksh?= =?utf-8?q?eHFEcJ55sLqiD36e2k9coIsJ6bRtp14etRR6d5U8y1xCIjl7/raAdNLHrGyqVoo9x?= =?utf-8?q?GhLMnjW71Q637rpi7b4VFEPT82UCBFRF+vX0X73xqP0wJavHCwfYJ2/n0GO1EgAmI?= =?utf-8?q?x6CtpP1hINQLHryXVpfOSrF+myU/niGbg/8I3B9DG/Fsn6leXWgquXgJStbM49xIK?= =?utf-8?q?Kk8w389RfzkZu1Ef5b4AZVDdAc2EuFgFfRg0udBlSmAzGUQM5bZii4i+WSzlz2aNa?= =?utf-8?q?06koi7MyjCh2MWZ3YPcioe9n2O2R4lYFWXsjdC5XR9UTbkKdebWi86GmQyojWQt5c?= =?utf-8?q?paAyFIaRIGVRcFXh9t1SqEikk3YFqZN+Zjm3uSpK0k5fZVnOqPEmPfFW+TkYlkNAk?= =?utf-8?q?eflGycyU4LsfE1xSfPbOHfqzeeQj7xSNaRQhOQ8+pcLln4JInVcCVRAeL8kE1aSHT?= =?utf-8?q?PEzVMfcd6kWkAaVZ7VFvCJ4ehSNYOHI2GjDwQnyk4XBJDdMJYfA1iSv5Ae5mqZrdF?= =?utf-8?q?C+fU5dTmE1JwM+SEYCPWwELbtvuneu66eTNF/02ORgiEF748IEVusCnIHBFfVrnZ6?= =?utf-8?q?xgvEUNrU36iwXTEkrRcJDFqFVA4Cx54PrYadwh0oCxEQQqn/bMv/iywufyxhT4i9e?= =?utf-8?q?DTseYEfPXQ7vvtvOHqMud9Yss+FjPqXUAmFP9nDeDwYN+kMTZSR50VoTs50Gf7ZzA?= =?utf-8?q?we2sm7kIubgOg+SW2RDjx8xxfUobYHESajW0O0tA1edBLZO/fq/7GEXDE36m+b5M8?= =?utf-8?q?iSHYZt66lwl14Y0tM4SGuX++rnOT2ORyj97qwH7JqP/17eEOtejjyf6lvkGXEARfX?= =?utf-8?q?3rWbyGLs5seK?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ffcb3906-f421-4dbf-99dc-08dcb00bc333 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:19:34.6519 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rMHGiugzNjGRP99CLVYip27yYkONduDvaMTivapq/xiwK6zZzOtFUFeKS7CjWGe22j+7WKH88X/P7/2VTh/V1w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7382 From: Richard Zhu Add i.MX8Q PCIe "fsl,imx8q-pcie" compatible strings. clock-names align dwc common naming convension. Signed-off-by: Richard Zhu Acked-by: Conor Dooley Reviewed-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 8b8d77b1154b5..1e05c560d7975 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -30,6 +30,7 @@ properties: - fsl,imx8mm-pcie - fsl,imx8mp-pcie - fsl,imx95-pcie + - fsl,imx8q-pcie clocks: minItems: 3 @@ -184,6 +185,21 @@ allOf: - const: pcie_bus - const: pcie_aux + - if: + properties: + compatible: + enum: + - fsl,imx8q-pcie + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: dbi + - const: mstr + - const: slv + unevaluatedProperties: false examples: From patchwork Mon Jul 29 20:18:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745674 X-Patchwork-Delegate: kw@linux.com Received: from EUR03-VI1-obe.outbound.protection.outlook.com (mail-vi1eur03on2049.outbound.protection.outlook.com [40.107.103.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 677D1190473; Mon, 29 Jul 2024 20:19:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.103.49 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284386; cv=fail; b=sXgUCzvS0u7OEG2hzStgGizadjgBhPWIU3POnlNxLpMsOI83wkp7YPyVIJ/XbQFn/m2KvQ6eFp2ej4TVIP1husbe5qAvijhMTcExu5DpGoZZVeln72U0/7hRsv3ZYTmTMMfx7Oi/0dcw0aMWuOOkAwFK0RuXuCeZvsaOuh3VljU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284386; c=relaxed/simple; bh=xnegrrqq+Q1Ekgre7IoRsuq7FwdKEEV8MnDreE+OHeQ=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=e66IJDnblFO1ytTREK3MY53TEEns0+aazdjV+//c7WsiD7Ad/ieLazhx3nmS8CZXd+9j7dXUzQMPkRkXRTKnfjPM/3g2YIXAKH9gRo3sj2tI9QGzIwrhwuCh3G6KFS37X8bBJpG17yjy5Krj48SD1MN2HLegS9caLrEHwaXCvDQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=ap+1KBwS; arc=fail smtp.client-ip=40.107.103.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="ap+1KBwS" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=U8p87ruLpFvkif9bPJmyTeVpdHisL7UoscE9uL6Y8BJ6uEOOQBQe4L8NRGF3+/+h3VMXL0/QtLpbf1OkaoT/a36uqkrU/ahepcUhSKQbj3pTAAS4dnDZWTkr0ovFPvUNMwk5To3I3NVKeut2dFvXJmHYs5yHqIf5ZwNTp6XeOydBKSKCvHJiYE+0TmEV9vCZG1WDnzZa+rmdEs/r2uEZ41rPMirCNzetNe4eh0EIrZkJYLObY6IOetZA9Wgtyb56W8zTx8R8NKmRVdhhG0rVAyH2bv+28j2FXaKm7td9areO4gZwb2Fpccak701T59Jo1p+98pM5YmnxIx2PPdphTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IBwLRFPfd+0byJrsW+igL3Gd6ozPrhPd3TitZlHjCHM=; b=T4aw5KUrKVJocWNMxB4aOocYy/G+aHSLxwS9fvT++JZ2H5J4JCHyb6ic1RDhDdVPcaScI+pwHd+jxfmN6R4f1C6nYY5pERY6GQIrDUVkgZd82v31Jo/EUgg+vUosuVrKYg4lnNMA3vVDpi33y3IyLVY6S6B/7iLYb9kQ2vaurTrIGr/0Wyzt0X1YnSpfPk3voW+xCgYgTK+vr40oNKXrQdk8iaH4Q/+8rBLMBAO1NhvdRFvbC9r+AdOUMuqOImdAwbC4ayRY15Y84y52s9qEZXNxqcZfUK4dcGnf7XtZo2Q8A+nARXGEgnr8bXz9aHy65fnZMMiCc5k8ZO8r8rMAkw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IBwLRFPfd+0byJrsW+igL3Gd6ozPrhPd3TitZlHjCHM=; b=ap+1KBwSyeEpPsOpbQNhTy+2+y+1nI4pVrvwOSD2NX4ivw73r9xldX3f73RW/aEhBYEw9YIAP4yalyvA7UU4FEJJEQdrxWV4TQb0sbGMsWguVA1pVcYT+mgUR/lwUpg1MFFuE5J2c8sJ6sTQzyIHWCowxF3AwcKsQuFUqGYkXp74HvPj6BeOrHSci3uiMyf2z7p9m+nDuOorr7cdIjtHIUE21kL/obEd2nzusgFu4V6BGl7UkvW8hxmXEGThf85i4WZOcmnbbNTcNq8552/JVb/p5JVGoqOBmhyoX4C9ZD+F7HqA1cW5qooxtK/GSm4rJVbP+9/GoICA0BWcBNEUTw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DBAPR04MB7382.eurprd04.prod.outlook.com (2603:10a6:10:1ab::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.27; Mon, 29 Jul 2024 20:19:40 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:19:40 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:17 -0400 Subject: [PATCH v8 10/11] PCI: imx6: Call common PHY API to set mode, speed, and submode Message-Id: <20240729-pci2_upstream-v8-10-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=2619; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=xnegrrqq+Q1Ekgre7IoRsuq7FwdKEEV8MnDreE+OHeQ=; b=3FmqDsHSTKKkzp+9sX7JBJOjNmCre53DefCsAe67ExslztvYHsn8f4rmrntF3dj1hUY4im/Qz GITWKhfUMSGCU0nCedF5e4B4e/G+HHiAiwjoLqsBpkEQmB8MD6SFm4W X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DBAPR04MB7382:EE_ X-MS-Office365-Filtering-Correlation-Id: ec0118d5-3f30-49fc-d490-08dcb00bc6ad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|52116014|1800799024|38350700014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?q?6Y8Vko0eY3aPhIMDdn4EVe0fXREWk5S?= =?utf-8?q?BHhc43GZZaeuFLt+pvXSumKIGffD0AVKjDimnnwa58MZ5BGa+2/F6oKNn2qTr7RoA?= =?utf-8?q?ezu5YSqHR+aHP3/78VzSSUCpbvQfsuuVKQgxtOnGuNkmec+dem/IXj4uqZE2VupuY?= =?utf-8?q?X0TFSG/c6Sfo50Xs7NeHKs4nvpsfCVXiR7afNnSCmXeXgY5OpzM9gcWeidgNVq9LJ?= =?utf-8?q?A+bY/wBqPt4o0bwi/JnQ2pUuCpBcr0l6cd4Y8Vokr/fCdNzNPSfSTThI5zCS9SB3U?= =?utf-8?q?h1hbv9FvExilJPI3aG7qrvgnl/7Zvz6juuD7412xW+rAlNTebBNVpifYdZ3GMSW8x?= =?utf-8?q?3vb7PTZVn7BfhJtQcHMk3qCQDatXzUkohNOSRM32/ci1osaGy9I8VUByVd6FlItPY?= =?utf-8?q?spuxeknuGE5S5ztIG2+KQ3BYYhrWcNTBZ3qxTV1MQb5304PWfp+UPWVAldTOrgk4A?= =?utf-8?q?18za7MqsBfVvFrJlFl1gBbtKiBlISVBFX+ktZwXh+fIGrXl15OLq4Z3NvB7CCd/D6?= =?utf-8?q?pyvcSJNOxp8+XXdjrKyMjwGP5m/F+ekjQEECddDFTGjElZngI/UBk/SPaIhgBrnZg?= =?utf-8?q?8D9EkoYddsBd0kTK17ZT1w5IAX9fjZg6zFC65LFI7o6DHOANIvaHEMtgE6loTgk0f?= =?utf-8?q?14D2gElUIurF1+eZoWqTDUKdoyRFgSGJT5bisf5Vo6MxjhypYyioYqN95FtYjhNbB?= =?utf-8?q?VABsksnInPc54JSFP2DajDO2sV/wbWWoqw3OAyJrXaxxqenWnaujEHQ1/1dLzicA7?= =?utf-8?q?FuS3NHROwsp3W4LetIK+MzwrS+H8vVx0iFRDDkfjEJrDTqG0x8KiPgkV2hYaPVsym?= =?utf-8?q?FbjZN3HLksKr7RXDQrGYHXqJMCO51RAyfaNnvz42mINxl5F5ZZyMkpdjqr9P8eBP3?= =?utf-8?q?hel6r1BUfdMm71MMsd+G3DDNiRtl8ztUiO8CNfpcJ2VlExUst2La2cDqvSr6LJGNN?= =?utf-8?q?WctiKFEhXjrZvJN+INpoTqrY0iPffFQzMFjPZlVlQphcwX0c9s1fo5xCMAThCVHmc?= =?utf-8?q?uHnwiN8enkUOeIUpHx/LQ8HLJN/G4AzQSHe3ybPA4RmwJxfpY5hUL2K/n/zmuLjUG?= =?utf-8?q?6jz4nHlfCuL2yYtpazBiYAu6syOZCefho5cdrvwm7DIHLg5vwXUM3wqlCpKxnb1++?= =?utf-8?q?N1+BuY8fxu8UdNEV115OXRRPK/gHUfFyLJedUUrV4CCdmR5v2Rxaib+YMcYA7nh/E?= =?utf-8?q?9Ej/wS6dqH3WttwnZhNo7FQO+IE535BmmDAS1W36VxDeYXxn4yoxShq8si+UTtL0V?= =?utf-8?q?jdzLTA5CUgxX5ao04Ia7sPTpkP0KSLaeEAVul4AGnzU/IXNcHbF4xhd7lrpdiVlnG?= =?utf-8?q?HtAY1vfsgD12kfVX2wmkTkMKtJtLuPlwNiA1/l1P5+ujkLVVBhLt/W0=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(52116014)(1800799024)(38350700014)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?3rPjfHFh/EpuddG2xRL1XU/Lc1hG?= =?utf-8?q?YKMrpPZ2bal4cjwqoSCSZwMk+Afm/qzFfjn3cimLNv10oo3YDJAPPvUMes/jKPv34?= =?utf-8?q?p28rB5ib9qscsQINQkZTyAObdvyj+29huAz86QktoPN91iejHuFBNLB7J/Ps5TODZ?= =?utf-8?q?03w4g3YMn3JvNZbUhYhINDeXE9gads10a0AHKIYD2YKtBMuAKPZXNZMTwAN5Y6NWy?= =?utf-8?q?b+b7pc9Z8/gkIfdF1cx7evzP9idLR69NLujAHV2xpr1KXpiAJYlwhwHh5Nm/SUUDv?= =?utf-8?q?9qZNE4h5X7ZbEUucgSXZLNJUUAyJFD6FtqISkdf0svkn1Smu9A5y4MrxmPPSWTsMS?= =?utf-8?q?Edx/EBQDAINb/yr9xgUByw0pngmv6ma6hP1REx2CzwcY4DI3CPDQQJJYw1S2FXHFN?= =?utf-8?q?fddQf+BclzDlcUri5bM5QqobwszpwxzQP8/k/4K2W1VtT6k7l0F3l+74lnp5/YD2I?= =?utf-8?q?GJ11Qq+gjkhfS7DV6ZjE8pNYZEUW+um0b1XyP1vNQCafcIAerDv4bv1BMnIdzxV7j?= =?utf-8?q?SAUeun+cwQqnZ3rxTDLXKwMa0eVp8UMK4aXjvyjT35ViAsEOP1r3hkJuKzHxOVUiX?= =?utf-8?q?zUoqryiXyBtUa3br8Si/ojTTwtM5n/rBEtmXxjY9igsU/QETRkYqXfg60+oArY0zI?= =?utf-8?q?gmOPQ19vkKaKKsHRg5N0SYe9aK/7iuqPnrjHcyaxi4zMdGtkH2iuBdNjBqhdy9x/5?= =?utf-8?q?XC/fYX98ppyhqOQuiaY60sNW/wOkBZtws89c7mf+j1Np1XS79I6rQC05CRpzdIdX3?= =?utf-8?q?wjwV37+jmOKLQVHkBq8O9mfZn11IDnN8iEv52diMdTaDVyYuIV4dYf9GYcQc3BWQ3?= =?utf-8?q?7spauEJeVEuP6u9vrZ4XariOQorQz6XG/gcAFK2VmJs6bMoAVXXTRakdtiDdavNUp?= =?utf-8?q?ytjsa9tEDwvZ8PPXWbDf+GQ+x+UAuz1FsqVyIykW/y+x9CisBlZjIVD135btwCWCU?= =?utf-8?q?6fFXaAoUEP75qzoFvqnPQGfYXM/Uop1shmvS9hrrfdqyCrDFK0Rwlz0/GtiuanZI0?= =?utf-8?q?DIOkI5B0unNSK8l1oluoaeuN+j7RiDsfBnQrsTNBQf1MRR3+0PfLeKGfoEltejbdS?= =?utf-8?q?M3wJGWKiRk9VUJjQOgufLDprGTUUYbawMJKFPp/0aov1ZAbeqfW1Yscy1Pgav/9YE?= =?utf-8?q?3RobtYk/X/PjPztLI4cZVkAmQbdjGm4AFJ+Jqe7+6/l38C7qmwzbW5Fqg/0flLjYt?= =?utf-8?q?ELRcPHK51AKUlz1F1oGAc5xk6Yhv69rz89gr3YhKjO7uX8DvtuSzKpIZ6GDmGoADh?= =?utf-8?q?hFHCpNLsVrf5wmU/97u5fqelWwhrfOD+LkoAgKKUiH0G+YHosm93TidpdKM62X2XQ?= =?utf-8?q?ZyAaTnMvwzaDsUP3bczf9dpbGekFvpvssJXFAZpYIZIwvA1R7df3471VEnlJRy+C1?= =?utf-8?q?9xSOjZ7hcAKTMw9FgxSinX4zH7AWXpdJJZBUj2z7btDBZ7z2NZbb3DT19yQ0Ebu9S?= =?utf-8?q?IkWREBqokI13v34DGpYQtH09REQ8GywnlVBamZiLlQbCD9vjJBDrB5zLxwPPYrD0R?= =?utf-8?q?Lfg+vJU3Obn3?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ec0118d5-3f30-49fc-d490-08dcb00bc6ad X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:19:40.5169 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Pw83kBQPGbL1dZfbBLglZMVmw7+67gVVExWGmdwkOLZRAk2p6lIHO7qOdhrkneLVbYeaVgmYhCpmh1m6QwBIzg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7382 Invoke the common PHY API to configure mode, speed, and submode. While these functions are optional in the PHY interface, they are necessary for certain PHY drivers. Lack of support for these functions in a PHY driver does not cause harm. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index ccb7cdae32756..91aab0288fdcb 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -227,6 +228,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) id = imx_pcie->controller_id; + /* If mode_mask is 0, then generic PHY driver is used to set the mode */ + if (!drvdata->mode_mask[0]) + return; + /* If mode_mask[id] is zero, means each controller have its individual gpr */ if (!drvdata->mode_mask[id]) id = 0; @@ -802,7 +807,11 @@ static void imx_pcie_ltssm_enable(struct device *dev) { struct imx_pcie *imx_pcie = dev_get_drvdata(dev); const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; + u8 offset = dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP); + u32 tmp; + tmp = dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP); + phy_set_speed(imx_pcie->phy, FIELD_GET(PCI_EXP_LNKCAP_SLS, tmp)); if (drvdata->ltssm_mask) regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, drvdata->ltssm_mask); @@ -815,6 +824,7 @@ static void imx_pcie_ltssm_disable(struct device *dev) struct imx_pcie *imx_pcie = dev_get_drvdata(dev); const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; + phy_set_speed(imx_pcie->phy, 0); if (drvdata->ltssm_mask) regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, 0); @@ -950,6 +960,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) goto err_clk_disable; } + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); + if (ret) { + dev_err(dev, "unable to set PCIe PHY mode\n"); + goto err_phy_exit; + } + ret = phy_power_on(imx_pcie->phy); if (ret) { dev_err(dev, "waiting for PHY ready timeout!\n"); From patchwork Mon Jul 29 20:18:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13745675 X-Patchwork-Delegate: kw@linux.com Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2068.outbound.protection.outlook.com [40.107.22.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B854E1891A5; Mon, 29 Jul 2024 20:19:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.22.68 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284391; cv=fail; b=dD9xhvzGb8zt68mdLoQ/3X2wWqF/GCjq2g7sJTJVydiWUDkwcvbRhWbzjHAMYL4cC26km/pihnbOsQJWp/+AONIeow5bdlX+VyaWOYiI8pKUswTcbQLKQaymjTf63k7owQEQn9aaklFaDSz8iEAEkBjay/LFJV8NS65T1XZcTbA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722284391; c=relaxed/simple; bh=KdZlyCITxZcXwj6rdScVn7jTqQq3WgNb0RtEfw8b6tA=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=tK0eF2FKeWICM5vRbcl++z3eKBxl7C8Y02KmxHCUFahl4DKymEwpvT0mJoLs3ZiNCJ/PW3V0M8PUMbCSwbcv3cWm8GDkiW4INTW4gHxpD2kh8C8EvtogPoLVXVjBzamnzU6l+jNcJ4QqlpCggz6df5trL/UrJN29fRBrIJA1B5E= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=ai5Wt+cs; arc=fail smtp.client-ip=40.107.22.68 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="ai5Wt+cs" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=WEaDqVT4iLB/A0Mka09DZnalNfOFpLkgmauLGyhWvZMs9IQSqwBawtPqDJV0LN+1ICRv9gI1SFfuKNibLq0ij5UQoxlQU9qinPUBswLTQME2c+abzNcvNdTmCZQ4O/A43vg3lJBy733x2WbRDEgQ4kn06RkqdZiofcrBjc8cBxg5Av6/xT2GpVSYSeY91rxjxpedwnyftUUshGMLrwDatUJxKDuiLf0YL6CPHrHudTSbyHZ36x2k36CYPi+/DxGjspiFcMXji7GOEa2vjS2JtdZTDIT+PG4n0ciHPaK3zcYRKgij4bHy360nKpd9Zgfi30Rso3LWu6GOO06XJBC/Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=r2iprTHuLx7USQWsCBZ4VtJzBtVOi1XxZNwYrdt/NJA=; b=IIjWtwzLW8BnEoambqFpY/GMw4AwFv7twHxLFp2O7vC0hiWZTVbad4Ip4wJx/Jy5WirGJ1IK5k8Th7zinu1Xky/h3iAB24pffb3LX7c9QlWMl9fUACIuVWX5aSyD0Kqfp+yK/rBTGiLRAW32koMMAIUFGG7q6ubXpAo2pJcWWnofWvbjfNLaNmgz8KyRJBoMLzehH7GDEEavxHosGOkmqH6oktNTYVcLuu4BpwAznRt87zIQ6x+v2EC7213O5b9Z2ZOIgukxdNMP2aeP5/UpOqbdbHx5Pwk9EA39wOHTTnBsMEQ+zD6T4rk8Vhh2Vwtstvif9ptXoJjNPtql1VWGsw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=r2iprTHuLx7USQWsCBZ4VtJzBtVOi1XxZNwYrdt/NJA=; b=ai5Wt+csG1vGfdP5IluEPeqZA0nYgKnLyS7iUtvoWxUHcu5AM940eLsMsuaYsQBX1o917g4bjP6SH3uPKYX20htxi6Ul6R87fGdOnFluZuREZIyIhGPoBb55GJbgCWe7Jl93pXqzPX3nG84PeXlFl6Mz8d9H2ghpioIFVgd9AuTuoJTSn7wuoxh9aO7oYqsSRoA4+uMrMh7+2mHR4iu4XKNUKZzSU8ad7MifV3iusUI5uIK78xs2obc+OoXSQKt9M9LpuZu52calV1E59eeI8x4hlikGhs9TAApW0NqnxPnSCtcRrI84tjsVFOvC1cXBu89SSSMihbnpj9DtOyDGNA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DBAPR04MB7382.eurprd04.prod.outlook.com (2603:10a6:10:1ab::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.27; Mon, 29 Jul 2024 20:19:46 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%5]) with mapi id 15.20.7807.026; Mon, 29 Jul 2024 20:19:46 +0000 From: Frank Li Date: Mon, 29 Jul 2024 16:18:18 -0400 Subject: [PATCH v8 11/11] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support Message-Id: <20240729-pci2_upstream-v8-11-b68ee5ef2b4d@nxp.com> References: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> In-Reply-To: <20240729-pci2_upstream-v8-0-b68ee5ef2b4d@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1722284317; l=3899; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=FeU0M7scoVtlq9n7CVtHi+M9qoXqi9J/fKpHzWWulhc=; b=ly3UYvzhU1A3G+y1qaOQQb5qwRHB3R/VA6CXczl0nDpWHA7oEfKYTPsH5ivFHu2OdMjqnDXR/ Yosu0/a0icZDq1BnkWMMwJQDvdkObthOSZvfuGzZiXgxxBpOTk7hxoJ X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR03CA0069.namprd03.prod.outlook.com (2603:10b6:a03:331::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DBAPR04MB7382:EE_ X-MS-Office365-Filtering-Correlation-Id: 0997430e-39f8-41f3-f562-08dcb00bc9fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|52116014|1800799024|38350700014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?q?J2KKce9TVyluVe4VmKSVe10NBsab7If?= =?utf-8?q?Q6L3zV7HOI/PUbeodOMVfPtp0djCRc7JUusl1dnxWPX5fUJgEH4fIYO6FMDwXKd3V?= =?utf-8?q?sIkXHZNUw/AXiXyJLoS47+C9e4GkbsTd3+jA6mAL3z4/vdV4XazZbRyOQwqOj2Ps7?= =?utf-8?q?kKyP4QFbCbDErDJJr5hfEcwpywsy6qOSi1dWG5TE+jZx9oi8q2XnYnmyTPuZaOWit?= =?utf-8?q?S/5JYAketfIOajH+yjagdOeypcktQPazggt3BFdKf+fZg5Cpv8QOj2qTYTNnaIaXd?= =?utf-8?q?u77T4v+Oihb58t8znavpa4GQdECkOZmMVFd2StwIB3CEyrzP5+7On2n2HToQfBOus?= =?utf-8?q?HCfsgYZ0UvXJZDdgVYfdJCFZbWqs9BO9ZJP3o0vl2nLVGDh74A0io/XXguDwDYV3M?= =?utf-8?q?Bz3hlvzDzxach1fTaDVf3kmSMi57CaTSOWlP7eEN/K7xsktwv+XTRhhcHXJG2PsuS?= =?utf-8?q?l/CHq3IdWudnVr5nkIMKzk9IB1SgPhuzs1LfW2lzhX0j/HBqx/aX1whB5DcRgAKrU?= =?utf-8?q?7X2JX0tX43GfpGhsCKYxPDPwQHFOwndkOA8oIRxZWNfjFkju7qPWRxyMPSITlBCaV?= =?utf-8?q?uhkgabC+oYTvIhfxJWTjJ4X0+ILhca/FpyS3+Qw+BhGk3CEr0vgz1liB9YfpiTqjE?= =?utf-8?q?DWDvA38TQbTwY3/2iJh+BA0ZBRPASYB/4Q5pauB848v2dxIuCtgURekpTqEiWOsHI?= =?utf-8?q?RC19I0xLOv4By7QtHEB88InHs1uu45yi5me3OQJ4LW5i4YfM1iqD61mEPKAZ11urb?= =?utf-8?q?IMFUiWQj1Xh1ld8RMCzijWUcDZneJjG74eAGnZ9RLMGgUyaIMi1uJ5oPcY94x1/JZ?= =?utf-8?q?9Sofa2zkZ2e5eEQ2DFWXWnmpw65hO6yZe3zN2u7hVyaU6dFYAyrc0aSQSY1T3qUvG?= =?utf-8?q?cGz9xvkYSACPFjOkMqYwyiqYMKZ828L4Yq3y0ueNOLHa1Fs1+BakpyLgMFFtw1toh?= =?utf-8?q?aeW7ypgMqz3nglQf3V7Mxs/OwDLf0gP1yWl6nBPAuxD0tKatOosy/Lvu1J8zaPy4y?= =?utf-8?q?/iyem1mowHv54Lo7P/Ahe/Jhlyi/5bSQGy5TqGrHuX3Ei0h33byTAfUzhbusJJORn?= =?utf-8?q?gWXUEuxXpv9B3dRKXCC4Rn4QQWTLC5AM95xvHGiv30KoyYRpuzabCgHZilYR5Goqj?= =?utf-8?q?SxSSiaOvVPgHqGk+47hRquouMc0KFx5d1YpEq8Mp4xd8AQuu9p8UH08kUQzhJvlia?= =?utf-8?q?WpkO1aq3Y23edJnnHEfxdFaZ4kUrxjqxBorAeh5gOPI2+4PrET/h9RZxPJZTHoqf/?= =?utf-8?q?3IHlLfEfzXXbl5ia8mN6nkIIjei3dTCTIybsBHNefxuQLTUT+eFlbTp4ehlYMl22n?= =?utf-8?q?fK+aMkBavKkW+MKEXAi/P6AlMcyqKPOvRR4f/O0nsv1tlrA/w6/+w44=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(52116014)(1800799024)(38350700014)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?1rWbNo16hzWFnMT89nqRtD5gl0RQ?= =?utf-8?q?kwnp/0SptA3gFgtIDybGy0+mWz7Oldf4qI0Vlgo3Igh0+knvWFhHesdJRWEcGe60Y?= =?utf-8?q?rZNmXtAk/4gK+7orrZhREMZY/ucynmB3XLk+nwuyJz/hNISmRIZsrUdSIA5vddgy3?= =?utf-8?q?pUiQCnVL5+p9pYsGJCUYLox8hsBcAoj9sThAZfDWo7eBWNbShjAGcIaG4d5gMLS/l?= =?utf-8?q?py5U2Or87kzS4JPKye3d1ad1XbHtd1pavmteTFjo8nRQzZeVwa1jHBHbPo1iw9DR7?= =?utf-8?q?6QCMnUhZ3a5fKyBA3sk1XoOAA3pe4gx0IMv5lTRj3Ecnyk0T0Ux70U23CphFM3SRH?= =?utf-8?q?uUImoRWc7epYskMCqAQO4m4FQzK3Qt9KzTQ/z+Q4GliXJuBh0t9iTMdtWkxWXlDOC?= =?utf-8?q?jeOla96CvZBwrfPcAWB2p7XVoeBYp+DfkicQzZ0N9Yuf/uRyby7jOB1rhYWVMbjpJ?= =?utf-8?q?TGM6xb/r1wq0okK1g5N4kSSApLzMeTCLdUF79tFldAqMxsRypVB3e9xC2Q7e8H0JJ?= =?utf-8?q?o1YbiRyPGhaZpjzp8lCunEPrdTqP931Lw8NGZE6qks8/vCNTtlSCrF/HVe5zwXUXS?= =?utf-8?q?1hlzSTR4lV3DDXC3Hd4S//GwaF6g9WcQCDv5hFt3bLFH8JAh6g5zJCEUQWD9C2RA3?= =?utf-8?q?FRshSy/zgvGDQricG5Wmdlo8f8ujHS8L/qnp4OZaz0n6PoKIMYSi1pGBGuEzx/ADN?= =?utf-8?q?0Kfj52pKKtVOruKJt9ZIdTr4S/TaK4hms3XGv5cTBXKowp0czgkW6Bl1wMq0VeT1Z?= =?utf-8?q?MXPeJtvIfTLJky7lxV/YR2uM0b/tzysOzyg2SseVwtNAGihBfduyCfLt/9q6y6BMt?= =?utf-8?q?21lkHdMoL8gz7W71tmEahgjA29gv4cPAFZBP9Tej0p6KmV5aEbGy2fvVhoFodXOlu?= =?utf-8?q?DfGPszsViGHq0YSbINuHYJAQmfCF+kx+7yNjAnjdwRBfKfAf8zw+4WQeXsnEGiPjK?= =?utf-8?q?TUglWsE4FscY2N2S30zOEgLO/BnNqZY93eFS4RyIpJXV+0VAj2fCR3KVEzDacGbIX?= =?utf-8?q?tTT/y+7ozURv69SbNQw5M88fSgRrsGFCvaxnE+lSVwCHw4n4PxvptaobQU4ajholI?= =?utf-8?q?7B8j3Vd39sqZU3wGZDx070Czw1cMEzQxIuXu4wFBJlC16mBlEzfnMtY6iwu27qYoV?= =?utf-8?q?fHY4b9Zhu5BdGg7y5N4kncRlAMjPk/GpxaNewOrYjCYl+s/VcRsJdrGdyorwgp/en?= =?utf-8?q?Ps40PAG+yrsVH8+Fyz4EWLNlFXPNYS+ZkOH+uQCED1lwVUluEwLF8W7S6wECTmwm0?= =?utf-8?q?azYPsZWECbjA3WqkpkJlqClDNz0GLFQ6kO/O3Yc+iGSM86/6Y8M4VF5YJRuyVPT5q?= =?utf-8?q?MxMchryvrtOqmy9LxIOKLlJkO9Z8HyEXYZsjKBuuBl5jmQR/3Sg5jrKsb/xCL0YbB?= =?utf-8?q?AdWIat6DQ44LfMgsnCP0emUTYoA0BslTQ3YaDTFpKZ2ZfjJSv9kRWxBD8aIbu1iex?= =?utf-8?q?hNQlCWE3PFbXrbcGW3RpJRYzQuoYvJdMD8kEvb5iTgTyAH/TxeDiUHgbqiE/8gptg?= =?utf-8?q?O6G1aBDQHxXD?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0997430e-39f8-41f3-f562-08dcb00bc9fe X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 20:19:46.0696 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XWmMQG3yh4r/XtOrOvrLZdsdOe6hFUKnwl3beQoUjpTao+jf+gC1VWjGryUjPGcV5Rdw3yHD6ixc8pWS+D9kQg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7382 From: Richard Zhu Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe RC support. While the controller resembles that of iMX8MP, the PHY differs significantly. Notably, there's a distinction between PCI bus addresses and CPU addresses. Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus address conversion according to "ranges" property. Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 91aab0288fdcb..4928cea05f6fe 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -65,6 +65,7 @@ enum imx_pcie_variants { IMX8MQ, IMX8MM, IMX8MP, + IMX8Q, IMX95, IMX8MQ_EP, IMX8MM_EP, @@ -80,6 +81,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) #define imx_check_flag(pci, val) (pci->drvdata->flags & val) @@ -1011,6 +1013,22 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) regulator_disable(imx_pcie->vpcie); } +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) +{ + struct imx_pcie *imx_pcie = to_imx_pcie(pcie); + struct dw_pcie_rp *pp = &pcie->pp; + struct resource_entry *entry; + unsigned int offset; + + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) + return cpu_addr; + + entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); + offset = entry->offset; + + return (cpu_addr - offset); +} + static const struct dw_pcie_host_ops imx_pcie_host_ops = { .init = imx_pcie_host_init, .deinit = imx_pcie_host_exit, @@ -1019,6 +1037,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = { static const struct dw_pcie_ops dw_pcie_ops = { .start_link = imx_pcie_start_link, .stop_link = imx_pcie_stop_link, + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup, }; static void imx_pcie_ep_init(struct dw_pcie_ep *ep) @@ -1461,6 +1480,7 @@ static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"}; static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; +static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"}; static const struct imx_pcie_drvdata drvdata[] = { [IMX6Q] = { @@ -1564,6 +1584,13 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .enable_ref_clk = imx8mm_pcie_enable_ref_clk, }, + [IMX8Q] = { + .variant = IMX8Q, + .flags = IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_CPU_ADDR_FIXUP, + .clk_names = imx8q_clks, + .clks_cnt = ARRAY_SIZE(imx8q_clks), + }, [IMX95] = { .variant = IMX95, .flags = IMX_PCIE_FLAG_HAS_SERDES, @@ -1641,6 +1668,7 @@ static const struct of_device_id imx_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, + { .compatible = "fsl,imx8q-pcie", .data = &drvdata[IMX8Q], }, { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], }, { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },