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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , Linus Walleij , "Russell King (Oracle)" , linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/9] net: dsa: vsc73xx: fix phylink capabilities Date: Mon, 29 Jul 2024 23:06:07 +0200 Message-Id: <20240729210615.279952-2-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729210615.279952-1-paweldembicki@gmail.com> References: <20240729210615.279952-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org According datasheet, VSC73XX family switches supports symmetric and asymmetric pause and 1000BASE in FD only. This patch fix it. Fixes: a026809c261b ("net: dsa: vsc73xx: add phylink capabilities") Signed-off-by: Pawel Dembicki --- drivers/net/dsa/vitesse-vsc73xx-core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index 07b704a1557e..43aeb578d608 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -1491,7 +1491,8 @@ static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port, __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); } - config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; + config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000FD; } static int From patchwork Mon Jul 29 21:06:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Dembicki?= X-Patchwork-Id: 13745806 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45D1518D4B9; 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Mon, 29 Jul 2024 14:06:26 -0700 (PDT) Received: from WBEC325.dom.lan ([185.188.71.122]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52fd5c2becesm1624210e87.258.2024.07.29.14.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jul 2024 14:06:26 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , "Russell King (Oracle)" , Linus Walleij , linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/9] net: dsa: vsc73xx: fix port MAC configuration in full duplex mode Date: Mon, 29 Jul 2024 23:06:08 +0200 Message-Id: <20240729210615.279952-3-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729210615.279952-1-paweldembicki@gmail.com> References: <20240729210615.279952-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org According to the datasheet description ("Port Mode Procedure" in 5.6.2), the VSC73XX_MAC_CFG_WEXC_DIS bit is configured only for half duplex mode. The WEXC_DIS bit is responsible for MAC behavior after an excessive collision. Let's set it as described in the datasheet. Signed-off-by: Pawel Dembicki --- drivers/net/dsa/vitesse-vsc73xx-core.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index 43aeb578d608..9bd186af8941 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -1019,6 +1019,11 @@ static void vsc73xx_mac_link_up(struct phylink_config *config, if (duplex == DUPLEX_FULL) val |= VSC73XX_MAC_CFG_FDX; + else + /* In datasheet description ("Port Mode Procedure" in 5.6.2) + * this bit is configured only for half duplex. + */ + val |= VSC73XX_MAC_CFG_WEXC_DIS; /* This routine is described in the datasheet (below ARBDISC register * description) @@ -1029,7 +1034,6 @@ static void vsc73xx_mac_link_up(struct phylink_config *config, get_random_bytes(&seed, 1); val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; val |= VSC73XX_MAC_CFG_SEED_LOAD; - val |= VSC73XX_MAC_CFG_WEXC_DIS; /* Those bits are responsible for MTU only. Kernel takes care about MTU, * let's enable +8 bytes frame length unconditionally. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , Linus Walleij , "Russell King (Oracle)" , linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/9] net: dsa: vsc73xx: pass value in phy_write operation Date: Mon, 29 Jul 2024 23:06:09 +0200 Message-Id: <20240729210615.279952-4-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729210615.279952-1-paweldembicki@gmail.com> References: <20240729210615.279952-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org In the 'vsc73xx_phy_write' function, the register value is missing, and the phy write operation always sends zeros. This commit passes the value variable into the proper register. Fixes: 975ae7c69d51 ("net: phy: vitesse: Add support for VSC73xx") Signed-off-by: Pawel Dembicki --- drivers/net/dsa/vitesse-vsc73xx-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index 9bd186af8941..e5466396669d 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -574,7 +574,7 @@ static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, return 0; } - cmd = (phy << 21) | (regnum << 16); + cmd = (phy << 21) | (regnum << 16) | val; ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); if (ret) return ret; From patchwork Mon Jul 29 21:06:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Dembicki?= X-Patchwork-Id: 13745808 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 663B118EFC2; Mon, 29 Jul 2024 21:06:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722287194; cv=none; b=mEeWYQNUMp0+z1lCpcV5x3uYoAlcxmiYluK+76JlX1vd16G/n9usch3lviznHv3EfNsSQeSTGPIv1UHhpz6UkjYXjmhccdcudKtXaF7bIn/eS1I8A6zKwOgD3V4p4YRwoh+rbeK4hF2pIh9RcPM/pIY+MoboBZdAu9XJSwQJOcU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722287194; c=relaxed/simple; bh=QuPKaf941lHkWf9prBu9zUyAhNquWVs+vlrb39sN+AY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jm89zvhtJbWVlMBdtNlDW0y+CfmUzGquqUUKm8S4ZQZ02nd9RKeNrFGwD/00xER6NOU/G/oeW68R56VzFJwh7PwfoX0+U4hy9p+jcRka3PRlaQo468PxGEE9Z/s+54fytbVWzcrkKMm+STouuZb9jxz3ZJfNpVI7ngp62HKbtbE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=nsMqLKlI; arc=none smtp.client-ip=209.85.208.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nsMqLKlI" Received: by mail-lj1-f181.google.com with SMTP id 38308e7fff4ca-2ef25511ba9so31800941fa.0; Mon, 29 Jul 2024 14:06:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722287190; x=1722891990; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gxl8FNTDoLnQTbWd6UAaRZ2yNtfTa4I0FfsdYDSD1cY=; b=nsMqLKlIoxyKjsdVNuo9UsLdPsneZF+qbJTG3fXs9Hhu5wD6w+WsNCqEhKx8Ai75kR nbl8VXdOl8/7XXnaNlMS7Bn+cCCqK/i2nAFXpfZLMMjVTIoPjYBO/5PARCFD9GiJjFwn C3h2D4n/FRvFh5Wkr5LmKZrb0zv7/xo9hpuB1HLFBsC4lrEnM6MJjXYMDwozh6E/rwaB ypB1qrPRyspxj+I+AKw3nHKJYx9xGIa21ALYROr8sBiKuECVkcsJ28k9LQe3pmLe7lC/ VbQ261JHGRJru+RSagvnnjvDY6HozZtR/jvQoZiuHIOyAtd4HtWmAwKONtXN8KFK8hUd 0UOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722287190; x=1722891990; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gxl8FNTDoLnQTbWd6UAaRZ2yNtfTa4I0FfsdYDSD1cY=; b=jEMVaRpuyks3LMoD2iBiOR0dyxyTVLSehZqrjPrpYD8rWkFpPUWFP06B4WqP10zQwO lFu1USRnb2RRfZzxtE+nJWI6S0fxHTTT+RFZfR66Yxlq2O4d5v/cUWZzIM3iZIFYB8Rl ubW2xx8yGRspcUp9eN1HIFlKvIbxxWr/P9F6bRJ/LAsvZjAlGEezJlJQAyVHoROo6ETz mgdAsgbj286kuvkyKcen3iMac599EkhqgphYH71avoLAPZBvNcZ/25JAFSWKiN6HFmeU ku68V2i5mVZidzj0whapDuz4UJ+z09pju6waWq9/pb4iz0V1SRDMcaPT4HQXM0vBtGgl EHvA== X-Forwarded-Encrypted: i=1; AJvYcCW/feMrUCtP8VAW8kSZByJiTAUsKG4hVV3JCrYg+jQY4eTORR0YsJquqMkt4F9P3+/pkbbpAxsr27wOy2/O97sJ9EMb1GZtkHgL0xHd X-Gm-Message-State: AOJu0YzwkymHubYcSgIqG2GF/v3/y5mBxmQfRa67WZQPYaLBBkwSk3aL hej+vpW6WWRLQNB0uyifxd+J5TbBL9Z1qwlCVSrZaG9ZvdZ8wtLek8bnAXIz X-Google-Smtp-Source: AGHT+IFFnxIKiVkCBtjvRBXBqJ+HQAJ+R5fG0pkmUdMchZUdhRzTJr4tqE6d/YHLbDBgq4hKMlA1uw== X-Received: by 2002:a05:6512:1308:b0:52f:cc9e:449d with SMTP id 2adb3069b0e04-5309b6d3473mr2583452e87.3.1722287190278; Mon, 29 Jul 2024 14:06:30 -0700 (PDT) Received: from WBEC325.dom.lan ([185.188.71.122]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52fd5c2becesm1624210e87.258.2024.07.29.14.06.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jul 2024 14:06:29 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , Linus Walleij , "Russell King (Oracle)" , linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/9] net: dsa: vsc73xx: use defined values in phy operations Date: Mon, 29 Jul 2024 23:06:10 +0200 Message-Id: <20240729210615.279952-5-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729210615.279952-1-paweldembicki@gmail.com> References: <20240729210615.279952-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This commit changes magic numbers in phy operations. Some shifted registers was replaced with bitfield macros. No functional changes done. Signed-off-by: Pawel Dembicki --- drivers/net/dsa/vitesse-vsc73xx-core.c | 45 ++++++++++++++++++++------ 1 file changed, 35 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index e5466396669d..5eb37dee2261 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,10 @@ #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */ #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ +/* MII Block subblock */ +#define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */ +#define VSC73XX_BLOCK_MII_EXTERNAL 0x1 /* External MDIO subblock */ + #define CPU_PORT 6 /* CPU port */ /* MAC Block registers */ @@ -221,9 +226,22 @@ #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3 /* MII block 3 registers */ -#define VSC73XX_MII_STAT 0x0 -#define VSC73XX_MII_CMD 0x1 -#define VSC73XX_MII_DATA 0x2 +#define VSC73XX_MII_STAT 0x0 +#define VSC73XX_MII_CMD 0x1 +#define VSC73XX_MII_DATA 0x2 + +#define VSC73XX_MII_STAT_BUSY BIT(3) +#define VSC73XX_MII_STAT_READ BIT(2) +#define VSC73XX_MII_STAT_WRITE BIT(1) + +#define VSC73XX_MII_CMD_SCAN BIT(27) +#define VSC73XX_MII_CMD_OPERATION BIT(26) +#define VSC73XX_MII_CMD_PHY_ADDR GENMASK(25, 21) +#define VSC73XX_MII_CMD_PHY_REG GENMASK(20, 16) +#define VSC73XX_MII_CMD_WRITE_DATA GENMASK(15, 0) + +#define VSC73XX_MII_DATA_FAILURE BIT(16) +#define VSC73XX_MII_DATA_READ_DATA GENMASK(15, 0) /* Arbiter block 5 registers */ #define VSC73XX_ARBEMPTY 0x0c @@ -535,20 +553,24 @@ static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) int ret; /* Setting bit 26 means "read" */ - cmd = BIT(26) | (phy << 21) | (regnum << 16); - ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); + cmd = VSC73XX_MII_CMD_OPERATION | + FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) | + FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum); + ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, + VSC73XX_MII_CMD, cmd); if (ret) return ret; msleep(2); - ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); + ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, + VSC73XX_MII_DATA, &val); if (ret) return ret; - if (val & BIT(16)) { + if (val & VSC73XX_MII_DATA_FAILURE) { dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", regnum, phy); return -EIO; } - val &= 0xFFFFU; + val &= VSC73XX_MII_DATA_READ_DATA; dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", regnum, phy, val); @@ -574,8 +596,11 @@ static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, return 0; } - cmd = (phy << 21) | (regnum << 16) | val; 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Mon, 29 Jul 2024 14:06:31 -0700 (PDT) Received: from WBEC325.dom.lan ([185.188.71.122]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52fd5c2becesm1624210e87.258.2024.07.29.14.06.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jul 2024 14:06:31 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , "Russell King (Oracle)" , Linus Walleij , linux-kernel@vger.kernel.org Subject: [PATCH net-next 5/9] net: dsa: vsc73xx: use mutex to mdio operations Date: Mon, 29 Jul 2024 23:06:11 +0200 Message-Id: <20240729210615.279952-6-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729210615.279952-1-paweldembicki@gmail.com> References: <20240729210615.279952-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org vsc73xx needs mutex during mdio bus access to avoid races. Without it, phys are misconfigured and bus operations aren't work as expected. Signed-off-by: Pawel Dembicki --- drivers/net/dsa/vitesse-vsc73xx-core.c | 59 ++++++++++++++++++++------ drivers/net/dsa/vitesse-vsc73xx.h | 2 + 2 files changed, 47 insertions(+), 14 deletions(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index 5eb37dee2261..40c64ef7e729 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -545,6 +545,18 @@ static int vsc73xx_detect(struct vsc73xx *vsc) return 0; } +static int vsc73xx_mdio_busy_check(struct vsc73xx *vsc) +{ + int val, ret; + + ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, + VSC73XX_MII_STAT, &val); + if (ret) + return ret; + + return (val & VSC73XX_MII_STAT_BUSY) ? -EBUSY : 0; +} + static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) { struct vsc73xx *vsc = ds->priv; @@ -552,6 +564,12 @@ static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) u32 val; int ret; + mutex_lock(&vsc->mdio_lock); + + ret = vsc73xx_mdio_busy_check(vsc); + if (ret) + goto err; + /* Setting bit 26 means "read" */ cmd = VSC73XX_MII_CMD_OPERATION | FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) | @@ -559,23 +577,27 @@ static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, VSC73XX_MII_CMD, cmd); if (ret) - return ret; - msleep(2); + goto err; + usleep_range(100, 200); ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, VSC73XX_MII_DATA, &val); if (ret) - return ret; + goto err; + if (val & VSC73XX_MII_DATA_FAILURE) { dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", regnum, phy); - return -EIO; + ret = -EIO; + goto err; } - val &= VSC73XX_MII_DATA_READ_DATA; + ret = val & VSC73XX_MII_DATA_READ_DATA; dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", - regnum, phy, val); + regnum, phy, ret); - return val; +err: + mutex_unlock(&vsc->mdio_lock); + return ret; } static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, @@ -583,7 +605,13 @@ static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, { struct vsc73xx *vsc = ds->priv; u32 cmd; - int ret; + int ret = 0; + + mutex_lock(&vsc->mdio_lock); + + ret = vsc73xx_mdio_busy_check(vsc); + if (ret) + goto err; /* It was found through tedious experiments that this router * chip really hates to have it's PHYs reset. They @@ -601,12 +629,13 @@ static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, FIELD_PREP(VSC73XX_MII_CMD_WRITE_DATA, val); ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, VSC73XX_MII_CMD, cmd); - if (ret) - return ret; - - dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", - val, regnum, phy); - return 0; + if (!ret) + dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", + val, regnum, phy); + usleep_range(100, 200); +err: + mutex_unlock(&vsc->mdio_lock); + return ret; } static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds, @@ -1973,6 +2002,8 @@ int vsc73xx_probe(struct vsc73xx *vsc) return -ENODEV; } + mutex_init(&vsc->mdio_lock); + eth_random_addr(vsc->addr); dev_info(vsc->dev, "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n", diff --git a/drivers/net/dsa/vitesse-vsc73xx.h b/drivers/net/dsa/vitesse-vsc73xx.h index 3ca579acc798..fc0fa8f5f57c 100644 --- a/drivers/net/dsa/vitesse-vsc73xx.h +++ b/drivers/net/dsa/vitesse-vsc73xx.h @@ -45,6 +45,7 @@ struct vsc73xx_portinfo { * @vlans: List of configured vlans. Contains port mask and untagged status of * every vlan configured in port vlan operation. It doesn't cover tag_8021q * vlans. + * @mdio_lock: Mutex used in mdio operations */ struct vsc73xx { struct device *dev; @@ -57,6 +58,7 @@ struct vsc73xx { void *priv; struct vsc73xx_portinfo portinfo[VSC73XX_MAX_NUM_PORTS]; struct list_head vlans; + struct mutex mdio_lock; }; /** From patchwork Mon Jul 29 21:06:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Dembicki?= X-Patchwork-Id: 13745810 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0B6C18F2F0; Mon, 29 Jul 2024 21:06:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722287197; cv=none; b=WkMr6o10122G6e25y+bzM7dZwuL+DZz4bo4LByOiyKLa1rxuq1rDq1iEAqryFTdT9KYdAfEbqahr03+5uN++cF0FLFI+DcDUDcg8mPpCCkbzwvKQqBNh/OLVYDOuUZR0U06MmARTFMA0cY7fkOZaoCVp+163Wy3fJEo3olHnAUI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722287197; c=relaxed/simple; bh=kD5S6LiCcTTGq4F4VT9DVxlZ8kQ+DCninIHU//YP9LU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kAk7ycko37wxizbbi0o81Wjcylp7OoXTu1zuSIg7Fe6+Zk51afP/ud2tSXsRU03gv7ER2QjcJ3nD3EXehGZvBo8xPsbfRRUIdN4Xj1Ln7HzJl6B417EOgiBI7AlwcjptckG0xrL6DfZkCIWtj3O6fUF0PVMa97dkFONN4EI6hk4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FqF2mMIV; arc=none smtp.client-ip=209.85.167.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FqF2mMIV" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-52efabf5d7bso4596154e87.1; Mon, 29 Jul 2024 14:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722287194; x=1722891994; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vmesrltev2WsoY00lWaXAlkGtiK5mvpuNF3kNqMCxx4=; b=FqF2mMIV0+FwY9o3fP2ZLPd31zzroIOTADay1xpYOupv0I+Hwk+oQjRd/hZHfvsgc/ PCQ+wNL85kZPStVWMVXXJf56QB0SV4fjw6LUEmOV5Uz8JfnVzBqvWw0HBeexdkVQvj0o kva1SdcmQQH28tR/rctoezDs3mZsFf8SfUMioiaD7CfjR04hUpg54NeB22OeR6Ka8Uu8 BtvGajhswXQEvIczACpZLsCAt5kDbnyNCwrQ1S+P8bNsVoCzFuBbYOXREaCWJ2iRwLh8 kAiWFAv1S2wTjU+gtIuzejL2J4f8wCAmGM7bEGhozR159pcnj+9yf38Fe06IAKV4ko62 iWqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722287194; x=1722891994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vmesrltev2WsoY00lWaXAlkGtiK5mvpuNF3kNqMCxx4=; b=Vmcw/tLqxp0kxS2okIWxuOslFcMz4EIaCVurhjdkdD/1AvdNNzQTVWunUunE9+0lEs zttHiuxPhjrrd8dWWphBSttAdJOgvTknvG7+erDgxH0FygXkV7FrjicZNl6J4hboK5kZ dSng2RCZn45fmofpBoXvHsAt0G2mFFsKZkHKGsrrVHdIg82dO5fES6FhNTRHBCj1H+SX 5F20N25FvNDxFp73a3a50Xc8AQ2zW3IT8STKYO2zhT1pCMSCRrwttKKBHn9orAehlwVG tb0uYe8sRCHOs20moEKknnEeMnrWf9to1Iut77bHKgcs6WzF8hHav6QJgDAmrMgaopkz 6XQg== X-Forwarded-Encrypted: i=1; AJvYcCVEH6ONRIHVXFF1eE3WykcB4MXiz5Z9ND/m5Ok17R8J4zjjH88u4uOHm0pU+3hCOaOOXamDAsJMXO+Xi/MHcFbgja4i5TuagDcqNKQp X-Gm-Message-State: AOJu0YzQ2oPu37wh94MILMjdJkK/cXiLaVU1F3WFYev0FMHrS2a0cfdn epf+dNDaEeYg4QuQfIb6e2KAq4l2v8Tky/j3+5q94+gQ12uzFZmgqsGr/jsO X-Google-Smtp-Source: AGHT+IGxa6YkKA4a4LQpnLOy906gdPbzxWSPbVRHKCdxP/eZy4Y/a/zmcs26+zvZi67kH4GPYfUBXQ== X-Received: by 2002:ac2:4bca:0:b0:52e:9fe0:bee4 with SMTP id 2adb3069b0e04-5309b25a273mr5980306e87.9.1722287193607; Mon, 29 Jul 2024 14:06:33 -0700 (PDT) Received: from WBEC325.dom.lan ([185.188.71.122]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52fd5c2becesm1624210e87.258.2024.07.29.14.06.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jul 2024 14:06:33 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , Linus Walleij , "Russell King (Oracle)" , linux-kernel@vger.kernel.org Subject: [PATCH net-next 6/9] net: dsa: vsc73xx: speed up mdio bus to max allowed value Date: Mon, 29 Jul 2024 23:06:12 +0200 Message-Id: <20240729210615.279952-7-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729210615.279952-1-paweldembicki@gmail.com> References: <20240729210615.279952-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org According the datasheet, vsc73xx family max internal mdio bus speed is 20MHz. It also allow to disable preamble. This commit sets mdio clock prescaler to minimal value and crop preamble to speed up mdio operations. Signed-off-by: Pawel Dembicki Reviewed-by: Andrew Lunn --- drivers/net/dsa/vitesse-vsc73xx-core.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index 40c64ef7e729..9e88eda6f4dd 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -229,6 +229,7 @@ #define VSC73XX_MII_STAT 0x0 #define VSC73XX_MII_CMD 0x1 #define VSC73XX_MII_DATA 0x2 +#define VSC73XX_MII_MPRES 0x3 #define VSC73XX_MII_STAT_BUSY BIT(3) #define VSC73XX_MII_STAT_READ BIT(2) @@ -243,6 +244,10 @@ #define VSC73XX_MII_DATA_FAILURE BIT(16) #define VSC73XX_MII_DATA_READ_DATA GENMASK(15, 0) +#define VSC73XX_MII_MPRES_NOPREAMBLE BIT(6) +#define VSC73XX_MII_MPRES_PRESCALEVAL GENMASK(5, 0) +#define VSC73XX_MII_PRESCALEVAL_MIN 3 /* min allowed mdio clock prescaler */ + /* Arbiter block 5 registers */ #define VSC73XX_ARBEMPTY 0x0c #define VSC73XX_ARBDISC 0x0e @@ -578,7 +583,7 @@ static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) VSC73XX_MII_CMD, cmd); if (ret) goto err; - usleep_range(100, 200); + usleep_range(4, 100); ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, VSC73XX_MII_DATA, &val); if (ret) @@ -632,7 +637,7 @@ static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, if (!ret) dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", val, regnum, phy); - usleep_range(100, 200); + usleep_range(4, 100); err: mutex_unlock(&vsc->mdio_lock); return ret; @@ -802,7 +807,7 @@ static int vsc73xx_configure_rgmii_port_delay(struct dsa_switch *ds) static int vsc73xx_setup(struct dsa_switch *ds) { struct vsc73xx *vsc = ds->priv; - int i, ret; + int i, ret, val; dev_info(vsc->dev, "set up the switch\n"); @@ -875,6 +880,15 @@ static int vsc73xx_setup(struct dsa_switch *ds) mdelay(50); + /* Disable preamble and use maximum allowed clock for the internal + * mdio bus, used for communication with internal PHYs only. + */ + val = VSC73XX_MII_MPRES_NOPREAMBLE | + FIELD_PREP(VSC73XX_MII_MPRES_PRESCALEVAL, + VSC73XX_MII_PRESCALEVAL_MIN); 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Mon, 29 Jul 2024 14:06:34 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , "Russell King (Oracle)" , Linus Walleij , linux-kernel@vger.kernel.org Subject: [PATCH net-next 7/9] net: dsa: vsc73xx: allow phy resetting Date: Mon, 29 Jul 2024 23:06:13 +0200 Message-Id: <20240729210615.279952-8-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729210615.279952-1-paweldembicki@gmail.com> References: <20240729210615.279952-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Now, phy reset isn't a problem for vsc73xx switches. 'soft_reset' can be done normally. This commit removes the reset blockade in the 'vsc73xx_phy_write' function. Signed-off-by: Pawel Dembicki --- drivers/net/dsa/vitesse-vsc73xx-core.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index 9e88eda6f4dd..df36118644f2 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -618,17 +618,6 @@ static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, if (ret) goto err; - /* It was found through tedious experiments that this router - * chip really hates to have it's PHYs reset. They - * never recover if that happens: autonegotiation stops - * working after a reset. Just filter out this command. - * (Resetting the whole chip is OK.) - */ - if (regnum == 0 && (val & BIT(15))) { - dev_info(vsc->dev, "reset PHY - disallowed\n"); - return 0; - } - cmd = FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) | FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum) | FIELD_PREP(VSC73XX_MII_CMD_WRITE_DATA, val); From patchwork Mon Jul 29 21:06:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Dembicki?= X-Patchwork-Id: 13745812 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2680918D4B0; Mon, 29 Jul 2024 21:06:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722287201; cv=none; b=ofldWotuLrFn4G6kT74/AmXFT7witUyu1kZaTyYiUK47ua+4IjUirzbfwkYFuZjzazU3pzPBygbspD3dzRxNfYbe2uJdG6UDS+R+rVXUucjjIWhqi/lbuIwjAajoOU+ShL8v/DMy3UGVvgkLxucBV6JVpRr/o6+ZWAjcYHYwaSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722287201; c=relaxed/simple; bh=F5NZxDnweHdu6at7fyQq2LLAHVE4BsU9fZw3/kQA2KA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GRge061iMHGdiow8EXizPZ3YT+yQ5yJ9UY3/a85hfhWwzyU2Imv7CIUcMqWN77XnS2BS3AJnNtnpzn9YC03yMXDmMgJyiICa7JCy/L1VmMLVTh/vMslzh1/skgQg8yIiHHOJTefR5GtLkt8F0cbK76ovG2bsBSqpHEtXlzrebDs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lTSoyyoB; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lTSoyyoB" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-52ef95ec938so4720769e87.3; Mon, 29 Jul 2024 14:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722287197; x=1722891997; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GUH0bFr3P3XDMrBpdmW5Yx5nikStsLn0wPrng5g2mmI=; b=lTSoyyoB0c+h+734y+WPcdwlheGC7nU10NfWskXBlw224KSeV2rS8cOrs3QtudjiVh hnOA9dB/meA92ibAttvSmikRDIcCDLjf8OVvWOYJnILTnOwUEz//VQXH6tSyJRuuh6J+ Rj4gfi8lyqdD9lN/FYxXxd9WkXBEFXJ1A1zIeGRAg30pKD83AKFkLH0rI4ZspHC5f+8z T7i4PN3K1IPrc76JqeRCsU+I9RnFHWb3I2L3e7zkDM4+VDc7iLgo+TFvfN+ZdL2guwbC lVFpf0vOaQSqGLd/CYolv1ED+a9r4UjO9bQ0ip9LFPxe5JNA7C/GobIIdLFhnZYGll80 ItQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722287197; x=1722891997; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GUH0bFr3P3XDMrBpdmW5Yx5nikStsLn0wPrng5g2mmI=; b=i/DnuyBHTkKelreLprKvCvOoAdO6fw1jbOxp3eVMpY61U72+na75pq+bweFgRDYK14 ddcTpGkwYLX8fdMXpx3uDGQzrSb61wltjVR3SC2qU7Y9X69ICHf5RadNWD4XX/azf3eF iegiSEQyy5eMVsTKqkXUa6Y23UKuf1ic17O1zwuUjozDahIJ9ZRz8laev5EvyN+l3j68 QOjlgJ+QtCJTIypeo976uqy7Eju9ip+6O91/RYI80Q57iMiGjKMOm1SnsLrsmaa94h3E 8Z8AG6Rn1BwScJp2ey4L8yMrQg2PChxL19sEb8SMSrz2Jpa3qd2O9l0a3sMHBdfC4LxR XOcQ== X-Forwarded-Encrypted: i=1; AJvYcCUkxgJV8eU8KqhaEmPUp1tPTpn6/rrjzq8TbJ+QKWBJGy2ULQ/afUNeOkCFHYAGVBrlNgrmsNEIkDmsBx+RpeNHRqfF7vETpXnh3Q9D X-Gm-Message-State: AOJu0Yy9rTp/VQJfW9BqNr9nDQD9NYTtPnWuu75GkM1EBHIbgHmm/LsW dIcvI2Vd76WZgnGpaulwTtwKi4ttHgg0Uzz88INnUxFXy6b8WaWteBlaIO0Q X-Google-Smtp-Source: AGHT+IFxxpsoquWZA4AZabFN6Fh0mTPqwOp2t+ejCtqRU10M0v7Pf85E9gZR9bYJr0VYk06p+T7OOw== X-Received: by 2002:ac2:4d89:0:b0:52c:8a37:6cf4 with SMTP id 2adb3069b0e04-5309b26b4a4mr5166755e87.14.1722287196847; Mon, 29 Jul 2024 14:06:36 -0700 (PDT) Received: from WBEC325.dom.lan ([185.188.71.122]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52fd5c2becesm1624210e87.258.2024.07.29.14.06.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jul 2024 14:06:36 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , Linus Walleij , "Russell King (Oracle)" , linux-kernel@vger.kernel.org Subject: [PATCH net-next 8/9] net: phy: vitesse: repair vsc73xx autonegotiation Date: Mon, 29 Jul 2024 23:06:14 +0200 Message-Id: <20240729210615.279952-9-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729210615.279952-1-paweldembicki@gmail.com> References: <20240729210615.279952-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org When the vsc73xx mdio bus work properly, the generic autonegotiation configuration works well. Vsc73xx have auto MDI-X disabled by default in forced mode. This commit enables it. Signed-off-by: Pawel Dembicki --- drivers/net/phy/vitesse.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 897b979ec03c..19b7bf189be5 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -60,6 +60,11 @@ /* Vitesse Extended Page Access Register */ #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f +/* VSC73XX PHY_BYPASS_CTRL register*/ +#define MII_VSC73XX_PHY_BYPASS_CTRL MII_DCOUNTER +#define MII_PBC_FORCED_SPEED_AUTO_MDIX_DIS BIT(7) +#define MII_VSC73XX_PBC_AUTO_NP_EXCHANGE_DIS BIT(1) + /* Vitesse VSC8601 Extended PHY Control Register 1 */ #define MII_VSC8601_EPHY_CTL 0x17 #define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8) @@ -239,12 +244,20 @@ static int vsc739x_config_init(struct phy_device *phydev) static int vsc73xx_config_aneg(struct phy_device *phydev) { - /* The VSC73xx switches does not like to be instructed to - * do autonegotiation in any way, it prefers that you just go - * with the power-on/reset defaults. Writing some registers will - * just make autonegotiation permanently fail. - */ - return 0; + int ret; + + /* Enable Auto MDI-X in forced 10/100 mode */ + if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) { + ret = genphy_setup_forced(phydev); + + if (ret < 0) /* error */ + return ret; + + return phy_clear_bits(phydev, MII_VSC73XX_PHY_BYPASS_CTRL, + MII_PBC_FORCED_SPEED_AUTO_MDIX_DIS); + } + + return genphy_config_aneg(phydev); } /* This adds a skew for both TX and RX clocks, so the skew should only be From patchwork Mon Jul 29 21:06:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Dembicki?= X-Patchwork-Id: 13745813 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A942818FDD1; Mon, 29 Jul 2024 21:06:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722287202; cv=none; b=cmTVWlkrIhLYP9qgt+2gOUwK1Pguwx68WSfUpy5SFZKfHtHwU/2eUKTXighNT5pBdXpMJKs8PkIOZGVs3zL6UCxQfgVqR1ll7v+2kBvM40PDDdvznJq2HuvyBHw2iy/VBE/k/JxHP8ik26KCPtasVSKiVePkNXmN+O4R5l3MOEU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722287202; c=relaxed/simple; bh=/nll/xQ57QpCe/KFcvY9S3fpHUjf5E1IdqrSu7nCt3Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RxFQvVx2eGpJyvW6WRFgPFroD1HkHPJSjn9fEVjYdTDOksQ2ofzP3HX0L3JLsZ/Heo2q8ZSOC5k4Xe5N5ukGed6f4Bw2gLaj7cj1fkYSrhuoWnXzZI4M1rsnSEa2JfjpJTNveOEiiDtET3KKXzu+lEq3MS45y+VQcdcd3hCrYrU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SHnpxRER; arc=none smtp.client-ip=209.85.167.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SHnpxRER" Received: by mail-lf1-f53.google.com with SMTP id 2adb3069b0e04-52f01ec08d6so5969295e87.2; Mon, 29 Jul 2024 14:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722287198; x=1722891998; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Aood59TYIo0CSyaSVOXxvTHUPNO93s3Ct8cxPWT2YP0=; b=SHnpxRERRJ3D5ooLIPWudwLvwSoMq7V43m/CA0m+EYHbO7MQRw4bF2/QJBc3bW6qd4 3Mz1GWvjgSHFi9u+cr6K/yiJfwWXW77RMtZ6C1xcJEf7ZfSQLV0gjWa1Ckf6baghxtdl q/2I34T5SgV1TJuQTbba4a7jdVheTfk28bmNXLhWLjkF5SKABGbYypqMb5+v9OlNlRsx MFP8nqhWexWlFMY4s43f5dVL0huZzySIqn4EcofD3VJ7QsvUozwkvh5eiQXyQiBFSiQc SXP9XVUKbof1Yr0qv19b3txOfQfESSZ9TarnHS9XcpUvvEF3dCo3o1LHWRy3E9O/nUhj fccQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722287198; x=1722891998; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Aood59TYIo0CSyaSVOXxvTHUPNO93s3Ct8cxPWT2YP0=; b=fI61RQC1Og+kNSZ88iJeIsYm6NH51oAFez/Hc/hsCokAlsWP4dJCWeHtvIPgAGK4Zu J+bnQOlxWPzIwnxRkzafkJoXkrJ3tzuExOUMIINGOQ07zTVqMvIyDxV1n7HWALNahqOb +Tajp4vcNpcbMUdCrtIOmuYGEJYvbGGCsGZcr6jbbEPsEN2SEpKNTkvCbMGWDLDv+rCD fgGTCwTTW81dtBjb3sNoB3s0lcu/IDNNY++ouelHR4k0VXFV5N/uZs09PIjUZoLO7gtU 0PkptHf56O5dkcAvQdmz9ryWE/w8JteguSLl6D9ok/k22cpVa5g5GkHOZaQFfAgAahow bbBw== X-Forwarded-Encrypted: i=1; AJvYcCUhreDcy5CrMBR1SetDGCy4jnzJW+TXx04woGMs/fp2xyz9U4F8tttrhoiROappwx20EeMD4SAuZacmkkI=@vger.kernel.org X-Gm-Message-State: AOJu0YwweIIzNqWiLpMNMvx/D6BOVEFhXzZVfvCJWsB25xDBFlHtTQko okWogQc6hykpNbNuKef+/PgC+f01yWzSl1a9K9uUD4gU4pVnj2xYm/Qgwt/R X-Google-Smtp-Source: AGHT+IF51byaAuVxiOkHYwjvPEN83vlnJXCSOK4Ixxb1xF9g1jgloJnfwk6kja8u9w/eD1+FBTBX7A== X-Received: by 2002:ac2:5692:0:b0:530:aa53:60f6 with SMTP id 2adb3069b0e04-530aa53625cmr58394e87.15.1722287198558; Mon, 29 Jul 2024 14:06:38 -0700 (PDT) Received: from WBEC325.dom.lan ([185.188.71.122]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52fd5c2becesm1624210e87.258.2024.07.29.14.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jul 2024 14:06:38 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , "Russell King (Oracle)" , Linus Walleij , linux-kernel@vger.kernel.org Subject: [PATCH net-next 9/9] net: phy: vitesse: implement downshift in vsc73xx phys Date: Mon, 29 Jul 2024 23:06:15 +0200 Message-Id: <20240729210615.279952-10-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729210615.279952-1-paweldembicki@gmail.com> References: <20240729210615.279952-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This commit implements downshift feature in vsc73xx family phys. By default downshift was enabled with maximum tries. Signed-off-by: Pawel Dembicki --- drivers/net/phy/vitesse.c | 100 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 19b7bf189be5..9228c6652627 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -10,8 +10,10 @@ #include #include #include +#include /* Vitesse Extended Page Magic Register(s) */ +#define MII_VSC73XX_EXT_PAGE_1E 0x01 #define MII_VSC82X4_EXT_PAGE_16E 0x10 #define MII_VSC82X4_EXT_PAGE_17E 0x11 #define MII_VSC82X4_EXT_PAGE_18E 0x12 @@ -60,6 +62,15 @@ /* Vitesse Extended Page Access Register */ #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f +/* Vitesse VSC73XX Extended Control Register */ +#define MII_VSC73XX_PHY_CTRL_EXT3 0x14 + +#define MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_EN BIT(4) +#define MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_CNT GENMASK(3, 2) +#define MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_STA BIT(1) +#define MII_VSC73XX_DOWNSHIFT_MAX 5 +#define MII_VSC73XX_DOWNSHIFT_INVAL 1 + /* VSC73XX PHY_BYPASS_CTRL register*/ #define MII_VSC73XX_PHY_BYPASS_CTRL MII_DCOUNTER #define MII_PBC_FORCED_SPEED_AUTO_MDIX_DIS BIT(7) @@ -133,6 +144,84 @@ static int vsc73xx_write_page(struct phy_device *phydev, int page) return __phy_write(phydev, VSC73XX_EXT_PAGE_ACCESS, page); } +static int vsc73xx_get_downshift(struct phy_device *phydev, u8 *data) +{ + int page, val, cnt, enable; + + page = phy_select_page(phydev, MII_VSC73XX_EXT_PAGE_1E); + if (page < 0) + return page; + + val = __phy_read(phydev, MII_VSC73XX_PHY_CTRL_EXT3); + if (val < 0) + goto restore_page; + + enable = FIELD_GET(MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_EN, val); + cnt = FIELD_GET(MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_CNT, val) + 2; + + *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE; + +restore_page: + phy_restore_page(phydev, page, val); + return 0; +} + +static int vsc73xx_set_downshift(struct phy_device *phydev, u8 cnt) +{ + int page, ret, val; + + if (cnt > MII_VSC73XX_DOWNSHIFT_MAX) + return -E2BIG; + else if (cnt == MII_VSC73XX_DOWNSHIFT_INVAL) + return -EINVAL; + + page = phy_select_page(phydev, MII_VSC73XX_EXT_PAGE_1E); + if (page < 0) + return page; + + if (!cnt) { + ret = __phy_clear_bits(phydev, MII_VSC73XX_PHY_CTRL_EXT3, + MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_EN); + } else { + val = MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_EN | + FIELD_PREP(MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_CNT, + cnt - 2); + + ret = __phy_modify(phydev, MII_VSC73XX_PHY_CTRL_EXT3, + MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_EN | + MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_CNT, + val); + } + + ret = phy_restore_page(phydev, page, ret); + if (ret < 0) + return ret; + + return genphy_soft_reset(phydev); +} + +static int vsc73xx_get_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_DOWNSHIFT: + return vsc73xx_get_downshift(phydev, data); + default: + return -EOPNOTSUPP; + } +} + +static int vsc73xx_set_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, const void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_DOWNSHIFT: + return vsc73xx_set_downshift(phydev, *(const u8 *)data); + default: + return -EOPNOTSUPP; + } +} + static void vsc73xx_config_init(struct phy_device *phydev) { /* Receiver init */ @@ -142,6 +231,9 @@ static void vsc73xx_config_init(struct phy_device *phydev) /* Config LEDs 0x61 */ phy_modify(phydev, MII_TPISTATUS, 0xff00, 0x0061); + + /* Enable downshift by default */ + vsc73xx_set_downshift(phydev, MII_VSC73XX_DOWNSHIFT_MAX); } static int vsc738x_config_init(struct phy_device *phydev) @@ -460,6 +552,8 @@ static struct phy_driver vsc82xx_driver[] = { .config_aneg = vsc73xx_config_aneg, .read_page = vsc73xx_read_page, .write_page = vsc73xx_write_page, + .get_tunable = vsc73xx_get_tunable, + .set_tunable = vsc73xx_set_tunable, }, { .phy_id = PHY_ID_VSC7388, .name = "Vitesse VSC7388", @@ -469,6 +563,8 @@ static struct phy_driver vsc82xx_driver[] = { .config_aneg = vsc73xx_config_aneg, .read_page = vsc73xx_read_page, .write_page = vsc73xx_write_page, + .get_tunable = vsc73xx_get_tunable, + .set_tunable = vsc73xx_set_tunable, }, { .phy_id = PHY_ID_VSC7395, .name = "Vitesse VSC7395", @@ -478,6 +574,8 @@ static struct phy_driver vsc82xx_driver[] = { .config_aneg = vsc73xx_config_aneg, .read_page = vsc73xx_read_page, .write_page = vsc73xx_write_page, + .get_tunable = vsc73xx_get_tunable, + .set_tunable = vsc73xx_set_tunable, }, { .phy_id = PHY_ID_VSC7398, .name = "Vitesse VSC7398", @@ -487,6 +585,8 @@ static struct phy_driver vsc82xx_driver[] = { .config_aneg = vsc73xx_config_aneg, .read_page = vsc73xx_read_page, .write_page = vsc73xx_write_page, + .get_tunable = vsc73xx_get_tunable, + .set_tunable = vsc73xx_set_tunable, }, { .phy_id = PHY_ID_VSC8662, .name = "Vitesse VSC8662",