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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Shay Drory , Moshe Shemesh , Tariq Toukan Subject: [PATCH net 1/8] net/mlx5: Always drain health in shutdown callback Date: Tue, 30 Jul 2024 09:16:30 +0300 Message-ID: <20240730061638.1831002-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730061638.1831002-1-tariqt@nvidia.com> References: <20240730061638.1831002-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000014:EE_|SJ0PR12MB8167:EE_ X-MS-Office365-Filtering-Correlation-Id: e3c34be0-8fec-4604-1f73-08dcb05f6c6a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: rsPTmerTb1NCIefHaVKYn8MpXcVa/imjx9t1nZsFPxOlXr84/3vJC7WJQtQzlgzvhozuW2YPeB1ugBteVFIObb1k1xZkwIpJ2A9KgIXQDucPN2HMDMYwVKRyrzxWpRUHOcHSXWCbf2NueyIBuQJiF/xy4EY5QQMbgpttCxW4Xn/laaqDoojhhvpmVVfnChJCJV4J5Rw+C2dLGH/phYM8fq+G8iDIEuud17+kS3tAVr9G8gifhHb/Qbs08zjhUu4R2pozUmRyxRvGjh7c7Kli+JLoBnBBOTW3zz8Dz+uLOuSo26WISeCmxOXG26G1rlTvHZnRtW86p+9GoLcdAWn2TU3Wg7ubaNBd8ag0I3Qj5h9ZyyIqsJDuqKdA/B5nHm6wja8VKxTRDMw9MuavPD+xL+JXv7mTFQQ9bmvgJA9gnO8MAp/zqTWYByCdku/nXLKo17OMdEOEG/BTGOMoQVjmDJynNVcmzcMgToN7bjuhQshePVU3xYG8qk89Eu38TsZAxctJKcjqK+GdbQXX5YlJ88YpHET471/xVayKyj2bWFjYeCCZXbAEqmh/BVh1WttUmmk/984EVphcvJKPtIAAp5a6XzhKtEJpc0//zIrLU2mljxOrscn9cLUWRwkG2z8ROSF3EwamjbHOV2uqptwHvB/vJrQX5VVo0bZGgZl4629MVJaJ84SLQ8qQg6S8f0vHlFIREQiXLilZjs0N/ZiSDO0/itXpR4LojCU+5eH89ATvcSsVkZD/IgRjkf934bkmoAN8PION/LXghBgWXBHi4JTqzMa0/L3je7Y112EJb8Tuc1oWAWyy3W+L12LzI2jzveSi6gL845ujWVs8FPFvdwgjhlFfyisxxn7jcLjdwkkRtfRp0jUZtlgiGbfu9Y+KGPxaKBAj1e1Bmaf1xdfh+KDuXAcO5DDJi3U5R2okImgSVyA9evGioNkekqT6ITo/3ePaO1Grjff6k+mSU1iH4prmtXrny0TLRyqN6nB87uQqcg1hhsCPENT5o7NPbRbK4HHYTRShCD0Yj3W8hViBTOgrEqf50yYbxkZGr+TphPkhD9P0XVBZlKHHWkdLdXNC6CthYeu57u2ym5JmrXIjbMLQwAxdxdDe1FBzH3q4EnrVn6FFfHka9Ghcbbp30yQykpUkqzeMao9NKYiPJCQtc9hFbSwUidaphPi2IPUGyOh7ZiZcbojba/uETBXzshvjnkk16wqfbQlh2w7a/xJNHyKpB7UvOcno8ilUY6jlUiMMRx3YTwMwDydcrqYGmg7Nn9ZdzXfY3PYMw8Oj0F31q7cV295XV1TMw8KfQ8/Yedpv/439S/j/Cx8BsPv7wzwOBo0YCIu/C2eGwQScXcCQJOYtoIT7XCsFyK+5j5IZz3L7WSLQbVbsEJTruQueM49kGD1H1t8hDl/TsWaZ8FQ29AgthQr101J6lCcSPD6AxFFDe9cZkA2koEGS2x0X6cjS X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 06:18:26.5481 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3c34be0-8fec-4604-1f73-08dcb05f6c6a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000014.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8167 X-Patchwork-Delegate: kuba@kernel.org From: Shay Drory There is no point in recovery during device shutdown. if health work started need to wait for it to avoid races and NULL pointer access. Hence, drain health WQ on shutdown callback. Fixes: 1958fc2f0712 ("net/mlx5: SF, Add auxiliary device driver") Fixes: d2aa060d40fa ("net/mlx5: Cancel health poll before sending panic teardown command") Signed-off-by: Shay Drory Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 527da58c7953..5b7e6f4b5c7e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -2142,7 +2142,6 @@ static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) /* Panic tear down fw command will stop the PCI bus communication * with the HCA, so the health poll is no longer needed. */ - mlx5_drain_health_wq(dev); mlx5_stop_health_poll(dev, false); ret = mlx5_cmd_fast_teardown_hca(dev); @@ -2177,6 +2176,7 @@ static void shutdown(struct pci_dev *pdev) mlx5_core_info(dev, "Shutdown was called\n"); set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); + mlx5_drain_health_wq(dev); err = mlx5_try_fast_unload(dev); if (err) mlx5_unload_one(dev, false); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c index b2986175d9af..b706f1486504 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c @@ -112,6 +112,7 @@ static void mlx5_sf_dev_shutdown(struct auxiliary_device *adev) struct mlx5_core_dev *mdev = sf_dev->mdev; set_bit(MLX5_BREAK_FW_WAIT, &mdev->intf_state); + mlx5_drain_health_wq(mdev); mlx5_unload_one(mdev, false); } From patchwork Tue Jul 30 06:16:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13746721 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2052.outbound.protection.outlook.com [40.107.223.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB92816B39F for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Shay Drory , Maher Sanalla , Tariq Toukan Subject: [PATCH net 2/8] net/mlx5: Fix error handling in irq_pool_request_irq Date: Tue, 30 Jul 2024 09:16:31 +0300 Message-ID: <20240730061638.1831002-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730061638.1831002-1-tariqt@nvidia.com> References: <20240730061638.1831002-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D7:EE_|LV3PR12MB9144:EE_ X-MS-Office365-Filtering-Correlation-Id: ac43f48d-5482-42ff-7f5b-08dcb05f6d58 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: nVra8myJ5i1Gukoogc+eIGC1PsTJwhDlA/m4FhKs2EDB6Hx04MkeiwXzUrBSzmYmpdgk0gaoDVoRyfBBOfO+JJqN5rP912Ht1mJk4JTsF0ReCnsYHtv33lIt/4T8wRSbXuDizooFSuGYDoBlANRMttrCQFEVPsklrtzpXbRug/h1dZbEw68IyPFCYwKwrE0s3fehJd1yXAg/lMi3Uikr+irMvbX81Sy4IrJqLye3vHC5g6kflDRf4zVESl+7ugYYyQ0jajsCZMGWsCnSUpEy5Dbcz7AOOy01PCISEmUwFSaqOpR3stk/LbLfsqUEkPMhEqmVTRiuJwFZrxhG0Ah2ha7Sw1gk3dbK7tEW083vrs0l0AeYC0jSLDiWXwsdly3tnUuvM3saogtI3ZBxrmN/452aI7b/b8zdmjxO6M9KWTWrj1zHaceFnFismpxVV5mnwNjB0pxP1EHPICvEcg5iz42SVI62VsEY4WG6e9cnfKfXee9Ru2W8DhGKd0AwZapOqMKO2abMWW/iSIjSJHH0c/rYbI6E4FN3vVHBkv65yRjcG8eXE5nuIhLPUY3Ixxa6Ghe9y/2VG/1+SY7SDspUAfQnVh/7cUoa278AVUSbrNKhj0jsrd+itNwy0wbpDgzzTI6/qlbpSQx8/JZ6F6EN0dTTWGpygUq6Sl4FN/0A6V79hcSfswvNwt2c30VsXYx3dwkq6BlDlWNLq/BkVS9QYnY+0wflimiFwv99/7ynVDTiV7yHZxBVKaMAbhZlBKkzBSpkM71E67Zj0fowCsXFt60O51hsvPEK1scIO54bOZs4jclGNFfP7vhOlj8QGVw1bzzW1DmaObmeVLi2odJr9s/0qpjw2h96bNNqX+1q9eRM/jaFG4N8K0/6CpgJo95U1aZR+doj/0gl8nbUz1/5Gn5D1epglai5OKy60eLSHrwfn9EWm+XuZxrM0wxDCZ7leeBaw9hr8b+VD+kDr0kBg9JD4BALTP0ALcTUgWY/aN8ewwu8bbEEDcYpXrFVzFODBT84lMBeUwEyR6jY8F6Qqpi52Jsj3ErSJcHT53lnADW/jt1wlicZZP8YlJj4hR2NXuG2+/3fKsrveovy2aMlfq2nUDClLyGHxAsouZ8D5SSuAYFooxrS+CY0xYeQX9aFFrT8TOQ/W52fRR7oG5/b3g9KOFSrh1gGSqVEjazT2fVNMaHpttoV+a9dhia2FXJsabfJsckHsvM6mtke2M1Oi1oSgOXfzdtZUrLaIVPY31cy6XezfJlht0uN5DaOjHZyt9ugFIVadDepW4STacXxL90ihiP+EcOzAUcNZkX5+hPb9rbzC7ywsH03XTGosWwlnI/bezbVSz1WzDiNoDqdfz0i5N1Pea7OixLAlJOcOThgEvVJyDV10Ci/lN7uSY4+6mmOo+uJNO5cBV9ldxirR2dUY4fXJayxdhQJ+8X3YiKZnVAXEHVdtKZytvpyuTzL X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 06:18:28.1103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac43f48d-5482-42ff-7f5b-08dcb05f6d58 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9144 X-Patchwork-Delegate: kuba@kernel.org From: Shay Drory In case mlx5_irq_alloc fails, the previously allocated index remains in the XArray, which could lead to inconsistencies. Fix it by adding error handling that erases the allocated index from the XArray if mlx5_irq_alloc returns an error. Fixes: c36326d38d93 ("net/mlx5: Round-Robin EQs over IRQs") Signed-off-by: Shay Drory Reviewed-by: Maher Sanalla Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c index f7b01b3f0cba..1477db7f5307 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c @@ -48,6 +48,7 @@ static struct mlx5_irq * irq_pool_request_irq(struct mlx5_irq_pool *pool, struct irq_affinity_desc *af_desc) { struct irq_affinity_desc auto_desc = {}; + struct mlx5_irq *irq; u32 irq_index; int err; @@ -64,9 +65,12 @@ irq_pool_request_irq(struct mlx5_irq_pool *pool, struct irq_affinity_desc *af_de else cpu_get(pool, cpumask_first(&af_desc->mask)); } - return mlx5_irq_alloc(pool, irq_index, - cpumask_empty(&auto_desc.mask) ? af_desc : &auto_desc, - NULL); + irq = mlx5_irq_alloc(pool, irq_index, + cpumask_empty(&auto_desc.mask) ? af_desc : &auto_desc, + NULL); + if (IS_ERR(irq)) + xa_erase(&pool->irqs, irq_index); + return irq; } /* Looking for the IRQ with the smallest refcount that fits req_mask. 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Yevgeny Kliteynik , Alex Vesker , Tariq Toukan Subject: [PATCH net 3/8] net/mlx5: DR, Fix 'stack guard page was hit' error in dr_rule Date: Tue, 30 Jul 2024 09:16:32 +0300 Message-ID: <20240730061638.1831002-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730061638.1831002-1-tariqt@nvidia.com> References: <20240730061638.1831002-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000013:EE_|CY8PR12MB7684:EE_ X-MS-Office365-Filtering-Correlation-Id: 74b89a35-0c86-4dcd-4540-08dcb05f7080 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: oDioGFIoOxIFKfWstcwgmlIJ15CEioeBfOCKmpC+1dBMahVrplXBRwH3xfBTwRJpDEtfquX7NhYxCCF6+xGpyA1bwAojOW6GYnuJGgGD9hFoksPRIkaE6r/dEzDBvliYc5yvr92lYRUlPi9KS4nsHuSU1qXm5ISf2yqtHdctgtNeXVlZd/8I5+C63ZtiZx7lwHy5FZGm7Phn6iSXZOxANQzyJtaVuGW1c83GPhRrc7mowPuuJ+PBoP8iXA9RfiZwjmpEA7BthoqYb7ijQEYmqn2WMVqk4qLZlOYeePJrvFfI1PHiLO3pRzqG2jMj0MoSSu6Fq1LxhSKCgY0EvbuE3/8VKsT66AWyzl4QCHL+7dfPuzBIxZU+FR3zPubYBs4z6CPF/0oRwaShqKmR0nNlESSCrNV+jtKcTKOmK9bmbG8qbxJkuHGv6Hvww1VSFZLG3WQ93pMMaAWrWFyC2pmsSCL876vnKpfYONIlPLjpDGlO0Mz81dL6zI+euez8biEEeav69mfHZw4QFs45/SMrbnOEpPOLp3xeXjeLH2MGRP8Z2aMnZYTMvJlbO95Q81IHEC8ekt5HRnQe8MJakc8yRz6BWBp/k4nQ2wCbT8yLbLKgbTnoPVnanlYftArHdFXaa9zbkhzSxltbDJa1fg8q4CR3GO0rX1MKZiPQIgqgBGXYWVxaZuClvEOApe4lUVcvC0T/eMgFppps1qpPd7KcWEetK5XrUprrDucAevxTKDH/5D2/7LAjzFqWrYwgLFmS3s7yWErEkf3nnsPCsQYH/ZXTO4f+8iZh8jqRAEsbx6+uqhG7YXtZ6+cZdQX9bNjd8/lVyruE30zR5uk4Fi07CNTGsEcWlGiPdzq2Z5WvT5zghY15GUah+dNIxUFGUrZPCI+L0urWQ65vLkpR5ob+qEmW/4db6jGw/dOt6bjGVMIgeuE5SOu52OMYojZbvJDi8/4zA1i45FAcNkzpJGY4N6kVKDwopWtGJWvDlOJsT+EuaFlhxVyPjI5gszAs3A5aktBljNnkA9/73V0Fa5b3JEivyB1Zy7BQCGglZojBUUByA7hVJO7UTN1Zlbuj7EBlr62Hh+tXr5/+u+LEUdiPhKRj0OJu8hfi4+f8DpVZ3s193r8PKgEwQi4cYNLKmMWQ9M8C1Zo3+fLgwECQVvFjA0zrBA4HDdtd5PFvdTmWpKd6xgVWS0ZMhLlq2cPC6NOtTrwk2iPVh72s4EC83PZ2KF+ZaPnMXF4zXMzxngGXuCWZQtCoQAcs+UQDkRM11FG/i2kryZFOlTnlBSCjEDC/wcqiCQJh+79CiL71kk9lR/lup1GaIUj+O3yV7zm3sSIgTDHz8MF2Icg7vlk2MQxEVSPnml+rqoyQXX+k9kSITlg8iu6pT8mQY8xlH+fHN1HkQGFMxohpGhRBLe5yOjQTZM28e+d3ORAQXQCnbNiesaZ2X+4Mh7xZ4Nxtisv7rl1Y X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 06:18:33.4510 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74b89a35-0c86-4dcd-4540-08dcb05f7080 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000013.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7684 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik This patch reduces the size of hw_ste_arr_optimized array that is allocated on stack from 640 bytes (5 match STEs + 5 action STES) to 448 bytes (2 match STEs + 5 action STES). This fixes the 'stack guard page was hit' issue, while still fitting majority of the usecases (up to 2 match STEs). Signed-off-by: Yevgeny Kliteynik Reviewed-by: Alex Vesker Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c index 042ca0349124..d1db04baa1fa 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c @@ -7,7 +7,7 @@ /* don't try to optimize STE allocation if the stack is too constaraining */ #define DR_RULE_MAX_STES_OPTIMIZED 0 #else -#define DR_RULE_MAX_STES_OPTIMIZED 5 +#define DR_RULE_MAX_STES_OPTIMIZED 2 #endif #define DR_RULE_MAX_STE_CHAIN_OPTIMIZED (DR_RULE_MAX_STES_OPTIMIZED + DR_ACTION_MAX_STES) From patchwork Tue Jul 30 06:16:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13746724 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2054.outbound.protection.outlook.com [40.107.102.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8739716C877 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Tariq Toukan Subject: [PATCH net 4/8] net/mlx5: Lag, don't use the hardcoded value of the first port Date: Tue, 30 Jul 2024 09:16:33 +0300 Message-ID: <20240730061638.1831002-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730061638.1831002-1-tariqt@nvidia.com> References: <20240730061638.1831002-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000013:EE_|SA3PR12MB7831:EE_ X-MS-Office365-Filtering-Correlation-Id: f961437a-082c-4fc3-adcb-08dcb05f7352 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: Mz2bI/ydM2j3K+xZ4eEq69iL0UuZ2bwFYM5WR29XbvadgK+PpBKixAkrMAPEN5pPZbBJzpElrjkwHczMTqeeaXzQUphoI7AH8kwmRC50UKRdn+0BiIl06+NoRP7iJTqATs+aMmsp4Yza5I7d5gpa3wpaGdFLrThbzN45lvPR/dt6fm46UQAZ/uqb2EbsTG6Or6t5bGWb0Ul/iEhpaW+OalTeSQU2+2QYdk3YysYCWCjKXGn3hfVM1CrYl9G5kEg8Tt1oJHkZqKWaXQ7dXbW6KI2Xv6qw2QYqxizazfMHJrHTJ+sZvuLwQyZF5ZgcQ7cXAxxBm6FPTeDZr8m5VctRjASbX72J20RzXuKJOXAWZe4dtjlOygxO7ZGkmHamR+7CArqM3wOKNnkYWWL58umgbLst3OxD49tWo3yacKTLyXwVil1co2K5LpfL1EfttWjLKLypjwF6lB4JkVO+JQICNjEWUfFbUBfF6cHJW7/92gfe6kTDwuISfJbgQm0YACr06bl3ebzwjMA3g99dFQFj+4xS5nXVq3wKkIMSNP+7YvhVNXwPONRnvkl+ZNnmp3XWRoD62/JN/H0MHTmvc5YNbXvzjzhZ21TlFifvMXyvCf9FF8BAzjHPmz01f9cQA9h9zYGq9CtigV4bZuI64g0Rc7aNn0ZU83Cf/8GyB8ujBMi1Gg8oGgQ9QC/FAGYQQT6+HxlnXZgiZMGgYOssplspUB7UkhVa35p/+lTSUhqZoABDw10A19kki4V+URT7d9YxGuq6XgVh9bBjurudtHLNDDsK/L+mINcFAabN6dQYHaMZ+CwIg/59mmdUPTgWZnJ6elxtB9hT0CDaAxuQ+EJSSjhjid65+WdE+q6NKLSV+JGQ+a4/CimYrYLe+KxK+lcl4jvhGmS7gSxyI1+l91u9ckQ0XDrm/3R5a1O3vxKyy/CJLvbERgq12Onw4dVITHe0xqdxTrAo3vNZZhGduhGm7Zt88uMzADWfuBFisMozhbQBZRS+mkPAQkE9GeimzkZDZYBdVPmpqdsdnOElLvro4uahc/pwYsMv/9bw3UP1c9BmmNPwgdRZe8yIQQ8jdtEooTw4c4pXFranCdvelIGmVC+I9wHrRsXd80hhHXoKxSn3iNhnPqB7eaXjUOO6S9qYQTxuBgriN+0YooBeMpyuoQhbQv/9lW/H+nlJ37ejjQoK9o4RdJoph94Xw9nH2SF2/nEcruPqvmHGq1BMwGFeJn8n6XLrnHg3belRA/8kwD2gOJrY3I/tTGcq40ZDPhDQ+8Ua5Va6JK/n21Ici5u2CoAbA7SbveTAEow2glvobJZMKkgP2S4IDXjYZVY23RI+GO0NVQXfmeFd6nh8Ep9phb13rlUamja3lQ8cNJanyhnhmCK8crcUMLuiItdYH2dVxWRO1/1W7qNfWlMh1HJlOltRfdzntJWvLrEccV1q4t/lHQVHmykGSIhFGbRoAcnG X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 06:18:38.1385 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f961437a-082c-4fc3-adcb-08dcb05f7352 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000013.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7831 X-Patchwork-Delegate: kuba@kernel.org From: Mark Bloch The cited commit didn't change the body of the loop as it should. It shouldn't be using MLX5_LAG_P1. Fixes: 7e978e7714d6 ("net/mlx5: Lag, use actual number of lag ports") Signed-off-by: Mark Bloch Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index d0871c46b8c5..cf8045b92689 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -1538,7 +1538,7 @@ u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev, goto unlock; for (i = 0; i < ldev->ports; i++) { - if (ldev->pf[MLX5_LAG_P1].netdev == slave) { + if (ldev->pf[i].netdev == slave) { port = i; break; } From patchwork Tue Jul 30 06:16:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13746725 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2081.outbound.protection.outlook.com [40.107.223.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87ABD18FDBD for ; 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Mon, 29 Jul 2024 23:18:26 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Jul 2024 23:18:26 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 29 Jul 2024 23:18:23 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Moshe Shemesh , Maor Gottlieb , Tariq Toukan Subject: [PATCH net 5/8] net/mlx5: Fix missing lock on sync reset reload Date: Tue, 30 Jul 2024 09:16:34 +0300 Message-ID: <20240730061638.1831002-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730061638.1831002-1-tariqt@nvidia.com> References: <20240730061638.1831002-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D9:EE_|IA1PR12MB6161:EE_ X-MS-Office365-Filtering-Correlation-Id: 56d4c2f0-37af-4883-2e00-08dcb05f74e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?q?+Y9uaBU1UtvuA5GqqPyORdYMPk52DdD?= =?utf-8?q?IbNJpRgSZgRotK3X0WBSWjDW1llWKAE5v2ZxSpsEUph6d6gsLyzr1JSTMyPWoXQzU?= =?utf-8?q?to4zjPWuugnuOzmF0U6KReIOxSKmsL0Yu52zfseVryZUw9kyz9P6CZYGkt8TvDkzb?= =?utf-8?q?m6FuEMpNVryW8Ko9XpKofkUH4492b5aI9g5DLvWoUglsaT/r2ynWGpCCrBTmyrhJ+?= =?utf-8?q?Ot5qxPToC+PYhkO7ki50zwGf39qoRfmSMXtsnvdmmuYp2IukuWxTY7CePVmaMz6vq?= =?utf-8?q?JaUyRTOLKVoViHXOonsRuLaivT2PQOb4yfyxDA5x0xJAA/pmA2sCvrWkCDUOhb3BR?= =?utf-8?q?UaIOlq95Vm9tYcRJlfgCxAMvTOf25DxlIQ0IPbAbCC7R9Q+ljcPiNhFc15WXb8kdf?= =?utf-8?q?/nnWZojLkk93HSlSVfDlkXPEXMRuqGxJprD1CDxHtNx8uOpTNQfDPpd664/8FKKCC?= =?utf-8?q?8+BFHnU4U3vUwcJOM5maxMUaKgMRF8wIWUBRC9edpZbGNK3J026/1qDvF79j2w1xS?= =?utf-8?q?Qx/7X0ucfSv2PSv3aVSxyEIwDttBs7wppeGqxGdDWwAPMOAzN27vczYCc+6KZZhb4?= =?utf-8?q?zabAAZuDK9flWsT7c6N6c8hdqcM2uOyU3KknExwT0e8D1N9+vewjVPvp4nd0fqVZu?= =?utf-8?q?QVNqmUiAabu1RrU5q0158tNpV0uqDVTI7xZiZGA23gQ4MvpqKploPObyXYo3L/sCO?= =?utf-8?q?o3gFyfpCmXtSpNWCMwhawiIQ+iSdKrQzbUWCc+6EtCBAP33cXHAjvCj1vwxJZW55m?= =?utf-8?q?Zu936kQb565l2i55Gle0ME3IY5CTwQkhGW1heUzu8zW10/Zj5mWBAguu7hX5RUzov?= =?utf-8?q?oenwAzv287JEg4Y2Biv+n7Rgtxow/u1e3EOxM3F9hZxDKNwo0HiSX+6ueSboqxIuW?= =?utf-8?q?1sRW67vl0ozbgsZ2CayWJhukmM0IxdV75fXci+bpn8pssBZPsr2EiXhku4wYW49bS?= =?utf-8?q?O3pIvB3N/oTN9HXVfg5lXLpghjXnjajpYcxzxXpWuQmKWVL56Dq3XqaDpdlAya4m4?= =?utf-8?q?p0TlJWuWO5zarOXA+it6rWuGdE7EcmL5tgURwPM09y4fTrbRCo9ThvvEn9x40UwZa?= =?utf-8?q?57cs07sleKOUkoUsahHOqYmDvRJPk2ZIRxB3EJCo4luoUrfgGeBv5MaIm10ZQ5hfG?= =?utf-8?q?0ekoKiKFeCo4PeVIhjW8uC6o6M+sMHr8MsoCv5CjQczu5AE+trjA09SeGeSISD9xA?= =?utf-8?q?nHoIFkBexj12h3wR5X33CZDKVtEuR7MB6OPIqopKZtpeX1I7sQ5fEcHQEoKOOW04u?= =?utf-8?q?ROH/pvDV1WIv8WBkTHXJ3LZSxRUb/iX0DbAldXSQUn8TlexeqJKmc5rscrfX59P++?= =?utf-8?q?k8aASg4W2IG62XE70d+5mauoxa9nhgGiQk6B2M7wVnsYuD7SpfOB2Lgh4OF2Zron/?= =?utf-8?q?TLssLpNBqiJ?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 06:18:40.8116 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56d4c2f0-37af-4883-2e00-08dcb05f74e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6161 X-Patchwork-Delegate: kuba@kernel.org From: Moshe Shemesh On sync reset reload work, when remote host updates devlink on reload actions performed on that host, it misses taking devlink lock before calling devlink_remote_reload_actions_performed() which results in triggering lock assert like the following: WARNING: CPU: 4 PID: 1164 at net/devlink/core.c:261 devl_assert_locked+0x3e/0x50 … CPU: 4 PID: 1164 Comm: kworker/u96:6 Tainted: G S W 6.10.0-rc2+ #116 Hardware name: Supermicro SYS-2028TP-DECTR/X10DRT-PT, BIOS 2.0 12/18/2015 Workqueue: mlx5_fw_reset_events mlx5_sync_reset_reload_work [mlx5_core] RIP: 0010:devl_assert_locked+0x3e/0x50 … Call Trace: ? __warn+0xa4/0x210 ? devl_assert_locked+0x3e/0x50 ? report_bug+0x160/0x280 ? handle_bug+0x3f/0x80 ? exc_invalid_op+0x17/0x40 ? asm_exc_invalid_op+0x1a/0x20 ? devl_assert_locked+0x3e/0x50 devlink_notify+0x88/0x2b0 ? mlx5_attach_device+0x20c/0x230 [mlx5_core] ? __pfx_devlink_notify+0x10/0x10 ? process_one_work+0x4b6/0xbb0 process_one_work+0x4b6/0xbb0 […] Fixes: 84a433a40d0e ("net/mlx5: Lock mlx5 devlink reload callbacks") Signed-off-by: Moshe Shemesh Reviewed-by: Maor Gottlieb Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c index 979c49ae6b5c..b43ca0b762c3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -207,6 +207,7 @@ int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev) static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded) { struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net 6/8] net/mlx5e: Require mlx5 tc classifier action support for IPsec prio capability Date: Tue, 30 Jul 2024 09:16:35 +0300 Message-ID: <20240730061638.1831002-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730061638.1831002-1-tariqt@nvidia.com> References: <20240730061638.1831002-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D8:EE_|SA1PR12MB7200:EE_ X-MS-Office365-Filtering-Correlation-Id: c47fc560-901c-4ed0-d40a-08dcb05f76ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: LZ6xpspupe+XXnpDT6LfICWnY3yj10krN5dhamReiOCskFssJdKdiOxSkuKc4xj8wi5FV4Y4Vwjl+B1Jyori0UD5eJTUax5GLeD/0gDoXgDXRgpza9er6EVjqeakg3D9DmGoEI3eY6v87Ib+g7zeyXjNIhnKWezXbZDHfaCXFK/97G4Fh3Mo1MN1ToNLhCaokRZeeQxBoIhnsNP3MCbqBkiKmjBhlw9L1cGUaavZsRemBNaV7N0z+Xeukh+/ckdJsUm2kgxIm9ojhToQp3qfPGLmo7m8kWfF8C2saYLjr6lpqdAcvxTtXOpg7PA7cC6U21vBYVFZYB1Ku+dhf/dbaTeTZEZGIqp7dBzVsNz7tUWLdhbI3ccm5fFmTuebQoV4MIyo/Vgn3Y6e9UTtorVGbnUV2QVWNHrNyUKcDkBu0qMGQgVLWRiHEorf5/8NOhjQ9IdcuS+VY3tqHilRSA27VUsmDfTPJG0os1vq7Z4T3o5r8o244dHFe+lrIShk28pPUxYeDTPPYcP1NAXAiEOC7Ho99HLxgPkwIO6b2G3Xct5B5g/u0NKI+i04dKuRTutMFT7oHVCAnm/3vkFmShAWV0NN+k1CWmhG/GFgxga0iKxEa+RbZ3cjL8WNQ6zVLKUpTT8jWbguJWhCZNeKa4hsVhFZVHTzXKAzvpdwjGaQxRT2ZS8sUKxyQaSbrPK9DSzdcVm5sPAQsGcaIumZJhkxqfSRryNdhag15XZhAfKzdU2KeS1dxU/SGw7DhpZ0dLOvEgFTmR8PSTDn7L1dBw1E3bAO/eYVQlOcjkzzWCtLgyA8KBtKSWRYPSGRMMZP1MaKHEBD3fuP5Wnj4yKLLK/iEEwB/c5TxqolPtocq7LNbZI5k0Ekm74gwxB+VhsvOT62AXW28ZzBPsWjGVs/xpNsXTRwop1+ry1ij1YXg8gYxnJwKidReHbHyGGHUOrKglzjaPptrf8R9R/g4jk4b1pMdaLrp58d9tSDwshU/zm78GGu+BP+M3AYE6P6oZLDEp8nYa2xDUp+y+PycS8W+m/RmArjq5usUPuA/0zQC6IRqZS/Lu9Cp6c1hFjgkjNxgrnqnNUJQMTBTsaWKVlnVjOWInYQCY5LxvljeZJNkYxt7J4j8B1fC56vAJACFqpI2KjUBre/j2xnx/2nsWReeLT3jG02lb4rPz+A+Vh04Ij0LZniU32yQ2q4QNa9AUUZcZ2MR6TAy6l8dUJOKBMiVTN/yrHdaY6fSdtewfF3FBOxtuf9LktarVNFvvfzJsg9AWKiCXN83X+oIjnZstRpo2KqmFY66T+tJDjgOXU6RotVm9RgCEXVK1FoECdwjrg1J3gaRa/t8fUQAVQ43OwmVi+cVBTMPSrLtPXA5DapfBswVcuLjS6W+auKQCVdcM96I6ZHodKBv6uFFVtLe36bg+vdF4OZB2uAURvVQxjPNPJmx78qYXwueeHkc3y+Zw2Kdl9p X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 06:18:43.7624 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c47fc560-901c-4ed0-d40a-08dcb05f76ac X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7200 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu Require mlx5 classifier action support when creating IPSec chains in offload path. MLX5_IPSEC_CAP_PRIO should only be set if CONFIG_MLX5_CLS_ACT is enabled. If CONFIG_MLX5_CLS_ACT=n and MLX5_IPSEC_CAP_PRIO is set, configuring IPsec offload will fail due to the mlxx5 ipsec chain rules failing to be created due to lack of classifier action support. Fixes: fa5aa2f89073 ("net/mlx5e: Use chains for IPsec policy priority offload") Signed-off-by: Rahul Rameshbabu Reviewed-by: Leon Romanovsky Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- .../ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c index 6e00afe4671b..797db853de36 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c @@ -51,9 +51,10 @@ u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev) MLX5_CAP_FLOWTABLE_NIC_RX(mdev, decap)) caps |= MLX5_IPSEC_CAP_PACKET_OFFLOAD; - if ((MLX5_CAP_FLOWTABLE_NIC_TX(mdev, ignore_flow_level) && - MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ignore_flow_level)) || - MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, ignore_flow_level)) + if (IS_ENABLED(CONFIG_MLX5_CLS_ACT) && + ((MLX5_CAP_FLOWTABLE_NIC_TX(mdev, ignore_flow_level) && + MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ignore_flow_level)) || + MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, ignore_flow_level))) caps |= MLX5_IPSEC_CAP_PRIO; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Chris Mi , Tariq Toukan Subject: [PATCH net 7/8] net/mlx5e: Fix CT entry update leaks of modify header context Date: Tue, 30 Jul 2024 09:16:36 +0300 Message-ID: <20240730061638.1831002-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730061638.1831002-1-tariqt@nvidia.com> References: <20240730061638.1831002-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D3:EE_|SJ0PR12MB5675:EE_ X-MS-Office365-Filtering-Correlation-Id: 21a71b2d-45a0-40bb-098f-08dcb05f7825 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: FDuqbxnSJSn9uqIKNSD15JvgJsPC5h7WR5PPUb2kqvlex5Lzrz1w4lvj16v/HgoeEV93pRnDa7RQ776uwwT3ZCdEhIySLQizD32LZra8rFiMTpuOuuZWdJ8TX7nfNG3pxvLwkSzeN6FQG1PBP2kUQ5PHIMWDR0tNIQG4UrqZdAOProgR3QejWZimLgseFDY6UhJ6gu5WhqO5AT+rrp33mK1C8N/AsgVk6kPGjKTHVHbe2hb81+0HVqCVklcR8IWyci0XjUd4nZn9z1SYmmr0M7V+zYnwodNq5DZpOKVyhjThLIHAOkP9ZYkOVqBrsYSO6BWX9zTquJiqBSLhIJYIcUItFoguTfmxS/p6YtKK4ZuzdHW+gY8GbOOkH8rZpFmAEjg7CtGyrEAndahbPEu3kBPQFXPRQipT79ZrtktEVECQt1FS0WpF3SU0waSB725CVJti8XWJSBfSLL6gBW3U++sLLPkTYASlowKxND3PzH9HwAvggwXa4jSe6Tyf+jnNcvHG94JBZoni/sokjlUDo5GollkIuJXrRHFxXP+qjdlJiF03qA5Eqp3RIcQG+7GkFu8KQUuCSx07DLjUFVCUkgGqm3dRVDDxjhi/50NrSb1KFDeCfLX2SNfMzu7FmDvUMYkP7fZ6yTvXg8i8Ds+x9WVUkqfDsMS3Mp46Gs9a7pbRBCwhT5WAOw3Us1mtA6KX4x3d1RExZaW5wC4APp8RFwzR6icXo+AMvi8dP5hHuvH63dWHNZ7tY5KuiVo6fuhaKTrGyV3ltDbpNpzLXtgsdujXjjx1tPlE8/ti7q1lHnOX12hhhLGgSLEABYDozq65E3osA8KFJtCED5MOVp/skiq40SAdLLjWAArfeUOyMtNxY8APIMG8eX+HJ4lm9sIXaE5b1+ga4dUhH3RTJJYnA0ABnEd3/KPa/dIvwkcdSssHqY5wLlv1tm4l8fLkR/WJmcvJvpaLHJpFKhzt8HgiAR2EJ/0vk/O6OWfQhJ2PlDR8bv96UeEEKHWbPHsWqPflhUqHPemCLhecegWaZ8PVOR069SOap7R+1rOw8nU/ZmsRhwGTm32M4DVD3EncEv1JqIiJgH3JY5wJFjrfVRi9H99Efeb5Ox3mdZxv4iJ3bK3ZhALWmCDNNkjC+3IM/FsuCtoQSSF2mb3yg+FTEmRta+DcI+xlh+KKz+gsz4jA20nqsJxX2FauI2Ii1g3Z9uu6ZWOM1+Uwon1MOHOdtOWqU8hFD5Kdxfxq4ajUkvmAlOZ2M9TrS7KbS/mTrDPxvJU7xHVQifoLSsKV2vauPs5lTNUOluC90ig88Jb3LUp2m+TbtvEp8A+StWopr8fzC7jlhgZLsZN7+yHIX9WLMvbfcgt5/ejRTzBYkRc10T+BQe6wvmTWUT8EHHObDzZCvZx8cz8jzC3x1AQX7s3VmrgKRpsdOxGEXeZRvL8ZYiAZ30n+901EfeWOq1HuBCImzGfp X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 06:18:46.2280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21a71b2d-45a0-40bb-098f-08dcb05f7825 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5675 X-Patchwork-Delegate: kuba@kernel.org From: Chris Mi The cited commit allocates a new modify header to replace the old one when updating CT entry. But if failed to allocate a new one, eg. exceed the max number firmware can support, modify header will be an error pointer that will trigger a panic when deallocating it. And the old modify header point is copied to old attr. When the old attr is freed, the old modify header is lost. Fix it by restoring the old attr to attr when failed to allocate a new modify header context. So when the CT entry is freed, the right modify header context will be freed. And the panic of accessing error pointer is also fixed. Fixes: 94ceffb48eac ("net/mlx5e: Implement CT entry update") Signed-off-by: Chris Mi Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c index 8cf8ba2622f2..71a168746ebe 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c @@ -932,6 +932,7 @@ mlx5_tc_ct_entry_replace_rule(struct mlx5_tc_ct_priv *ct_priv, mlx5_tc_ct_entry_destroy_mod_hdr(ct_priv, zone_rule->attr, mh); mlx5_put_label_mapping(ct_priv, attr->ct_attr.ct_labels_id); err_mod_hdr: + *attr = *old_attr; kfree(old_attr); err_attr: kvfree(spec); From patchwork Tue Jul 30 06:16:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13746728 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2074.outbound.protection.outlook.com [40.107.220.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CDDA161914 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Shahar Shitrit , Carolina Jubran , Tariq Toukan Subject: [PATCH net 8/8] net/mlx5e: Add a check for the return value from mlx5_port_set_eth_ptys Date: Tue, 30 Jul 2024 09:16:37 +0300 Message-ID: <20240730061638.1831002-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730061638.1831002-1-tariqt@nvidia.com> References: <20240730061638.1831002-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000016:EE_|SJ0PR12MB7458:EE_ X-MS-Office365-Filtering-Correlation-Id: f560e52b-7de2-43de-8ce8-08dcb05f7b7d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: qIimqtZdBjXQmVbT/Bo4QnC2wYN1uZsB6aGYu0bnqWiM3WtafW5FrwyZlcSJwvxEX55rcZNw02qINs3YCLJ1dp/VJFB1aPVlEEwDFFPxR360zITUxivvWMtMhLPQLa7Fj9+mnRPy5IapDk7xXJIxoOoxbHABpU6H7kOhWfyhKK2nl2oz6lMWGlT1SJ7raZNBvFE/kFkAl8WcvmPtErtNLJYiOWOBkmvn7ba+LHHCBBz6n1348yWpi+qxZS/atkZMhp2qarrWAoVcl3r6C8WRD5+WsIEc4Uf/9c5u8q/crNWHTA3lzYLffGgIJcv32tqCy4wWGlVusk2jS9QInIhAYOq7MjErPBEgF49AKyiEKjKPWmiV7TwDHytbFZ0TUaZPBwKEd+QCoH1/oIHHdVRMCuZf4IH6Zdz2vUFBfiPq7uh4NiGWyiizZIlSBqwp/o3na6CciL5gKqcvJuqrwYj+ULgi2b1N16p/vU7BJAw3yK//jje42cRv+mYqPm09XgOvwYQ1KtunfKPhSbahcBChAEgb8Ket4u2S4cFUu47G7YpvArZ5ZRbofTPIgwxCojrG57bhWX6NQS1L7uAxxbFNQqivEpPIIUNVAoHV4xymuFceNvYUCNX9++nWdZY/jiy3A4NSweyyawnVweGJlt6YsYJ624EatAiZt9LOYi1PDxDUVgBKbajstkDSVY97BDk8NXyrrKQDSGDYyHHy+SErt5/+MhB/4VfA3T77IzaygR+P6g3ThogSJHANSd9UJaS5be9rZt+51zRH7lyDJMYTc9EB0CcHWRfl4upY5zvpXDlTfe4op7K/ISqzMh9QSLLYSZbQx81Epy+pzJKTxgwSsRvUUvacojCEwrrDl3mTTXEqNkRlxR6NCDm1LwT2Fdk8V89KY6pDm0FfsYaB89SvbRxi+xuu1xt815bh/PkLu0nAQrMkCRihMW6by6LQPIUG/KS+589JHRxPao1APziTmN69QqmmMEMHZJNMUpqGrzewcM1t/s2pBJOwiMbrRLJWN0nGlGgoY1uvrRFOafqxiFBzskAmv/CIIHxGEwCE3DXXKJ/x/rWywNrQtkfzUdcw6ndaxXRniW3PmLRj6KYvvDR/kIV/N66Oe4KgfjJTEynYe9hr0EHYHEiE/rTJzLa0T1oqsIw8qC0ZmB+oCpswLpxbc288o4ktSaZdJGIeZxMTLZ9BZe6k/zWl0J5mr3+BX15iw4Ylkz4hGVUoLy3a/R9Mu0tRf8dTapnsKHAyC3yBYtMnQ6IlYd58+2uojmKmHl5X7uKofeNpIS2iyPylw4KWZilZPGhpbvts/Fb172ySGL2+yhWvJNmwjFPBZOTS75TevbJoTeyoLGzFTtIIEtCo+je9/NshRR7waTMGtfl4h2W5jzdXN944aAfrNJAFaoYV9tBkCjD212X8g9/Q0f8idvHsY95WDuswscYUFVk3XKK5ye6kpfIe/Zueps5L X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 06:18:51.8256 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f560e52b-7de2-43de-8ce8-08dcb05f7b7d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000016.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7458 X-Patchwork-Delegate: kuba@kernel.org From: Shahar Shitrit Since the documentation for mlx5_toggle_port_link states that it should only be used after setting the port register, we add a check for the return value from mlx5_port_set_eth_ptys to ensure the register was successfully set before calling it. Fixes: 667daedaecd1 ("net/mlx5e: Toggle link only after modifying port parameters") Signed-off-by: Shahar Shitrit Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 00d5661dc62e..36845872ae94 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -1409,7 +1409,12 @@ static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, if (!an_changes && link_modes == eproto.admin) goto out; - mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext); + err = mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext); + if (err) { + netdev_err(priv->netdev, "%s: failed to set ptys reg: %d\n", __func__, err); + goto out; + } + mlx5_toggle_port_link(mdev); out: