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bh=g8epCXay0Jg+C/diMxaa0Up6nv/rRA5yt4XrpKr+p18=; t=1722448784; x=1722538784; b=CLV33i2RR1s3OZdZZy6upyq8KId+tc8aBkUaEEafJhuTeSO7Mnad+QfiHiPbL6wh8a0Gf7++bry nOBrOtcoT0S2CtQ50H7RP7jl9x/SnDcUFHo9nuvBVSl70GAoBe5AqW+C7jPp99zTz39f7aJuqQG8H DCM48JsNRV33Bd1g2VI=; Received: by exim-smtp-5c6c85c787-mv4xc with esmtpa (envelope-from ) id 1sZDbj-00000000IYY-0mGF; Wed, 31 Jul 2024 20:59:27 +0300 From: Danila Tikhonov To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, vkoul@kernel.org, vladimir.zapolskiy@linaro.org, quic_jkona@quicinc.com, dmitry.baryshkov@linaro.org, konradybcio@kernel.org, quic_tdas@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, Danila Tikhonov Subject: [PATCH 01/10] dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings Date: Wed, 31 Jul 2024 20:59:10 +0300 Message-ID: <20240731175919.20333-2-danila@jiaxyga.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731175919.20333-1-danila@jiaxyga.com> References: <20240731175919.20333-1-danila@jiaxyga.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailru-Src: smtp X-4EC0790: 10 X-7564579A: 78E4E2B564C1792B X-77F55803: 4F1203BC0FB41BD926BB450FD17188A915E3E16B49BA92E473D9E9365E0544A7182A05F53808504090544F0EEE1FCA413DE06ABAFEAF6705711FB7C5DE05C8A9F806485F292FBEEB141B3585208100AE X-7FA49CB5: FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE74D0D2DEF2EB846B0EA1F7E6F0F101C67BD4B6F7A4D31EC0BCC500DACC3FED6E28638F802B75D45FF8AA50765F79006378ABD31E9FF1CD53C8638F802B75D45FF36EB9D2243A4F8B5A6FCA7DBDB1FC311F39EFFDF887939037866D6147AF826D847B723E399AC477C995830582C796B1883259F87B893204ACC7F00164DA146DAFE8445B8C89999728AA50765F79006372A3B24BF85B2E607389733CBF5DBD5E9C8A9BA7A39EFB766F5D81C698A659EA7CC7F00164DA146DA9985D098DBDEAEC8ED96AA85C75E140D117882F4460429728AD0CFFFB425014E868A13BD56FB6657D81D268191BDAD3DC09775C1D3CA48CF56E3D212986C9D9EBA3038C0950A5D36C8A9BA7A39EFB766D91E3A1F190DE8FDBA3038C0950A5D36D5E8D9A59859A8B6D91B6531E6CC8CCB76E601842F6C81A1F004C906525384303E02D724532EE2C3F43C7A68FF6260569E8FC8737B5C2249957A4DEDD2346B42E827F84554CEF50127C277FBC8AE2E8B2EE5AD8F952D28FBAAAE862A0553A39223F8577A6DFFEA7C5B09DCDDD98ABCD243847C11F186F3C59DAA53EE0834AAEE X-C1DE0DAB: 0D63561A33F958A54D45E046ADEAFA725002B1117B3ED69659213019B8A0FB3BED71F038FC046993823CB91A9FED034534781492E4B8EEAD220496FFA5CD4785C79554A2A72441328621D336A7BC284946AD531847A6065A535571D14F44ED41 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF3FED46C3ACD6F73ED3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CFAAAE386D03EDBA5BB96FBCDEBE75CD5B6201D079E1A4D3280325D02851A02B2BA4BD9291AB2A84561D9D8FAF50ED830BE81C388445EAECB1C126D84212B092F69C9D13D1AD570697983AD880C8D3B7BB02C26D483E81D6BE72B480F99247062FEE42F474E8A1C6FD34D382445848F2F3 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2bioj2j9vV9f5a3u1/U5B8RMY7A== X-Mailru-Sender: 9EB879F2C80682A09F26F806C7394981A1FC0BF4BF26A8A10841F56765D88C405553DB1DFEC3BEC947F2D2A5A79AF8E32C62728BC403A049225EC17F3711B6CF1A6F2E8989E84EC137BFB0221605B344978139F6FA5A77F05FEEDEB644C299C0ED14614B50AE0675 X-Mras: Ok X-7564579A: 78E4E2B564C1792B X-77F55803: 6242723A09DB00B438D8D16241E2C9674218E0EBCD2528CD2DC820544DB7BD83049FFFDB7839CE9E45E89A588AFC070541965E3F48AB11C69E31339189790A75383B57F53CC0B9B9 X-7FA49CB5: 0D63561A33F958A50394500F873E365473F50D156C539EE3A9131AFC1D147B0E8941B15DA834481FA18204E546F3947C1CF6DFABFD638A7DF6B57BC7E64490618DEB871D839B7333395957E7521B51C2DFABB839C843B9C08941B15DA834481F8AA50765F7900637AF8DFA94C5B6F7D6389733CBF5DBD5E9B5C8C57E37DE458BD96E472CDF7238E0725E5C173C3A84C3777F8C72A04D893B35872C767BF85DA2F004C90652538430E4A6367B16DE6309 X-87b9d050: 1 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2bioj2j9vV9f5a3uooJveIBPrFQ== X-Mailru-MI: 8000000000000800 X-Mras: Ok Add SM8475 GCC bindings, which are simply a symlink to the SM8450 bindings. Update the documentation with the new compatible. Signed-off-by: Danila Tikhonov --- .../devicetree/bindings/clock/qcom,gcc-sm8450.yaml | 8 ++++++-- include/dt-bindings/clock/qcom,gcc-sm8450.h | 2 ++ include/dt-bindings/clock/qcom,sm8475-gcc.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-) create mode 120000 include/dt-bindings/clock/qcom,sm8475-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml index d848361beeb3..c7d75ee2a23b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml @@ -13,11 +13,15 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM8450 - See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h + See also:: + include/dt-bindings/clock/qcom,gcc-sm8450.h + include/dt-bindings/clock/qcom,sm8475-gcc.h properties: compatible: - const: qcom,gcc-sm8450 + enum: + - qcom,gcc-sm8450 + - qcom,sm8475-gcc clocks: items: diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h index 9679410843a0..5f1f9ab71a22 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8450.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h @@ -194,6 +194,8 @@ #define GCC_VIDEO_AXI0_CLK 182 #define GCC_VIDEO_AXI1_CLK 183 #define GCC_VIDEO_XO_CLK 184 +#define GCC_GPLL2 185 +#define GCC_GPLL3 186 /* GCC resets */ #define GCC_CAMERA_BCR 0 diff --git a/include/dt-bindings/clock/qcom,sm8475-gcc.h b/include/dt-bindings/clock/qcom,sm8475-gcc.h new file mode 120000 index 000000000000..daafdd881892 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8475-gcc.h @@ -0,0 +1 @@ +qcom,gcc-sm8450.h \ No newline at end of file From patchwork Wed Jul 31 17:59:11 2024 Content-Type: text/plain; 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Signed-off-by: Danila Tikhonov --- drivers/clk/qcom/Kconfig | 3 +- drivers/clk/qcom/gcc-sm8450.c | 182 +++++++++++++++++++++++++++++++++- 2 files changed, 183 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 11ae28430dad..decb41c4a58e 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1032,7 +1032,8 @@ config SM_GCC_8450 depends on ARM64 || COMPILE_TEST select QCOM_GDSC help - Support for the global clock controller on SM8450 devices. + Support for the global clock controller on SM8450 or SM8475 + devices. Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index c445c271678a..83e8f1a5d51b 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -26,6 +26,8 @@ enum { P_BI_TCXO, P_GCC_GPLL0_OUT_EVEN, P_GCC_GPLL0_OUT_MAIN, + P_GCC_GPLL2_OUT_EVEN, + P_GCC_GPLL3_OUT_EVEN, P_GCC_GPLL4_OUT_MAIN, P_GCC_GPLL9_OUT_MAIN, P_PCIE_1_PHY_AUX_CLK, @@ -36,6 +38,15 @@ enum { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, }; +static struct clk_init_data gcc_gpll0_sm8475_init = { + .name = "gcc_gpll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, +}; + static struct clk_alpha_pll gcc_gpll0 = { .offset = 0x0, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -53,6 +64,15 @@ static struct clk_alpha_pll gcc_gpll0 = { }, }; +static struct clk_init_data gcc_gpll0_out_even_sm8475_init = { + .name = "gcc_gpll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &gcc_gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { { 0x1, 2 }, { } @@ -75,6 +95,49 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { }, }; +static struct clk_alpha_pll gcc_gpll2 = { + .offset = 0x2000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x62018, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpll2", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll3 = { + .offset = 0x3000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x62018, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpll3", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_init_data gcc_gpll4_sm8475_init = { + .name = "gcc_gpll4", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, +}; + static struct clk_alpha_pll gcc_gpll4 = { .offset = 0x4000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -92,6 +155,15 @@ static struct clk_alpha_pll gcc_gpll4 = { }, }; +static struct clk_init_data gcc_gpll9_sm8475_init = { + .name = "gcc_gpll9", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, +}; + static struct clk_alpha_pll gcc_gpll9 = { .offset = 0x9000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -153,6 +225,22 @@ static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, }; +static const struct parent_map gcc_parent_map_sm8475_3[] = { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL2_OUT_EVEN, 2 }, + { P_GCC_GPLL3_OUT_EVEN, 3 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_sm8475_3[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gcc_gpll0.clkr.hw }, + { .hw = &gcc_gpll2.clkr.hw }, + { .hw = &gcc_gpll3.clkr.hw }, + { .hw = &gcc_gpll0_out_even.clkr.hw }, +}; + static const struct parent_map gcc_parent_map_5[] = { { P_PCIE_1_PHY_AUX_CLK, 0 }, { P_BI_TCXO, 2 }, @@ -915,6 +1003,16 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, }; +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src_sm8475[] = { + F(400000, P_BI_TCXO, 12, 1, 4), + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), + F(37000000, P_GCC_GPLL9_OUT_MAIN, 16, 0, 0), + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + F(148000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), + { } +}; + static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { F(400000, P_BI_TCXO, 12, 1, 4), F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), @@ -963,6 +1061,25 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src_sm8475[] = { + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0), + F(806400000, P_GCC_GPLL2_OUT_EVEN, 1, 0, 0), + F(850000000, P_GCC_GPLL2_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_init_data gcc_ufs_phy_axi_clk_src_sm8475_init = { + .name = "gcc_ufs_phy_axi_clk_src", + .parent_data = gcc_parent_data_sm8475_3, + .num_parents = ARRAY_SIZE(gcc_parent_map_sm8475_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, +}; + static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), @@ -987,6 +1104,24 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src_sm8475[] = { + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0), + F(806400000, P_GCC_GPLL2_OUT_EVEN, 1, 0, 0), + F(850000000, P_GCC_GPLL2_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_init_data gcc_ufs_phy_ice_core_clk_src_sm8475_init = { + .name = "gcc_ufs_phy_ice_core_clk_src", + .parent_data = gcc_parent_data_sm8475_3, + .num_parents = ARRAY_SIZE(gcc_parent_map_sm8475_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, +}; + static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), @@ -1032,6 +1167,14 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { }, }; +static struct clk_init_data gcc_ufs_phy_unipro_core_clk_src_sm8475_init = { + .name = "gcc_ufs_phy_unipro_core_clk_src", + .parent_data = gcc_parent_data_sm8475_3, + .num_parents = ARRAY_SIZE(gcc_parent_map_sm8475_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, +}; + static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .cmd_rcgr = 0x8708c, .mnd_width = 0, @@ -3166,6 +3309,8 @@ static struct clk_regmap *gcc_sm8450_clocks[] = { [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, + [GCC_GPLL2] = &gcc_gpll2.clkr, + [GCC_GPLL3] = &gcc_gpll3.clkr, }; static const struct qcom_reset_map gcc_sm8450_resets[] = { @@ -3259,6 +3404,7 @@ static const struct qcom_cc_desc gcc_sm8450_desc = { static const struct of_device_id gcc_sm8450_match_table[] = { { .compatible = "qcom,gcc-sm8450" }, + { .compatible = "qcom,sm8475-gcc" }, { } }; MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table); @@ -3277,6 +3423,40 @@ static int gcc_sm8450_probe(struct platform_device *pdev) if (ret) return ret; + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gcc")) { + /* Update GCC PLL0 Config */ + gcc_gpll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + gcc_gpll0.clkr.hw.init = &gcc_gpll0_sm8475_init; + + gcc_gpll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + gcc_gpll0_out_even.clkr.hw.init = &gcc_gpll0_out_even_sm8475_init; + + /* Update GCC PLL4 Config */ + gcc_gpll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + gcc_gpll4.clkr.hw.init = &gcc_gpll4_sm8475_init; + + /* Update GCC PLL9 Config */ + gcc_gpll9.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + gcc_gpll9.clkr.hw.init = &gcc_gpll9_sm8475_init; + + gcc_sdcc2_apps_clk_src.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src_sm8475; + + gcc_ufs_phy_axi_clk_src.parent_map = gcc_parent_map_sm8475_3; + gcc_ufs_phy_axi_clk_src.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src_sm8475; + gcc_ufs_phy_axi_clk_src.clkr.hw.init = &gcc_ufs_phy_axi_clk_src_sm8475_init; + + gcc_ufs_phy_ice_core_clk_src.parent_map = gcc_parent_map_sm8475_3; + gcc_ufs_phy_ice_core_clk_src.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src_sm8475; + gcc_ufs_phy_ice_core_clk_src.clkr.hw.init = &gcc_ufs_phy_ice_core_clk_src_sm8475_init; + + gcc_ufs_phy_unipro_core_clk_src.parent_map = gcc_parent_map_sm8475_3; + gcc_ufs_phy_unipro_core_clk_src.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src_sm8475; + gcc_ufs_phy_unipro_core_clk_src.clkr.hw.init = &gcc_ufs_phy_unipro_core_clk_src_sm8475_init; + } else { + gcc_sm8450_desc.clks[GCC_GPLL2] = NULL; + gcc_sm8450_desc.clks[GCC_GPLL3] = NULL; + } + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); @@ -3312,5 +3492,5 @@ static void __exit gcc_sm8450_exit(void) } module_exit(gcc_sm8450_exit); -MODULE_DESCRIPTION("QTI GCC SM8450 Driver"); +MODULE_DESCRIPTION("QTI GCC SM8450 / SM8475 Driver"); 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Update the documentation with the new compatible. Signed-off-by: Danila Tikhonov --- .../devicetree/bindings/clock/qcom,sm8450-dispcc.yaml | 5 ++++- include/dt-bindings/clock/qcom,sm8475-dispcc.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) create mode 120000 include/dt-bindings/clock/qcom,sm8475-dispcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml index 4794c53793a8..76f5a8cc42cc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml @@ -13,12 +13,15 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SM8450. - See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h + See also:: + include/dt-bindings/clock/qcom,sm8450-dispcc.h + include/dt-bindings/clock/qcom,sm8475-dispcc.h properties: compatible: enum: - qcom,sm8450-dispcc + - qcom,sm8475-dispcc clocks: minItems: 3 diff --git a/include/dt-bindings/clock/qcom,sm8475-dispcc.h b/include/dt-bindings/clock/qcom,sm8475-dispcc.h new file mode 120000 index 000000000000..21a9db2d0f09 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8475-dispcc.h @@ -0,0 +1 @@ +qcom,sm8450-dispcc.h \ No newline at end of file From patchwork Wed Jul 31 17:59:13 2024 Content-Type: text/plain; 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bh=MNTdLq98UluVQT6zc6ezhte0eSzBe52Pmk4Ar4jVVK0=; t=1722448782; x=1722538782; b=eJerZKTE1qIwF3SaNe/C2Y/7AX05ZBGql122DZE+kcb6tBvZoxpVXzDj6GEwGtD2U5dZKRs5I6c /HBpIx+PWbc0Rqj6wX+RrXyA0VvPaNLwqA2/7uvob2OVUAyo/WUN7+7WM+pvZFWdE4Dgg/hOHx7tg 9sXotp/A6f/0HEjHqqI=; Received: by exim-smtp-5c6c85c787-mv4xc with esmtpa (envelope-from ) id 1sZDbp-00000000IYY-34Hg; Wed, 31 Jul 2024 20:59:34 +0300 From: Danila Tikhonov To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, vkoul@kernel.org, vladimir.zapolskiy@linaro.org, quic_jkona@quicinc.com, dmitry.baryshkov@linaro.org, konradybcio@kernel.org, quic_tdas@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, Danila Tikhonov Subject: [PATCH 04/10] clk: qcom: dispcc-sm8450: Add SM8475 support Date: Wed, 31 Jul 2024 20:59:13 +0300 Message-ID: <20240731175919.20333-5-danila@jiaxyga.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731175919.20333-1-danila@jiaxyga.com> References: <20240731175919.20333-1-danila@jiaxyga.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailru-Src: smtp X-4EC0790: 10 X-7564579A: 646B95376F6C166E X-77F55803: 4F1203BC0FB41BD926BB450FD17188A9AD89A2A5D4CA2288CAB961C0C201B531182A05F538085040DA430C42C03EF50A3DE06ABAFEAF6705289E9C3536A6F507F806485F292FBEEBA7398ABDDC9FB8BB X-7FA49CB5: FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE76DD23B0452F84E3CEA1F7E6F0F101C67BD4B6F7A4D31EC0BCC500DACC3FED6E28638F802B75D45FF8AA50765F79006378D08D652E28591A78638F802B75D45FF36EB9D2243A4F8B5A6FCA7DBDB1FC311F39EFFDF887939037866D6147AF826D81CDF03BD932202F4995830582C796B18EF28B70C237C8726CC7F00164DA146DAFE8445B8C89999728AA50765F7900637028599BB38096F4F389733CBF5DBD5E9C8A9BA7A39EFB766F5D81C698A659EA7CC7F00164DA146DA9985D098DBDEAEC878444BBB7636F62AF6B57BC7E6449061A352F6E88A58FB86F5D81C698A659EA73AA81AA40904B5D9A18204E546F3947CDA7BFA4571439BB203F1AB874ED890284AD6D5ED66289B523666184CF4C3C14F6136E347CC761E07725E5C173C3A84C305525BC79FAC2943BA3038C0950A5D36B5C8C57E37DE458B330BD67F2E7D9AF16D1867E19FE14079C09775C1D3CA48CFED8438A78DFE0A9E1DD303D21008E298D5E8D9A59859A8B6957A4DEDD2346B4275ECD9A6C639B01B78DA827A17800CE7CD707F342D9BDC98731C566533BA786AA5CC5B56E945C8DA X-C1DE0DAB: 0D63561A33F958A54471CEB927CB90995002B1117B3ED696632C0940C7DD2CF9466072E6821086B3823CB91A9FED034534781492E4B8EEAD21D4E6D365FE45D1C79554A2A72441328621D336A7BC284946AD531847A6065A535571D14F44ED41 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF3FED46C3ACD6F73ED3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CFD84A3B58A8F4BCCC602CC612F54802370A39D97685009209CFB0AB8DFE761E97C2F598A3E54AB4511D9D8FAF50ED830B6DC22B4C0AAAC09AC126D84212B092F63A54771ED8825433983AD880C8D3B7BB02C26D483E81D6BE72B480F99247062FEE42F474E8A1C6FD34D382445848F2F3 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2bioj2j9vV9f5a3t/obBCAdZ/Nw== X-Mailru-Sender: 9EB879F2C80682A09F26F806C7394981A1FC0BF4BF26A8A1D4570605F44DF537A9F2889ECAC8CD7833DAC8D12F5BC5EB2C62728BC403A049225EC17F3711B6CF1A6F2E8989E84EC137BFB0221605B344978139F6FA5A77F05FEEDEB644C299C0ED14614B50AE0675 X-Mras: Ok X-7564579A: 78E4E2B564C1792B X-77F55803: 6242723A09DB00B438D8D16241E2C9674218E0EBCD2528CD2DC820544DB7BD83049FFFDB7839CE9E45E89A588AFC0705F3515FAC263D563A73EE7157A86EE01ACAEB7A96BA42A091 X-7FA49CB5: 0D63561A33F958A587CD5281A4328B6C01644FE7694DEEE86A9E91CD71AB9B938941B15DA834481FA18204E546F3947CD6760E474F0469B4F6B57BC7E64490618DEB871D839B7333395957E7521B51C2DFABB839C843B9C08941B15DA834481F8AA50765F790063792238A98CB01235D389733CBF5DBD5E9B5C8C57E37DE458BD96E472CDF7238E0725E5C173C3A84C3777F8C72A04D893B35872C767BF85DA2F004C90652538430E4A6367B16DE6309 X-87b9d050: 1 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2bioj2j9vV9f5a3urlPYivLNJIw== X-Mailru-MI: 8000000000000800 X-Mras: Ok Add support to the SM8475 display clock controller by extending the SM8450 display clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov --- drivers/clk/qcom/Kconfig | 2 +- drivers/clk/qcom/dispcc-sm8450.c | 49 ++++++++++++++++++++++++++++++-- 2 files changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index decb41c4a58e..702de741cedd 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -924,7 +924,7 @@ config SM_DISPCC_8450 depends on SM_GCC_8450 help Support for the display clock controller on Qualcomm Technologies, Inc - SM8450 devices. + SM8450 or SM8475 devices. Say Y if you want to support display devices and functionality such as splash screen. diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index d1d3f60789ee..cef38cdd7318 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -75,7 +75,7 @@ static const struct pll_vco lucid_evo_vco[] = { { 249600000, 2000000000, 0 }, }; -static const struct alpha_pll_config disp_cc_pll0_config = { +static struct alpha_pll_config disp_cc_pll0_config = { .l = 0xD, .alpha = 0x6492, .config_ctl_val = 0x20485699, @@ -85,6 +85,15 @@ static const struct alpha_pll_config disp_cc_pll0_config = { .user_ctl_hi_val = 0x00000805, }; +static struct clk_init_data disp_cc_pll0_sm8475_init = { + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_reset_lucid_ole_ops, +}; + static struct clk_alpha_pll disp_cc_pll0 = { .offset = 0x0, .vco_table = lucid_evo_vco, @@ -102,7 +111,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { }, }; -static const struct alpha_pll_config disp_cc_pll1_config = { +static struct alpha_pll_config disp_cc_pll1_config = { .l = 0x1F, .alpha = 0x4000, .config_ctl_val = 0x20485699, @@ -112,6 +121,15 @@ static const struct alpha_pll_config disp_cc_pll1_config = { .user_ctl_hi_val = 0x00000805, }; +static struct clk_init_data disp_cc_pll1_sm8475_init = { + .name = "disp_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_reset_lucid_ole_ops, +}; + static struct clk_alpha_pll disp_cc_pll1 = { .offset = 0x1000, .vco_table = lucid_evo_vco, @@ -1746,6 +1764,7 @@ static struct qcom_cc_desc disp_cc_sm8450_desc = { static const struct of_device_id disp_cc_sm8450_match_table[] = { { .compatible = "qcom,sm8450-dispcc" }, + { .compatible = "qcom,sm8475-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table); @@ -1769,6 +1788,30 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev) goto err_put_rpm; } + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-dispcc")) { + /* Update DISPCC PLL0 Config */ + disp_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c; + disp_cc_pll0_config.test_ctl_val = 0x00000000; + disp_cc_pll0_config.test_ctl_hi_val = 0x00000003; + disp_cc_pll0_config.test_ctl_hi1_val = 0x00009000; + disp_cc_pll0_config.test_ctl_hi2_val = 0x00000034; + disp_cc_pll0_config.user_ctl_hi_val = 0x00000005; + + disp_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + disp_cc_pll0.clkr.hw.init = &disp_cc_pll0_sm8475_init; + + /* Update DISPCC PLL1 Config */ + disp_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c; + disp_cc_pll1_config.test_ctl_val = 0x00000000; + disp_cc_pll1_config.test_ctl_hi_val = 0x00000003; + disp_cc_pll1_config.test_ctl_hi1_val = 0x00009000; + disp_cc_pll1_config.test_ctl_hi2_val = 0x00000034; + disp_cc_pll1_config.user_ctl_hi_val = 0x00000005; + + disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + disp_cc_pll1.clkr.hw.init = &disp_cc_pll1_sm8475_init; + } + clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); @@ -1802,5 +1845,5 @@ static struct platform_driver disp_cc_sm8450_driver = { module_platform_driver(disp_cc_sm8450_driver); -MODULE_DESCRIPTION("QTI DISPCC SM8450 Driver"); +MODULE_DESCRIPTION("QTI DISPCC SM8450 / SM8475 Driver"); MODULE_LICENSE("GPL"); From patchwork Wed Jul 31 17:59:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Danila Tikhonov X-Patchwork-Id: 13749016 Received: from smtp50.i.mail.ru (smtp50.i.mail.ru [95.163.41.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB2723BBF2; Wed, 31 Jul 2024 17:59:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.163.41.92 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 31 Jul 2024 20:59:36 +0300 From: Danila Tikhonov To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, vkoul@kernel.org, vladimir.zapolskiy@linaro.org, quic_jkona@quicinc.com, dmitry.baryshkov@linaro.org, konradybcio@kernel.org, quic_tdas@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, Danila Tikhonov Subject: [PATCH 05/10] dt-bindings: clock: qcom,sm8450-gpucc: Add SM8475 GPUCC bindings Date: Wed, 31 Jul 2024 20:59:14 +0300 Message-ID: <20240731175919.20333-6-danila@jiaxyga.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731175919.20333-1-danila@jiaxyga.com> References: <20240731175919.20333-1-danila@jiaxyga.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Authentication-Results: exim-smtp-5c6c85c787-mv4xc; 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Update the documentation with the new compatible. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml | 3 +++ include/dt-bindings/clock/qcom,sm8475-gpucc.h | 1 + include/dt-bindings/reset/qcom,sm8475-gpucc.h | 1 + 3 files changed, 5 insertions(+) create mode 120000 include/dt-bindings/clock/qcom,sm8475-gpucc.h create mode 120000 include/dt-bindings/reset/qcom,sm8475-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index d10bb002906e..608fe63fb43a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -15,8 +15,10 @@ description: | See also:: include/dt-bindings/clock/qcom,sm8450-gpucc.h + include/dt-bindings/clock/qcom,sm8475-gpucc.h include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h + include/dt-bindings/reset/qcom,sm8475-gpucc.h include/dt-bindings/reset/qcom,sm8650-gpucc.h include/dt-bindings/reset/qcom,x1e80100-gpucc.h @@ -24,6 +26,7 @@ properties: compatible: enum: - qcom,sm8450-gpucc + - qcom,sm8475-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc - qcom,x1e80100-gpucc diff --git a/include/dt-bindings/clock/qcom,sm8475-gpucc.h b/include/dt-bindings/clock/qcom,sm8475-gpucc.h new file mode 120000 index 000000000000..2ba622290833 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8475-gpucc.h @@ -0,0 +1 @@ +qcom,sm8450-gpucc.h \ No newline at end of file diff --git a/include/dt-bindings/reset/qcom,sm8475-gpucc.h b/include/dt-bindings/reset/qcom,sm8475-gpucc.h new file mode 120000 index 000000000000..2ba622290833 --- /dev/null +++ b/include/dt-bindings/reset/qcom,sm8475-gpucc.h @@ -0,0 +1 @@ +qcom,sm8450-gpucc.h \ No newline at end of file From patchwork Wed Jul 31 17:59:15 2024 Content-Type: text/plain; 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bh=X8YgQ5A7zaABYlFnaxaSlD/KdyPUc1UxVaY40Dsr97w=; t=1722448791; x=1722538791; b=0gUjowLvcHizaVW67zlq0bfWfKS2uuhGEc5ibA83ajAS/xXu4tjZU6ZfdJqA7oSc6esN5wbDFT9 KoyJm/XtCVLrfog0Rp4NSPmADahpi+UWJd6wW+bZL/hA30SZu2e/27domVHS5JdAzoyCGZMvaXzXb OU/Rib8XXI0b4gd6stE=; Received: by exim-smtp-5c6c85c787-mv4xc with esmtpa (envelope-from ) id 1sZDbu-00000000IYY-0N7Z; Wed, 31 Jul 2024 20:59:38 +0300 From: Danila Tikhonov To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, vkoul@kernel.org, vladimir.zapolskiy@linaro.org, quic_jkona@quicinc.com, dmitry.baryshkov@linaro.org, konradybcio@kernel.org, quic_tdas@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, Danila Tikhonov Subject: [PATCH 06/10] clk: qcom: gpucc-sm8450: Add SM8475 support Date: Wed, 31 Jul 2024 20:59:15 +0300 Message-ID: <20240731175919.20333-7-danila@jiaxyga.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731175919.20333-1-danila@jiaxyga.com> References: <20240731175919.20333-1-danila@jiaxyga.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailru-Src: smtp X-4EC0790: 10 X-7564579A: B8F34718100C35BD X-77F55803: 4F1203BC0FB41BD926BB450FD17188A9239C2541717B5AEF810C4A468CE7865A182A05F5380850404A74BBC21EF8743C3DE06ABAFEAF6705FF2A0758AC8FB411F806485F292FBEEB53A4CEC99A690AFB X-7FA49CB5: FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE74BE895B46187343CEA1F7E6F0F101C67BD4B6F7A4D31EC0BCC500DACC3FED6E28638F802B75D45FF8AA50765F7900637E25DEE08FA4D750E8638F802B75D45FF36EB9D2243A4F8B5A6FCA7DBDB1FC311F39EFFDF887939037866D6147AF826D85D20E8AE10AE9B00995830582C796B1897466A5007D2FA65CC7F00164DA146DAFE8445B8C89999728AA50765F7900637F3E38EE449E3E2AE389733CBF5DBD5E9C8A9BA7A39EFB766F5D81C698A659EA7CC7F00164DA146DA9985D098DBDEAEC821E93C0F2A571C7BF6B57BC7E6449061A352F6E88A58FB86F5D81C698A659EA73AA81AA40904B5D9A18204E546F3947CDA7BFA4571439BB2AD7EC71F1DB884274AD6D5ED66289B523666184CF4C3C14F6136E347CC761E07725E5C173C3A84C30F1327A8DDF03E57BA3038C0950A5D36B5C8C57E37DE458B330BD67F2E7D9AF16D1867E19FE14079C09775C1D3CA48CFED8438A78DFE0A9E1DD303D21008E298D5E8D9A59859A8B6957A4DEDD2346B4275ECD9A6C639B01B78DA827A17800CE7CD707F342D9BDC98731C566533BA786AA5CC5B56E945C8DA X-C1DE0DAB: 0D63561A33F958A59F36C249BFBAC6B05002B1117B3ED696F577B21CE7AA68EB5D145BB8EF0DE66B823CB91A9FED034534781492E4B8EEAD2B25D9E4C92BC8ACC79554A2A72441328621D336A7BC284946AD531847A6065A535571D14F44ED41 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF3FED46C3ACD6F73ED3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CF105F4D36C92D6871B314A4C3F61D8D9ECF0BE80FB1C42A352728E3D7CFF502DA77ACD0092D6ACCC81D9D8FAF50ED830BCD6CCC40CCFF5B7CC126D84212B092F6E49EFAEB4BC0E7A2983AD880C8D3B7BB02C26D483E81D6BE72B480F99247062FEE42F474E8A1C6FD34D382445848F2F3 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2bioj2j9vV9f5a3uEdJbpDxMBfg== X-Mailru-Sender: 9EB879F2C80682A09F26F806C7394981A1FC0BF4BF26A8A1A7CF1FCFAF80C0E927534AC78082B92989820344C91CE3612C62728BC403A049225EC17F3711B6CF1A6F2E8989E84EC137BFB0221605B344978139F6FA5A77F05FEEDEB644C299C0ED14614B50AE0675 X-Mras: Ok X-7564579A: B8F34718100C35BD X-77F55803: 6242723A09DB00B438D8D16241E2C9674218E0EBCD2528CDC4E1543BC0AC038D049FFFDB7839CE9E45E89A588AFC0705D4A75EF7E7A86FF8252A7B132C6C7CCA1454DF3F5777FC7B X-7FA49CB5: 0D63561A33F958A55F9A416B69970837D0AF8B9838189D0CB3507DBD4F740AA28941B15DA834481FA18204E546F3947C02FF25FFE938E774F6B57BC7E64490618DEB871D839B7333395957E7521B51C2DFABB839C843B9C08941B15DA834481F8AA50765F7900637B286A8317E92A103389733CBF5DBD5E9B5C8C57E37DE458BD96E472CDF7238E0725E5C173C3A84C393E899A2A207F19735872C767BF85DA2F004C90652538430E4A6367B16DE6309 X-87b9d050: 1 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2bioj2j9vV9f5a3sI6uueFRfwvA== X-Mailru-MI: 8000000000000800 X-Mras: Ok Add support to the SM8475 graphics clock controller by extending the SM8450 graphics clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov --- drivers/clk/qcom/Kconfig | 3 ++- drivers/clk/qcom/gpucc-sm8450.c | 25 ++++++++++++++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 702de741cedd..eb2c8db95daf 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1123,7 +1123,8 @@ config SM_GPUCC_8450 depends on ARM64 || COMPILE_TEST select SM_GCC_8450 help - Support for the graphics clock controller on SM8450 devices. + Support for the graphics clock controller on SM8450 or SM8475 + devices. Say Y if you want to support graphics controller devices and functionality such as 3D graphics. diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c index b3c5d6923cd2..35ebf93fdb66 100644 --- a/drivers/clk/qcom/gpucc-sm8450.c +++ b/drivers/clk/qcom/gpucc-sm8450.c @@ -736,6 +736,7 @@ static const struct qcom_cc_desc gpu_cc_sm8450_desc = { static const struct of_device_id gpu_cc_sm8450_match_table[] = { { .compatible = "qcom,sm8450-gpucc" }, + { .compatible = "qcom,sm8475-gpucc" }, { } }; MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table); @@ -748,6 +749,28 @@ static int gpu_cc_sm8450_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gpucc")) { + /* Update GPUCC PLL0 Config */ + gpu_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c; + gpu_cc_pll0_config.test_ctl_val = 0x00000000; + gpu_cc_pll0_config.test_ctl_hi_val = 0x00000003; + gpu_cc_pll0_config.test_ctl_hi1_val = 0x00009000; + gpu_cc_pll0_config.test_ctl_hi2_val = 0x00000034; + gpu_cc_pll0_config.user_ctl_hi_val = 0x00000005; + + gpu_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + /* Update GPUCC PLL1 Config */ + gpu_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c; + gpu_cc_pll1_config.test_ctl_val = 0x00000000; + gpu_cc_pll1_config.test_ctl_hi_val = 0x00000003; + gpu_cc_pll1_config.test_ctl_hi1_val = 0x00009000; + gpu_cc_pll1_config.test_ctl_hi2_val = 0x00000034; + gpu_cc_pll1_config.user_ctl_hi_val = 0x00000005; + + gpu_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + } + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); @@ -763,5 +786,5 @@ static struct platform_driver gpu_cc_sm8450_driver = { }; module_platform_driver(gpu_cc_sm8450_driver); -MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver"); +MODULE_DESCRIPTION("QTI GPU_CC SM8450 / SM8475 Driver"); MODULE_LICENSE("GPL"); From patchwork Wed Jul 31 17:59:16 2024 Content-Type: text/plain; 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Update the documentation with the new compatible. Signed-off-by: Danila Tikhonov --- .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 2 ++ include/dt-bindings/clock/qcom,sm8475-videocc.h | 1 + 2 files changed, 3 insertions(+) create mode 120000 include/dt-bindings/clock/qcom,sm8475-videocc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index b2792b4bb554..9186d2ee87f8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -16,12 +16,14 @@ description: | See also: include/dt-bindings/clock/qcom,sm8450-videocc.h + include/dt-bindings/clock/qcom,sm8475-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h properties: compatible: enum: - qcom,sm8450-videocc + - qcom,sm8475-videocc - qcom,sm8550-videocc - qcom,sm8650-videocc diff --git a/include/dt-bindings/clock/qcom,sm8475-videocc.h b/include/dt-bindings/clock/qcom,sm8475-videocc.h new file mode 120000 index 000000000000..231cd153052c --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8475-videocc.h @@ -0,0 +1 @@ +qcom,sm8450-videocc.h \ No newline at end of file From patchwork Wed Jul 31 17:59:17 2024 Content-Type: text/plain; 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bh=AxpJ3uwTGNq14RStEKHgWF/Zndvnhh1RfoPtq3cN9tc=; t=1722448797; x=1722538797; b=W/WaJfiAo6p1Z0amT9EYWYyMlNDKUIwOyEFFUZYXdt7S2ycuVTIkrBi5Fl8GQ5TQ9J7Olk03D6l /JRqXtGq4vMWnsfhhMxp7LLOtRdBP6GDmgy9KOjKX7HPzjsnhjFXXUD8xy4J+t+e+Muo29u/bxxDd 2pX112jJOLtPy3Sas6U=; Received: by exim-smtp-5c6c85c787-mv4xc with esmtpa (envelope-from ) id 1sZDby-00000000IYY-2btz; Wed, 31 Jul 2024 20:59:42 +0300 From: Danila Tikhonov To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, vkoul@kernel.org, vladimir.zapolskiy@linaro.org, quic_jkona@quicinc.com, dmitry.baryshkov@linaro.org, konradybcio@kernel.org, quic_tdas@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, Danila Tikhonov Subject: [PATCH 08/10] clk: qcom: videocc-sm8450: Add SM8475 support Date: Wed, 31 Jul 2024 20:59:17 +0300 Message-ID: <20240731175919.20333-9-danila@jiaxyga.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731175919.20333-1-danila@jiaxyga.com> References: <20240731175919.20333-1-danila@jiaxyga.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailru-Src: smtp X-4EC0790: 10 X-7564579A: B8F34718100C35BD X-77F55803: 4F1203BC0FB41BD926BB450FD17188A9239C2541717B5AEF810C4A468CE7865A182A05F538085040048EAB2F9C24DBB53DE06ABAFEAF6705E0F3965BEAF8EBF0F806485F292FBEEB16538BC1624513DC X-7FA49CB5: FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE771540F9ECFC94C4BEA1F7E6F0F101C67BD4B6F7A4D31EC0BCC500DACC3FED6E28638F802B75D45FF8AA50765F790063716A4A39B750036BB8638F802B75D45FF36EB9D2243A4F8B5A6FCA7DBDB1FC311F39EFFDF887939037866D6147AF826D862A5491648FEC983995830582C796B18BB16BFAEA554FF3DCC7F00164DA146DAFE8445B8C89999728AA50765F7900637DCE3DBD6F8E38AFD389733CBF5DBD5E9C8A9BA7A39EFB766F5D81C698A659EA7CC7F00164DA146DA9985D098DBDEAEC821E93C0F2A571C7BF6B57BC7E6449061A352F6E88A58FB86F5D81C698A659EA73AA81AA40904B5D9A18204E546F3947CDA7BFA4571439BB2C0837EA9F3D197644AD6D5ED66289B523666184CF4C3C14F6136E347CC761E07725E5C173C3A84C3E43D663FACA9F152BA3038C0950A5D36B5C8C57E37DE458B330BD67F2E7D9AF16D1867E19FE14079C09775C1D3CA48CFED8438A78DFE0A9E1DD303D21008E298D5E8D9A59859A8B6957A4DEDD2346B4275ECD9A6C639B01B78DA827A17800CE7CD707F342D9BDC98731C566533BA786AA5CC5B56E945C8DA X-C1DE0DAB: 0D63561A33F958A587CD5281A4328B6C5002B1117B3ED696FCEE7DBDAAD95236F5FEB6EB1EB183FD823CB91A9FED034534781492E4B8EEAD003C2D46C52F18F2C79554A2A72441328621D336A7BC284946AD531847A6065A535571D14F44ED41 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF3FED46C3ACD6F73ED3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CF59C1C708A8BAD02C35B649C4129B82008394AC1A9CB4B3062B46D337FC50033A673DC415E80A8BD91D9D8FAF50ED830BA1583D508140B86BC126D84212B092F64B67D54C3C1649A8983AD880C8D3B7BB02C26D483E81D6BE72B480F99247062FEE42F474E8A1C6FD34D382445848F2F3 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2bioj2j9vV9f5a3tsvHFa7wRyzQ== X-Mailru-Sender: 9EB879F2C80682A09F26F806C7394981A1FC0BF4BF26A8A10B9BF4F79351F757FB1B413D279FBA4A1D6F5243312F17222C62728BC403A049225EC17F3711B6CF1A6F2E8989E84EC137BFB0221605B344978139F6FA5A77F05FEEDEB644C299C0ED14614B50AE0675 X-Mras: Ok X-7564579A: 78E4E2B564C1792B X-77F55803: 6242723A09DB00B438D8D16241E2C9674218E0EBCD2528CD2DC820544DB7BD83049FFFDB7839CE9E45E89A588AFC0705ABB767D8160287041B39F60525B4706617DD740B0BCDD1BA X-7FA49CB5: 0D63561A33F958A5AE041C50731737CA729C713A950B45EFF891C3E255CC68B18941B15DA834481FA18204E546F3947C629BAC65E8BCEBC0F6B57BC7E64490618DEB871D839B7333395957E7521B51C2DFABB839C843B9C08941B15DA834481F8AA50765F7900637EDB6B411A17B440E389733CBF5DBD5E9B5C8C57E37DE458BD96E472CDF7238E0725E5C173C3A84C393E899A2A207F19735872C767BF85DA2F004C90652538430E4A6367B16DE6309 X-87b9d050: 1 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2bioj2j9vV9f5a3vqKsfDj1WTyw== X-Mailru-MI: 8000000000000800 X-Mras: Ok Add support to the SM8475 video clock controller by extending the SM8450 video clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov --- drivers/clk/qcom/Kconfig | 2 +- drivers/clk/qcom/videocc-sm8450.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index eb2c8db95daf..60e70bf69cb9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1258,7 +1258,7 @@ config SM_VIDEOCC_8450 select QCOM_GDSC help Support for the video clock controller on Qualcomm Technologies, Inc. - SM8450 devices. + SM8450 or SM8475 devices. Say Y if you want to support video devices and functionality such as video encode/decode. endif diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index ed9163d64244..14d18e73332e 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -35,7 +35,7 @@ static const struct pll_vco lucid_evo_vco[] = { { 249600000, 2020000000, 0 }, }; -static const struct alpha_pll_config video_cc_pll0_config = { +static struct alpha_pll_config video_cc_pll0_config = { /* .l includes CAL_L_VAL, L_VAL fields */ .l = 0x0044001e, .alpha = 0x0, @@ -63,7 +63,7 @@ static struct clk_alpha_pll video_cc_pll0 = { }, }; -static const struct alpha_pll_config video_cc_pll1_config = { +static struct alpha_pll_config video_cc_pll1_config = { /* .l includes CAL_L_VAL, L_VAL fields */ .l = 0x0044002b, .alpha = 0xc000, @@ -397,6 +397,7 @@ static struct qcom_cc_desc video_cc_sm8450_desc = { static const struct of_device_id video_cc_sm8450_match_table[] = { { .compatible = "qcom,sm8450-videocc" }, + { .compatible = "qcom,sm8475-videocc" }, { } }; MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table); @@ -420,6 +421,30 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) return PTR_ERR(regmap); } + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) { + /* Update VideoCC PLL0 Config */ + video_cc_pll0_config.l = 0x1e; + video_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c; + video_cc_pll0_config.test_ctl_val = 0x00000000; + video_cc_pll0_config.test_ctl_hi_val = 0x00000003; + video_cc_pll0_config.test_ctl_hi1_val = 0x00009000; + video_cc_pll0_config.test_ctl_hi2_val = 0x00000034; + video_cc_pll0_config.user_ctl_hi_val = 0x00000005; + + video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + /* Update VideoCC PLL1 Config */ + video_cc_pll1_config.l = 0x2b; + video_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c; + video_cc_pll1_config.test_ctl_val = 0x00000000; + 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Update the documentation with the new compatible. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 2 ++ include/dt-bindings/clock/qcom,sm8475-camcc.h | 1 + 2 files changed, 3 insertions(+) create mode 120000 include/dt-bindings/clock/qcom,sm8475-camcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index f58edfc10f4c..2dea246882c3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -17,6 +17,7 @@ description: | See also: include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h + include/dt-bindings/clock/qcom,sm8475-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sm8650-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h @@ -29,6 +30,7 @@ properties: enum: - qcom,sc8280xp-camcc - qcom,sm8450-camcc + - qcom,sm8475-camcc - qcom,sm8550-camcc - qcom,sm8650-camcc - qcom,x1e80100-camcc diff --git a/include/dt-bindings/clock/qcom,sm8475-camcc.h b/include/dt-bindings/clock/qcom,sm8475-camcc.h new file mode 120000 index 000000000000..45444160d465 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8475-camcc.h @@ -0,0 +1 @@ +qcom,sm8450-camcc.h \ No newline at end of file From patchwork Wed Jul 31 17:59:19 2024 Content-Type: text/plain; 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bh=U3NoS7FPD22Ooolh9nIA4bbxpKQIdS35sANdBmC+rw0=; t=1722448801; x=1722538801; b=MJjdudVERCPkrtGAzJlfs63D2F9hK7plmJjIQ00sP5z0oKKYhwA3x+mEZdzoydWzvRiQNx0FYFP jejn846+Mni8RuAz9Quimn5o75Eu/iGcObpen+dxqR9KIbO6+iOpJckTjDlaTzcfCnTRi1fIteA9r BGlsOLfgYqhq8XSeG1c=; Received: by exim-smtp-5c6c85c787-mv4xc with esmtpa (envelope-from ) id 1sZDc3-00000000IYY-1cMu; Wed, 31 Jul 2024 20:59:48 +0300 From: Danila Tikhonov To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, vkoul@kernel.org, vladimir.zapolskiy@linaro.org, quic_jkona@quicinc.com, dmitry.baryshkov@linaro.org, konradybcio@kernel.org, quic_tdas@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, Danila Tikhonov Subject: [PATCH 10/10] clk: qcom: camcc-sm8450: Add SM8475 support Date: Wed, 31 Jul 2024 20:59:19 +0300 Message-ID: <20240731175919.20333-11-danila@jiaxyga.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731175919.20333-1-danila@jiaxyga.com> References: <20240731175919.20333-1-danila@jiaxyga.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailru-Src: smtp X-4EC0790: 10 X-7564579A: B8F34718100C35BD X-77F55803: 4F1203BC0FB41BD926BB450FD17188A9D748797E4778289DF1EEB2AE45DEEA42182A05F53808504091404AB2FF0B53CD3DE06ABAFEAF67059B20A077E21CE35DF806485F292FBEEBC1B496903CC57CC2 X-7FA49CB5: FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE7EED5D2FAB4CEB1EDEA1F7E6F0F101C67BD4B6F7A4D31EC0BCC500DACC3FED6E28638F802B75D45FF8AA50765F7900637C8DFB935205A313D8638F802B75D45FF36EB9D2243A4F8B5A6FCA7DBDB1FC311F39EFFDF887939037866D6147AF826D89CF5FE640F57405D995830582C796B18C1F1DE060261E832CC7F00164DA146DAFE8445B8C89999728AA50765F7900637A359038F01FFAF82389733CBF5DBD5E9C8A9BA7A39EFB766F5D81C698A659EA7CC7F00164DA146DA9985D098DBDEAEC8C2B5EEE3591E0D35F6B57BC7E6449061A352F6E88A58FB86F5D81C698A659EA73AA81AA40904B5D9A18204E546F3947C6089696B24BB1D19BA3038C0950A5D36C8A9BA7A39EFB766D91E3A1F190DE8FDBA3038C0950A5D36D5E8D9A59859A8B68BFD6B1B042489AC3AA81AA40904B5D99C9F4D5AE37F343AD1F44FA8B9022EA23BBE47FD9DD3FB595F5C1EE8F4F765FC2EE5AD8F952D28FBE2021AF6380DFAD18AA50765F7900637B8FA30D9455089A722CA9DD8327EE4930A3850AC1BE2E735F3CCD8A865B74A75C4224003CC83647689D4C264860C145E X-C1DE0DAB: 0D63561A33F958A5FF26F3A4B57F82FA5002B1117B3ED696666B84C65C4C62A3C81EEE05487B0209823CB91A9FED034534781492E4B8EEAD577AE849BCD98940C79554A2A72441328621D336A7BC284946AD531847A6065A535571D14F44ED41 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF3FED46C3ACD6F73ED3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CFAA21A0A2EF2E35251D9401D16A2CB4B31FC9AAD5CC50067167BF0C7A4DB2496A4D6C1B221ADCA6641D9D8FAF50ED830B6DB71DC97271B727C126D84212B092F6383893F97A2511FF983AD880C8D3B7BB02C26D483E81D6BE72B480F99247062FEE42F474E8A1C6FD34D382445848F2F3 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2bioj2j9vV9f5a3uGZjSO5I5RbQ== X-Mailru-Sender: 9EB879F2C80682A09F26F806C7394981F091418BA14BADF057FFD5DAF71AD12CB9B3AF8CF4CE49CE9E368351EECC161E2C62728BC403A049225EC17F3711B6CF1A6F2E8989E84EC137BFB0221605B344978139F6FA5A77F05FEEDEB644C299C0ED14614B50AE0675 X-Mras: Ok X-7564579A: B8F34718100C35BD X-77F55803: 6242723A09DB00B438D8D16241E2C9674218E0EBCD2528CDD20AB09974864291049FFFDB7839CE9E45E89A588AFC070551325792C209612A3014ADDCE96807A370E3BEDF0E22E033 X-7FA49CB5: 0D63561A33F958A516EB33383EDD5B989755A23C6F01BD97751EB1A5A3E80F088941B15DA834481FA18204E546F3947CAD0E433DBF1FBFA3F6B57BC7E64490618DEB871D839B7333395957E7521B51C2DFABB839C843B9C08941B15DA834481F8AA50765F79006373E1F328EEA58DAAF389733CBF5DBD5E9B5C8C57E37DE458BD96E472CDF7238E0725E5C173C3A84C393E899A2A207F19735872C767BF85DA2F004C90652538430E4A6367B16DE6309 X-87b9d050: 1 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2bioj2j9vV9f5a3sWgHnhmgItcA== X-Mailru-MI: 8000000000000800 X-Mras: Ok Add support to the SM8475 camera clock controller by extending the SM8450 camera clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov --- drivers/clk/qcom/Kconfig | 2 +- drivers/clk/qcom/camcc-sm8450.c | 231 ++++++++++++++++++++++++++++++-- 2 files changed, 222 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 60e70bf69cb9..7a5d47019a45 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -839,7 +839,7 @@ config SM_CAMCC_8450 depends on ARM64 || COMPILE_TEST select SM_GCC_8450 help - Support for the camera clock controller on SM8450 devices. + Support for the camera clock controller on SM8450 or SM8475 devices. Say Y if you want to support camera devices and camera functionality. config SM_CAMCC_8550 diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c index 26b78eed15ef..75af91fc160f 100644 --- a/drivers/clk/qcom/camcc-sm8450.c +++ b/drivers/clk/qcom/camcc-sm8450.c @@ -54,9 +54,13 @@ static const struct pll_vco rivian_evo_vco[] = { { 864000000, 1056000000, 0 }, }; +static const struct pll_vco rivian_ole_vco[] = { + { 864000000, 1075000000, 0 }, +}; + static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO }; -static const struct alpha_pll_config cam_cc_pll0_config = { +static struct alpha_pll_config cam_cc_pll0_config = { .l = 0x3e, .alpha = 0x8000, .config_ctl_val = 0x20485699, @@ -86,6 +90,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll0_out_even_sm8475_init = { + .name = "cam_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { .offset = 0x0, .post_div_shift = 10, @@ -109,6 +123,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { { } }; +static struct clk_init_data cam_cc_pll0_out_odd_sm8475_init = { + .name = "cam_cc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { .offset = 0x0, .post_div_shift = 14, @@ -127,7 +151,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { }, }; -static const struct alpha_pll_config cam_cc_pll1_config = { +static struct alpha_pll_config cam_cc_pll1_config = { .l = 0x25, .alpha = 0xeaaa, .config_ctl_val = 0x20485699, @@ -157,6 +181,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll1_out_even_sm8475_init = { + .name = "cam_cc_pll1_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { .offset = 0x1000, .post_div_shift = 10, @@ -175,7 +209,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll2_config = { +static struct alpha_pll_config cam_cc_pll2_config = { .l = 0x32, .alpha = 0x0, .config_ctl_val = 0x90008820, @@ -198,7 +232,7 @@ static struct clk_alpha_pll cam_cc_pll2 = { }, }; -static const struct alpha_pll_config cam_cc_pll3_config = { +static struct alpha_pll_config cam_cc_pll3_config = { .l = 0x2d, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -228,6 +262,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll3_out_even_sm8475_init = { + .name = "cam_cc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { .offset = 0x3000, .post_div_shift = 10, @@ -246,7 +290,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll4_config = { +static struct alpha_pll_config cam_cc_pll4_config = { .l = 0x2d, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -276,6 +320,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll4_out_even_sm8475_init = { + .name = "cam_cc_pll4_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { .offset = 0x4000, .post_div_shift = 10, @@ -294,7 +348,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll5_config = { +static struct alpha_pll_config cam_cc_pll5_config = { .l = 0x2d, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -324,6 +378,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll5_out_even_sm8475_init = { + .name = "cam_cc_pll5_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { .offset = 0x5000, .post_div_shift = 10, @@ -342,7 +406,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll6_config = { +static struct alpha_pll_config cam_cc_pll6_config = { .l = 0x2d, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -372,6 +436,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll6_out_even_sm8475_init = { + .name = "cam_cc_pll6_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { .offset = 0x6000, .post_div_shift = 10, @@ -390,7 +464,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll7_config = { +static struct alpha_pll_config cam_cc_pll7_config = { .l = 0x2d, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -420,6 +494,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll7_out_even_sm8475_init = { + .name = "cam_cc_pll7_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll7.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { .offset = 0x7000, .post_div_shift = 10, @@ -438,7 +522,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll8_config = { +static struct alpha_pll_config cam_cc_pll8_config = { .l = 0x32, .alpha = 0x0, .config_ctl_val = 0x20485699, @@ -468,6 +552,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { { } }; +static struct clk_init_data cam_cc_pll8_out_even_sm8475_init = { + .name = "cam_cc_pll8_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll8.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { .offset = 0x8000, .post_div_shift = 10, @@ -2817,6 +2911,7 @@ static const struct qcom_cc_desc cam_cc_sm8450_desc = { static const struct of_device_id cam_cc_sm8450_match_table[] = { { .compatible = "qcom,sm8450-camcc" }, + { .compatible = "qcom,sm8475-camcc" }, { } }; MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table); @@ -2829,6 +2924,122 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) { + /* Update CAMCC PLL0 Config */ + cam_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll0_config.test_ctl_val = 0x00000000; + cam_cc_pll0_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll0_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll0_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll0_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll0_out_even.clkr.hw.init = &cam_cc_pll0_out_even_sm8475_init; + cam_cc_pll0_out_odd.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll0_out_odd.clkr.hw.init = &cam_cc_pll0_out_odd_sm8475_init; + + /* Update CAMCC PLL1 Config */ + cam_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll1_config.test_ctl_val = 0x00000000; + cam_cc_pll1_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll1_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll1_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll1_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll1_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll1_out_even.clkr.hw.init = &cam_cc_pll1_out_even_sm8475_init; + + /* Update CAMCC PLL2 Config */ + cam_cc_pll2_config.config_ctl_val = 0x10000030; + cam_cc_pll2_config.config_ctl_hi_val = 0x80890263; + cam_cc_pll2_config.user_ctl_val = 0x00000001; + cam_cc_pll2_config.user_ctl_hi_val = 0x00000000; + + cam_cc_pll2.vco_table = rivian_ole_vco; + + /* Update CAMCC PLL3 Config */ + cam_cc_pll3_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll3_config.test_ctl_val = 0x00000000; + cam_cc_pll3_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll3_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll3_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll3_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll3.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll3_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll3_out_even.clkr.hw.init = &cam_cc_pll3_out_even_sm8475_init; + + /* Update CAMCC PLL4 Config */ + cam_cc_pll4_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll4_config.test_ctl_val = 0x00000000; + cam_cc_pll4_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll4_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll4_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll4_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll4_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll4_out_even.clkr.hw.init = &cam_cc_pll4_out_even_sm8475_init; + + /* Update CAMCC PLL5 Config */ + cam_cc_pll5_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll5_config.test_ctl_val = 0x00000000; + cam_cc_pll5_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll5_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll5_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll5_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll5.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll5_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll5_out_even.clkr.hw.init = &cam_cc_pll5_out_even_sm8475_init; + + /* Update CAMCC PLL6 Config */ + cam_cc_pll6_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll6_config.test_ctl_val = 0x00000000; + cam_cc_pll6_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll6_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll6_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll6_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll6.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll6_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll6_out_even.clkr.hw.init = &cam_cc_pll6_out_even_sm8475_init; + + /* Update CAMCC PLL7 Config */ + cam_cc_pll7_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll7_config.test_ctl_val = 0x00000000; + cam_cc_pll7_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll7_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll7_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll7_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll7.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll7_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll7_out_even.clkr.hw.init = &cam_cc_pll7_out_even_sm8475_init; + + /* Update CAMCC PLL8 Config */ + cam_cc_pll8_config.config_ctl_hi1_val = 0x82aa299c; + cam_cc_pll8_config.test_ctl_val = 0x00000000; + cam_cc_pll8_config.test_ctl_hi_val = 0x00000003; + cam_cc_pll8_config.test_ctl_hi1_val = 0x00009000; + cam_cc_pll8_config.test_ctl_hi2_val = 0x00000034; + cam_cc_pll8_config.user_ctl_hi_val = 0x00000005; + + cam_cc_pll8.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + + cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll8_out_even.clkr.hw.init = &cam_cc_pll8_out_even_sm8475_init; + } + clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); @@ -2852,5 +3063,5 @@ static struct platform_driver cam_cc_sm8450_driver = { module_platform_driver(cam_cc_sm8450_driver); -MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver"); +MODULE_DESCRIPTION("QCOM CAMCC SM8450 / SM8475 Driver"); MODULE_LICENSE("GPL");