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Mon, 04 Mar 2019 15:28:07 -0800 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1h0x06-00079T-19; Mon, 04 Mar 2019 15:28:02 -0800 Received: from xsj-pvapsmtp01 (xsj-smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x24NRq5U030278; Mon, 4 Mar 2019 15:27:52 -0800 Received: from [172.19.2.91] (helo=xsjjollys50.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1h0wzw-00077M-Gg; Mon, 04 Mar 2019 15:27:52 -0800 From: Jolly Shah To: , , , CC: , , , Rajan Vaja , Jolly Shah Subject: [PATCH] drivers: clk: zynqmp: Allow zero divisor value Date: Mon, 4 Mar 2019 15:27:46 -0800 Message-ID: <1551742066-10825-1-git-send-email-jollys@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(39860400002)(396003)(136003)(346002)(376002)(2980300002)(189003)(199004)(2201001)(106466001)(4326008)(50466002)(9786002)(26005)(47776003)(77096007)(356004)(48376002)(44832011)(110136005)(54906003)(2616005)(50226002)(6666004)(486006)(126002)(476003)(106002)(36386004)(16586007)(63266004)(316002)(336012)(51416003)(305945005)(7696005)(426003)(4744005)(107886003)(478600001)(2906002)(8936002)(186003)(72206003)(8676002)(81156014)(81166006)(5660300002)(36756003)(107986001)(5001870100001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR02MB4224;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com;MX:1;A:1; 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Allow zero divisor when CLK_DIVIDER_ALLOW_ZERO for the clock is set. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah --- drivers/clk/zynqmp/divider.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index a371c66..e146b6f 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -76,6 +76,13 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, else value = div >> 16; + if (!value) { + WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), + "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", + clk_name); + return parent_rate; + } + return DIV_ROUND_UP_ULL(parent_rate, value); }