From patchwork Mon Aug 5 09:17:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13753291 Received: from mail-oo1-f43.google.com (mail-oo1-f43.google.com [209.85.161.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22E173BB48; Mon, 5 Aug 2024 09:17:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849451; cv=none; b=QtJe7DEXBqGrcI9S+nKxW6j6Khc97gVwYly4UQZxKvA9WGJeHmIwVLogTR6GqeBQbajPsQce7HvswBUlglV2YOrVzS27t1E028J9o7zPApKBDUs1tSfLgmmouiQZ3oRL//8dHadu8MQGq/LfFz/MtMoTHviF2npnGY/cXtueGiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849451; c=relaxed/simple; bh=gRISN6VGNF9/g5MWQMWyS15u9A1X4YCJbdBU/quLlAc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=F3GQJaQpSnD7+RHw6qIsOCvMDbdKBf8UFQjiC8ltfhd8t775+7bLIBvQ4WsotHPoDD7GZzh4Z/C/KNDC9+YixWqgrzlrV4KDZ9JLS3PDqpJM8LD6inxjamISYW22T19cOgnLd9TOnRxHuqN/M7oFDrjGs0wTERhwYiHPmgLB//c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UmAje5uj; arc=none smtp.client-ip=209.85.161.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UmAje5uj" Received: by mail-oo1-f43.google.com with SMTP id 006d021491bc7-5c667b28c82so2731078eaf.1; Mon, 05 Aug 2024 02:17:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722849449; x=1723454249; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mQqYFrR1LoRoAq9WMHUyKnpA+f/vebxojh36F6qI1pQ=; b=UmAje5ujoNdCyFsdFycxztSQJ4FqNIu+FjEWu+dPzz87yGC2rdgtuAYuIg/8hlvwIw 86Go2pDFurHraGbMsWtDizjVE4sL3qM59q582Xf/J+tIXleL6/oeVKEE9Wz8EMdbal87 cBgNanHq/bijE+ihOU8LCQILh2YCrEa5uyxm0ilaGSpAVMT420gwgcuEpOVzw1M5Zahd v3+E/ZIYmDlvgCmW7w0TaaVfBkdirUend0GfXq4LrWb07ZeKzvIh6o4YwflXJbr9wB8l WGzCKIrD5+8+V5iGaK0eAGLjG2UoJxuMOFrNtyjiCHCBAukmUarvt5MyN7K89spUrJqm 9Kyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722849449; x=1723454249; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mQqYFrR1LoRoAq9WMHUyKnpA+f/vebxojh36F6qI1pQ=; b=rZ1bmNjwOGhKSXaohspam95YeiztdPnhe7mt2Ah6DcGNV3H9Tl56lqPaNLoWyhH8MA hrbAj8pjS23caRsCIPogIA8tOnvwpvMYszujaA9KS5m41XQDyfVfZjCcwiuuIiJ1qd+f Awcb4ZBDNjxsYfA4BTA5/Ey6KZgl/hTZB7NkyATapqIrljT3nkWh7E6S3XouhzwhKssA vVvWx7uzVaVV4y+9dWFO6Q5m4hJpTVY0zVRrm3mYTNXd03uadxQytlh86iM3TJr/zgA0 t7xmGaElkO2fZygmRthjAeVkpBaWDlld05hyWW2BftWInJr3/omOUHKZpl+/yPtCzsZS JySg== X-Forwarded-Encrypted: i=1; AJvYcCXLA3F1fU578II5gCKiZDWn5peZOwccYPYE0jcqm/3+w7+8MAmUxbmCmYtRmsKz49yksa96ebLBMgE/xB/M/LgzUxGN75Vava5zU/4RFp4RG84mCQUmtycESSVdmLetVXeUcIhElB1RmwrQGtsFo29Ixqm5gzWM/o3HLOTixbj00B8p4g== X-Gm-Message-State: AOJu0YxiA/YNOMnhPP7YJahgHQrY6Ffx6xQTtF4qRW1WAbtqmiqqxS5y EhngrORJCfyTlMniJDpiR6heJ2H9q/mCZKlIeiQK4k8kPjnYtKTy X-Google-Smtp-Source: AGHT+IGCy+jdlK/J3lqkGlGo1ErX2mOA09jw089OryMpR/Vo8xZDbSFHm7BN15u6pLFZnwVwM21NYQ== X-Received: by 2002:a4a:e609:0:b0:5d8:a13:f99d with SMTP id 006d021491bc7-5d80a1411c3mr2590865eaf.1.1722849449035; Mon, 05 Aug 2024 02:17:29 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-70a31ec3713sm2973075a34.44.2024.08.05.02.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 02:17:28 -0700 (PDT) From: Chen Wang To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang , Drew Fustini Subject: [PATCH v6 1/8] mmc: sdhci-of-dwcmshc: add common bulk optional clocks support Date: Mon, 5 Aug 2024 17:17:21 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang In addition to the required core clock and optional bus clock, the soc will expand its own clocks, so the bulk clock mechanism is abstracted. Note, I call the bulk clocks as "other clocks" due to the bus clock has been called as "optional". Signed-off-by: Chen Wang Tested-by: Drew Fustini # TH1520 Tested-by: Inochi Amaoto # Duo and Huashan Pi Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-dwcmshc.c | 90 +++++++++++++++-------------- 1 file changed, 48 insertions(+), 42 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index e79aa4b3b6c3..35401616fb2e 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -108,7 +108,6 @@ #define DLL_LOCK_WO_TMOUT(x) \ ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) -#define RK35xx_MAX_CLKS 3 /* PHY register area pointer */ #define DWC_MSHC_PTR_PHY_R 0x300 @@ -199,23 +198,54 @@ enum dwcmshc_rk_type { }; struct rk35xx_priv { - /* Rockchip specified optional clocks */ - struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS]; struct reset_control *reset; enum dwcmshc_rk_type devtype; u8 txclk_tapnum; }; +#define DWCMSHC_MAX_OTHER_CLKS 3 + struct dwcmshc_priv { struct clk *bus_clk; int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */ int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */ + int num_other_clks; + struct clk_bulk_data other_clks[DWCMSHC_MAX_OTHER_CLKS]; + void *priv; /* pointer to SoC private stuff */ u16 delay_line; u16 flags; }; +static int dwcmshc_get_enable_other_clks(struct device *dev, + struct dwcmshc_priv *priv, + int num_clks, + const char * const clk_ids[]) +{ + int err; + + if (num_clks > DWCMSHC_MAX_OTHER_CLKS) + return -EINVAL; + + for (int i = 0; i < num_clks; i++) + priv->other_clks[i].id = clk_ids[i]; + + err = devm_clk_bulk_get_optional(dev, num_clks, priv->other_clks); + if (err) { + dev_err(dev, "failed to get clocks %d\n", err); + return err; + } + + err = clk_bulk_prepare_enable(num_clks, priv->other_clks); + if (err) + dev_err(dev, "failed to enable clocks %d\n", err); + + priv->num_other_clks = num_clks; + + return err; +} + /* * If DMA addr spans 128MB boundary, we split the DMA transfer into two * so that each DMA transfer doesn't exceed the boundary. @@ -1036,8 +1066,9 @@ static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device * static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) { - int err; + static const char * const clk_ids[] = {"axi", "block", "timer"}; struct rk35xx_priv *priv = dwc_priv->priv; + int err; priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); if (IS_ERR(priv->reset)) { @@ -1046,21 +1077,10 @@ static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc return err; } - priv->rockchip_clks[0].id = "axi"; - priv->rockchip_clks[1].id = "block"; - priv->rockchip_clks[2].id = "timer"; - err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS, - priv->rockchip_clks); - if (err) { - dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err); - return err; - } - - err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks); - if (err) { - dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err); + err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, + ARRAY_SIZE(clk_ids), clk_ids); + if (err) return err; - } if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", &priv->txclk_tapnum)) @@ -1280,9 +1300,7 @@ static int dwcmshc_probe(struct platform_device *pdev) err_clk: clk_disable_unprepare(pltfm_host->clk); clk_disable_unprepare(priv->bus_clk); - if (rk_priv) - clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, - rk_priv->rockchip_clks); + clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); free_pltfm: sdhci_pltfm_free(pdev); return err; @@ -1304,7 +1322,6 @@ static void dwcmshc_remove(struct platform_device *pdev) struct sdhci_host *host = platform_get_drvdata(pdev); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); - struct rk35xx_priv *rk_priv = priv->priv; pm_runtime_get_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); @@ -1316,9 +1333,7 @@ static void dwcmshc_remove(struct platform_device *pdev) clk_disable_unprepare(pltfm_host->clk); clk_disable_unprepare(priv->bus_clk); - if (rk_priv) - clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, - rk_priv->rockchip_clks); + clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); sdhci_pltfm_free(pdev); } @@ -1328,7 +1343,6 @@ static int dwcmshc_suspend(struct device *dev) struct sdhci_host *host = dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); - struct rk35xx_priv *rk_priv = priv->priv; int ret; pm_runtime_resume(dev); @@ -1347,9 +1361,7 @@ static int dwcmshc_suspend(struct device *dev) if (!IS_ERR(priv->bus_clk)) clk_disable_unprepare(priv->bus_clk); - if (rk_priv) - clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, - rk_priv->rockchip_clks); + clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); return ret; } @@ -1359,7 +1371,6 @@ static int dwcmshc_resume(struct device *dev) struct sdhci_host *host = dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); - struct rk35xx_priv *rk_priv = priv->priv; int ret; ret = clk_prepare_enable(pltfm_host->clk); @@ -1372,29 +1383,24 @@ static int dwcmshc_resume(struct device *dev) goto disable_clk; } - if (rk_priv) { - ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, - rk_priv->rockchip_clks); - if (ret) - goto disable_bus_clk; - } + ret = clk_bulk_prepare_enable(priv->num_other_clks, priv->other_clks); + if (ret) + goto disable_bus_clk; ret = sdhci_resume_host(host); if (ret) - goto disable_rockchip_clks; + goto disable_other_clks; if (host->mmc->caps2 & MMC_CAP2_CQE) { ret = cqhci_resume(host->mmc); if (ret) - goto disable_rockchip_clks; + goto disable_other_clks; } return 0; -disable_rockchip_clks: - if (rk_priv) - clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, - rk_priv->rockchip_clks); +disable_other_clks: + clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); disable_bus_clk: if (!IS_ERR(priv->bus_clk)) clk_disable_unprepare(priv->bus_clk); From patchwork Mon Aug 5 09:17:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13753292 Received: from mail-oo1-f41.google.com (mail-oo1-f41.google.com [209.85.161.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DBC414B972; Mon, 5 Aug 2024 09:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849471; cv=none; b=rV/IU9+AqrOiYL/mTd6VNouP1JC/2Uh5nvSIRv4ScwPCHst67Kahccr5PT5Z5GoTpBblRDg4ahK77gNZFV6OyHGrRzSkaOEDPMar40rU4d1ZkgJfi2nKtnJ4ro0YbbaCwG35cpmgP4eCmuzC8lnqJISaIAnzxEgypFdJnst6ZAE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849471; c=relaxed/simple; bh=1p/349K3IO1rk9ZoWOQeR3BQuqWpRESY7cifdcnU0ko=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LWU8wgz6LCpr2vAvgxs8xX5VOuEcbHupzWQSeN458z+4/ykWNkd/LWnRQd70zIsgSsj+jqJkqr4NgG1B7kkHH/TyR7Kjvs3YSPF4b2zJ1KMW4nNNSPrBiWzoMtf7DBkOoEYZN7P1b3njZGI6RJUgJTTvfycMs6+z14hnOJRqSIE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UuSeVEC2; arc=none smtp.client-ip=209.85.161.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UuSeVEC2" Received: by mail-oo1-f41.google.com with SMTP id 006d021491bc7-5d829d41a89so165603eaf.3; Mon, 05 Aug 2024 02:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722849469; x=1723454269; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q8k5uVQtfV8NUTOLFTh7RVXzJOtMU6EKEmam/qAPo2E=; b=UuSeVEC26hbdCI3YaMr/pcpc/Moej/FJCn++z7uSbVrmHvYld4agFksM0hyDctM1qz KQklwyCEhOAN9bvjtcCh32uItdiz9S9K7vrORj5Ggle57z+hz/4VWTgBusVBkknPOVwR wvXO8W8tukuZqK7j1QRTZMCz2GcQp/nIdS0YGDu1nrLOWfBcgld4ERb/Fu7/yC3aSXuu fjZJhEOIwj/wBbCFi1h8VDnXpr+hZUWR7QS/Wrsl4YSBbviKo1xJDl2hCP3KlbtKvuqe EmokYpAyiJsmSzJxsJgHzcbimT84NPQidDp0UbrX3M6cD4x8gDWWFT32sy31o5PJvgjb ugew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722849469; x=1723454269; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q8k5uVQtfV8NUTOLFTh7RVXzJOtMU6EKEmam/qAPo2E=; b=ZooGM20e10wujF0wJfdcWBmQeiTPgrTOD0yXFIN+zhj0mBaYfYlEazGygw069K/EFM HUA87X3e+VWX9TGw/hZJwUtMB0JfSztLCSGbl/9aL7tWCDibL6tSDfZvaxEi/kHh338L uw3IwrXgd3giIocXR0kEgQDNpOp6RcD5u4ScSmJqn1eCGZcQg2Atfb84E9lY8DJkFThP CnI3VE4k6XlqAx2N4KUsmqh5XUaUJC2fszhcbnm1gFKzzGTPghlHPUghlbKpNzKf94bs CAadP4TK0cZrwA4p/9YQN5Mua8TVVHRC7XB21jz5L36uPSnGnIyfvzpuVRhSYxmmvblN oi8Q== X-Forwarded-Encrypted: i=1; AJvYcCUtISmdLyEvG/TJXlBqBEat+TjolUXNq+/nLbO/Qgm/ahNbzZEZjK6h3xV7JSmwwSqbqZN5sbaXjAW61hP9khQkjbaoEtqkZNGU3wiXWInCb1HdLZ3xBeF/2DN5hUZPFZMoKAqehykojFoMpJRW4YUuNRSQDpQbeV1vkfwo2TUWMiPgRw== X-Gm-Message-State: AOJu0YyzA9u5malv2q2zUrFDDpnv6N6fs8Cb0913+3QG6VnQwqZJ+1hq NWzMDc/GnA2vEWLwnNVYrAJws59HhWJ4wMYtMpj39gWSdg/hyGAF X-Google-Smtp-Source: AGHT+IEIp8y7lLQIWcjPh7pCGQ/cek2Jyros8ijAp0OQXpassUcZ+4MW/h9yG7N6uQtXrGDYyEcl1w== X-Received: by 2002:a05:6820:4b0a:b0:5d8:ebe:23fb with SMTP id 006d021491bc7-5d80ebe26ffmr5871359eaf.7.1722849468666; Mon, 05 Aug 2024 02:17:48 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5d7478b084csm1882630eaf.0.2024.08.05.02.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 02:17:48 -0700 (PDT) From: Chen Wang To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang , Drew Fustini Subject: [PATCH v6 2/8] mmc: sdhci-of-dwcmshc: move two rk35xx functions Date: Mon, 5 Aug 2024 17:17:40 +0800 Message-Id: <54204702d5febd3e867eb3544c36919fe4140a88.1722847198.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang This patch just move dwcmshc_rk35xx_init() and dwcmshc_rk35xx_postinit() to put the functions of rk35xx together as much as possible. This change is an intermediate process before further modification. Signed-off-by: Chen Wang Tested-by: Drew Fustini # TH1520 Tested-by: Inochi Amaoto # Duo and Huashan Pi Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-dwcmshc.c | 90 ++++++++++++++--------------- 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 35401616fb2e..a002636d51fd 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -711,6 +711,51 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_reset(host, mask); } +static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) +{ + static const char * const clk_ids[] = {"axi", "block", "timer"}; + struct rk35xx_priv *priv = dwc_priv->priv; + int err; + + priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); + if (IS_ERR(priv->reset)) { + err = PTR_ERR(priv->reset); + dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); + return err; + } + + err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, + ARRAY_SIZE(clk_ids), clk_ids); + if (err) + return err; + + if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", + &priv->txclk_tapnum)) + priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; + + /* Disable cmd conflict check */ + sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); + /* Reset previous settings */ + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); + + return 0; +} + +static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) +{ + /* + * Don't support highspeed bus mode with low clk speed as we + * cannot use DLL for this condition. + */ + if (host->mmc->f_max <= 52000000) { + dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", + host->mmc->f_max); + host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); + host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); + } +} + static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -1064,51 +1109,6 @@ static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device * host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD); } -static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) -{ - static const char * const clk_ids[] = {"axi", "block", "timer"}; - struct rk35xx_priv *priv = dwc_priv->priv; - int err; - - priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); - if (IS_ERR(priv->reset)) { - err = PTR_ERR(priv->reset); - dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); - return err; - } - - err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, - ARRAY_SIZE(clk_ids), clk_ids); - if (err) - return err; - - if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", - &priv->txclk_tapnum)) - priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; - - /* Disable cmd conflict check */ - sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); - /* Reset previous settings */ - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); - - return 0; -} - -static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) -{ - /* - * Don't support highspeed bus mode with low clk speed as we - * cannot use DLL for this condition. - */ - if (host->mmc->f_max <= 52000000) { - dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", - host->mmc->f_max); - host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); - host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); - } -} - static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { { .compatible = "rockchip,rk3588-dwcmshc", From patchwork Mon Aug 5 09:17:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13753293 Received: from mail-oi1-f172.google.com (mail-oi1-f172.google.com [209.85.167.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F5D3139D12; Mon, 5 Aug 2024 09:18:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849489; cv=none; b=AI2mF0BVMO+k2GXrJ9f3fUvvwHNhrEbjyKGC5qEwwyXro1EA+4RQ+YDVfgmHi5zCXaa6jT79XA4hpZF7xcQNcRijBFClLH0r8nRzbCOJyT6Kl2heD9+kWnjX14M3T/LiDlLmvb4a6FnAkXUtuASCBhv9ghplLfbB5RKXW1dnz0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849489; c=relaxed/simple; bh=lhr4ycr5iT/HvMKPlMZc/xTGMersf1RPOPJHu8DVYIA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UKh96By/jlJV2TCcpM5u1bVY05lzyHkmovCv+IDy3VtgrRsZM9SBLaIqJoV3KvdH9JlumfLORoc2QkUNW7DSqJ20S1m6HRBdP+DeYk7W2/HxcD/PiP2YDCSw34NZs90QzRPPQ0awSlgVBpHxW6bCCZbRiK6JZ2helmzNxHr3AHo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=doxbNJAC; arc=none smtp.client-ip=209.85.167.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="doxbNJAC" Received: by mail-oi1-f172.google.com with SMTP id 5614622812f47-3db1bc36bc2so2553143b6e.0; Mon, 05 Aug 2024 02:18:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722849487; x=1723454287; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RfW+yJcH0UPgHr9h+kry6dKwgvMmuDMaA8IPcQFaE90=; b=doxbNJACTGQA88+rvsveK2bfVYqhuOseBk2a5k1PdOF6bejiUgVHCKESwY53dKgJJy grNZs6+FndTroQhcv6kdDWG+fPqOVqsgOS4doFVp3OoeVEzRHqRIgeKOdJ4uPjkJKiHU lcHe39k7bKVl32XaUurGMeOF1fMET1W5DfcbD31ZLvL+Nh/rJ6Gh7Z8l+s8PTcLt69ex AQDUQYj6RC1gzkjFCPslJf5qBB1BM5udL7wmW3+sKiKTiabVvpUQS637PQ4swZNRDh2p awjrrLnhOrJrHzV8cYDMkCRYhw9BzDNH3oTa2setwtuH/xy8ordzn4h+d7GGlX5rS9Y3 +MgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722849487; x=1723454287; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RfW+yJcH0UPgHr9h+kry6dKwgvMmuDMaA8IPcQFaE90=; b=RyOTeGggPvaouy8au/EBHJm52pgdBmgqGDlMaZxrn0gfEsppUb9jEgYEuoPCwkehpj cHcG6qL09odOpVv2mdnag+7kWIfrGbg/BqWGcxq5w5gj3otx51kbip9KYPzIkG+cE/Et VIT8NgXo3tjsaUOgDv8sflHnDgtQUU07ROF/Wn2fjQXLfwF2PFAAG6e28TkaGab6LWRp BJokYWht+G62eaiwKvvFPbMcSLE1+BF1T9yfbtXg18CwQjGP3Y349q4P3FVC1P6fCPRJ QwlWgndvGJqL5BeGxvExmd7gAg91DBdEm1hJG9q2uoS5P8TiPFkqXIQU+ltmYVVjaBa2 6wFA== X-Forwarded-Encrypted: i=1; AJvYcCVgoyORhcHiAdHv3KXiJp7oWLxZy+XoAkvPmZTkM+SSMxUQ05YCTPwcUgRIkFhehPglW6h6zKTLDVU5yfB9T2c1AGIhlFtNXc34yt40BWt8cK4kELu96RLSX9pXZbIjEEegnKsY9zx9lOPfFObzry653nrZ/I3FQn44GIjG7XF+4Voh7w== X-Gm-Message-State: AOJu0Yxl4bV9CFLsUnSngAKOuju9vkp5Ll1vEp6bgxkYn8SWAmn0djgG ma6cq0/5BLkKNL19CzpXGYQud3ZFLr3Qvzux5LzArIc50f+BcZgI X-Google-Smtp-Source: AGHT+IFbBF3lExmEwSsTcYdXzKwjXYiy2njdzQYc05gkHhL2aT6+SgSAyFcfMhbQrS/LyC+XIkUjzg== X-Received: by 2002:a05:6808:6091:b0:3db:2025:110 with SMTP id 5614622812f47-3db537ecc54mr4533948b6e.11.1722849487166; Mon, 05 Aug 2024 02:18:07 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3db56371007sm2520804b6e.17.2024.08.05.02.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 02:18:06 -0700 (PDT) From: Chen Wang To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang , Drew Fustini Subject: [PATCH v6 3/8] mmc: sdhci-of-dwcmshc: factor out code for th1520_init() Date: Mon, 5 Aug 2024 17:17:59 +0800 Message-Id: <23c6a81052a6dd3660d60348731229d60a209b32.1722847198.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Different socs have initialization operations in the probe process, which are summarized as functions. This patch first factor out init function for th1520. Signed-off-by: Chen Wang Reviewed-by: Drew Fustini Tested-by: Drew Fustini # TH1520 Tested-by: Inochi Amaoto # Duo and Huashan Pi Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-dwcmshc.c | 51 +++++++++++++++++------------ 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index a002636d51fd..b272ec2ab232 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -830,6 +830,35 @@ static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) } } +static int th1520_init(struct device *dev, + struct sdhci_host *host, + struct dwcmshc_priv *dwc_priv) +{ + dwc_priv->delay_line = PHY_SDCLKDL_DC_DEFAULT; + + if (device_property_read_bool(dev, "mmc-ddr-1_8v") || + device_property_read_bool(dev, "mmc-hs200-1_8v") || + device_property_read_bool(dev, "mmc-hs400-1_8v")) + dwc_priv->flags |= FLAG_IO_FIXED_1V8; + else + dwc_priv->flags &= ~FLAG_IO_FIXED_1V8; + + /* + * start_signal_voltage_switch() will try 3.3V first + * then 1.8V. Use SDHCI_SIGNALING_180 rather than + * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V + * in sdhci_start_signal_voltage_switch(). + */ + if (dwc_priv->flags & FLAG_IO_FIXED_1V8) { + host->flags &= ~SDHCI_SIGNALING_330; + host->flags |= SDHCI_SIGNALING_180; + } + + sdhci_enable_v4_mode(host); + + return 0; +} + static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -1231,27 +1260,7 @@ static int dwcmshc_probe(struct platform_device *pdev) } if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) { - priv->delay_line = PHY_SDCLKDL_DC_DEFAULT; - - if (device_property_read_bool(dev, "mmc-ddr-1_8v") || - device_property_read_bool(dev, "mmc-hs200-1_8v") || - device_property_read_bool(dev, "mmc-hs400-1_8v")) - priv->flags |= FLAG_IO_FIXED_1V8; - else - priv->flags &= ~FLAG_IO_FIXED_1V8; - - /* - * start_signal_voltage_switch() will try 3.3V first - * then 1.8V. Use SDHCI_SIGNALING_180 rather than - * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V - * in sdhci_start_signal_voltage_switch(). - */ - if (priv->flags & FLAG_IO_FIXED_1V8) { - host->flags &= ~SDHCI_SIGNALING_330; - host->flags |= SDHCI_SIGNALING_180; - } - - sdhci_enable_v4_mode(host); + th1520_init(dev, host, priv); } #ifdef CONFIG_ACPI From patchwork Mon Aug 5 09:18:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13753294 Received: from mail-oo1-f47.google.com (mail-oo1-f47.google.com [209.85.161.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0391F139D12; Mon, 5 Aug 2024 09:18:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849514; cv=none; b=MWJ7tfdxYCv0s/F2pKluSBrrezBwmEvseAAbJNbDKDHL0+ptiW1SnyG/AXu/vfyqLPxthB5S+zet2RKIuXVP5RAMLm/Wdzk7TZcw/HW7WvsE5wVTY5yNCeIh9yZFISUxS1huCXNGQCandOOSX6QInSRckZnTcUFnVpg0GBllz+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849514; c=relaxed/simple; bh=eTuZ+aHAhbkq+3UlCiBExwS6jgikSXjl2/uk3rc3Ps0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PTUsfQAJgFZsFztNf4HKK4+O2sA3S1nNiiQ68/9tdbEm7gPj19uIgczzBnWu9uyZ8fx11cGMdQiy83nAvDrRlmvx6SMApMN/0msMaxUUZRD7VyNwyPc0Te6TFxdQ6mrc4l7kuWdIa/GM040drzxvg+0wwIGEYSZAmJuMJwG0HpY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kI0cu6Re; arc=none smtp.client-ip=209.85.161.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kI0cu6Re" Received: by mail-oo1-f47.google.com with SMTP id 006d021491bc7-5d5de0e47b9so4283623eaf.0; Mon, 05 Aug 2024 02:18:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722849512; x=1723454312; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zmKZrnXukkShyh9UMVBbKCtUheE+m0Zm5Rm16FZ9/eQ=; b=kI0cu6Re6AG6f1FRjIMtIqsrxzR9/1r564myr4JjFStjkvKxAzDnGxdeE436jbTHhc zrsM77E8s+9o0Fn+rchd5q3mEXaH8Aga0/5awWhh59t2/SJK+x+ykJd4bCV3SYm15ZhW B5whEYi6+opiOZrl4mnlvI3WyiaYt8tos/2ta/yoa9xA5EFtIKeHx+dnHEjjj+INSmAR QlXS02bSDZFnSndx8fNwh3m8gmzG5qp2ZOGwae5DcDPNxj3NWQD6oPDvK0IuvNqY54yW DEa0Yg/6dGDRC8OAoKDVzlbwECG4iW01E0uzvkrgz8NAv/mC1lDpu+J8UNVxPI//unRS IGNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722849512; x=1723454312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zmKZrnXukkShyh9UMVBbKCtUheE+m0Zm5Rm16FZ9/eQ=; b=KnYJljxHYAd0EL+4T5v0gKWDvIWC6Q6FXK80s/jHAJcUuCMmIHQ1Wykc+RqQOrWPIj BDmqlVbhTORK4WYjVojwVM3oqcJxMjiRK4o+pZBY4xoI/xKsETVxLvq2hfHGVDqyQio8 U+a4j8KDC2WOSS24chKJuVIcJWggcPQdER9BjnRULLx+LCz88B8ucZUwNhWl1rktOi8q iJBIjoF7nuhiUtbPaqQhPY5GHirvowuqqJoVPFwTfuWQIN1ViBDOa2QMFFvMTB6hvulH b4jbXi+T9WTl6+oZxOTDVOKwBCBeUd/s9ImyCFMDQotMUqoxu0ThUEBUMuKDdJ8cGj8q 4VwA== X-Forwarded-Encrypted: i=1; AJvYcCX4Ffn7nOOm08wbm/enxhDb2N3nB+qS9VFhICm0xOSNAFT8GEKzrvkPag16L4hLuAOCZdMLcSi+oWFr+v4zfP3TfPSirmdRx3YG67A2UTth2hRsukE+S9IhBig6MP0rM6E8y04z/sHBvlJdK6ZryWr7SN6n8MMiS3kq8tVs7ghZ1/QGpA== X-Gm-Message-State: AOJu0YzCgDKNCvTR3lwdCFAOQzU6ZtHpsDxbK576JvLSrMIuaeC+OKBU oXHrmAqL86C+DEZDjM7Jh73MxX68E6IlMF+s9vgiRdUT8M8gbYGB X-Google-Smtp-Source: AGHT+IHt5AjerbbszibT04CTu+Jr9V86wxjhGeMFu/4kABcPnvtNQ1BSOPHfj2k8UNkcshgOsmiD1Q== X-Received: by 2002:a05:6820:1504:b0:5d5:d5ad:35f8 with SMTP id 006d021491bc7-5d67155434dmr12279312eaf.8.1722849511973; Mon, 05 Aug 2024 02:18:31 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5d762052c46sm1902121eaf.27.2024.08.05.02.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 02:18:31 -0700 (PDT) From: Chen Wang To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang , Drew Fustini Subject: [PATCH v6 4/8] mmc: sdhci-of-dwcmshc: factor out code into dwcmshc_rk35xx_init Date: Mon, 5 Aug 2024 17:18:19 +0800 Message-Id: <4f1f2fa403ce7f0b4d79afb7d7e8a1690cde5d6c.1722847198.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Continue factor out code fron probe into dwcmshc_rk35xx_init. Signed-off-by: Chen Wang Tested-by: Drew Fustini # TH1520 Tested-by: Inochi Amaoto # Duo and Huashan Pi Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-dwcmshc.c | 34 ++++++++++++++--------------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index b272ec2ab232..55fba5ef37ba 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -711,12 +711,22 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_reset(host, mask); } -static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) +static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host, + struct dwcmshc_priv *dwc_priv) { static const char * const clk_ids[] = {"axi", "block", "timer"}; - struct rk35xx_priv *priv = dwc_priv->priv; + struct rk35xx_priv *priv; int err; + priv = devm_kzalloc(dev, sizeof(struct rk35xx_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc")) + priv->devtype = DWCMSHC_RK3588; + else + priv->devtype = DWCMSHC_RK3568; + priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); if (IS_ERR(priv->reset)) { err = PTR_ERR(priv->reset); @@ -739,6 +749,8 @@ static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); + dwc_priv->priv = priv; + return 0; } @@ -1184,7 +1196,6 @@ static int dwcmshc_probe(struct platform_device *pdev) struct sdhci_pltfm_host *pltfm_host; struct sdhci_host *host; struct dwcmshc_priv *priv; - struct rk35xx_priv *rk_priv = NULL; const struct sdhci_pltfm_data *pltfm_data; int err; u32 extra, caps; @@ -1241,20 +1252,7 @@ static int dwcmshc_probe(struct platform_device *pdev) host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning; if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { - rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL); - if (!rk_priv) { - err = -ENOMEM; - goto err_clk; - } - - if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc")) - rk_priv->devtype = DWCMSHC_RK3588; - else - rk_priv->devtype = DWCMSHC_RK3568; - - priv->priv = rk_priv; - - err = dwcmshc_rk35xx_init(host, priv); + err = dwcmshc_rk35xx_init(dev, host, priv); if (err) goto err_clk; } @@ -1290,7 +1288,7 @@ static int dwcmshc_probe(struct platform_device *pdev) dwcmshc_cqhci_init(host, pdev); } - if (rk_priv) + if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) dwcmshc_rk35xx_postinit(host, priv); err = __sdhci_add_host(host); From patchwork Mon Aug 5 09:18:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13753295 Received: from mail-oo1-f47.google.com (mail-oo1-f47.google.com [209.85.161.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21706139D12; Mon, 5 Aug 2024 09:18:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849532; cv=none; b=oPgmgvmb3xbaeqgXk1BYrwbaiTobJouxkcY8nweirVZXkYwZJWLsTsFILTszwQcgNclHNeTO1gM/BL9G/ykxI6oQiL8626dS3JyE5GNsUpuWNr0cKhGm3jNDrooOwt0BdWEubRXeFSctgp1LmhaK52sZTUo9u0KQEMouMTIBHk0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849532; c=relaxed/simple; bh=OT1PAQFI1kISeEB6/Mju0shxPjUb/FrP6MLwj+WGzpQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fUYpqhDaugBoLsKLAyD+PhZOYiXQsnfA+guG29yeN9CjepXtl1NThkFlcw8lJe05o5y8jL1nZ0e+isYwTG+TCQxIVgSj17kagxiIvyZ+lNlzFwLfaxrNGdqGoUq6pHtgb3pbp6R3zPSt3NsKg5qoLJt6LcP3RZMxNe70zu6N+Fo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=C9GVT82P; arc=none smtp.client-ip=209.85.161.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="C9GVT82P" Received: by mail-oo1-f47.google.com with SMTP id 006d021491bc7-5d5e97b8a22so4566127eaf.2; Mon, 05 Aug 2024 02:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722849530; x=1723454330; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T1MnlW12Z5yHzYi9o0JgUJzJS63Qd/F5nfYcYQI4OPQ=; b=C9GVT82P/0r/zjOMqsfEdDhXM0CaQp+R0Jg1lq/eMa4zp+vcWBPNZYb5KhgwvC3UDz VjKfjEILdewMWDDK2ioHLbrHqCrSvrOjverSi3KvBYt0x3hqef7wZB7GipaCgYQTewhj Lmyd07SldVVii11fvQiSDoudHuAORB0Y4QcofChT4Xk2H9RdRvvYrz+THtXwLO3UQ8g4 UX9KMCfS78b4quAUxSWqb2EmUfbrA1oRTHnserCZg51NlibT4McEyuF3d88rXk0TNiuY wHbT6kKca+ypzwrVA7CdylE1sOCcBJCchB6gfc+TGUcni5H5uvnImkk/NPgJPETVXn1V pQ0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722849530; x=1723454330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T1MnlW12Z5yHzYi9o0JgUJzJS63Qd/F5nfYcYQI4OPQ=; b=Zd7Fopx7oRjuA+qvsYInOG57tZ5ugCPkkEu24XwsLDE9Q/HZPP9EdcH0Poj8EX71n6 rLRfWvxNRtjtMXm6I91XjIbTsGu8MDWiWv+ODRuvS/fXAq5ybqrN8cFzIvtcM7RXjGl9 uWrJrmCarzTs5bL5dnT/OUvt2UoOCo8l5BuY1K6WMgJKYyKKYfLU0OV4Y2l8M6s6YrrV JZDs/cdeM4gQnR2wfpicvzP86hdXckTUkQM0vS63HThZxPnqIuWiWII2TdyvrezwsuNa s5CzuY/OdhJLCSfOIqQYE9Z70+BsMfMoLHHDupxHv79g87v7wp9ve2PeWzfK8Ysh8Svu 9tiQ== X-Forwarded-Encrypted: i=1; AJvYcCUI6adqCCP0YJt/7s+XP58gVNu+cR8z3w78+mncjCLa1bfghOYW8ohBaq636qhvQKNlgPalQVnYucP/8ODdj6+gyiWer2zpfDpffYzgrb+DO/ZPZPW/xm/6d0kpoHA46yC8G80S6B1r+MQZk5ZrB9sJ4t6dazgbl4IWq65FSDgRuEfeSg== X-Gm-Message-State: AOJu0YzVzkdzvWC/hqJ5A/pAFMXlCXlkLK3Oof1lTZKowzhKViRyQdyH f/sfKv5KhMirAGqkpG2vSIW9WysliLDSgu11fOaqsU4dZM+QAB/z X-Google-Smtp-Source: AGHT+IE18FzxH3OoOcp5Zlherg/5bQthq69s9/T1LwkgOuOQJapvfIy1Z+YEqkBwYqUzxhpHCy3F+g== X-Received: by 2002:a05:6820:2228:b0:5c4:7b18:b8eb with SMTP id 006d021491bc7-5d6553365f8mr13200926eaf.2.1722849530205; Mon, 05 Aug 2024 02:18:50 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5d76261a27fsm1901822eaf.39.2024.08.05.02.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 02:18:49 -0700 (PDT) From: Chen Wang To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang , Drew Fustini Subject: [PATCH v6 5/8] mmc: sdhci-of-dwcmshc: add dwcmshc_pltfm_data Date: Mon, 5 Aug 2024 17:18:43 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Abstract dwcmshc_pltfm_data to hold the sdhci_pltfm_data plus some comoon operations of soc such as init/postinit. Signed-off-by: Chen Wang Tested-by: Drew Fustini # TH1520 Tested-by: Inochi Amaoto # Duo and Huashan Pi Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-dwcmshc.c | 81 +++++++++++++++++------------ 1 file changed, 48 insertions(+), 33 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 55fba5ef37ba..16f420994519 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -218,6 +218,12 @@ struct dwcmshc_priv { u16 flags; }; +struct dwcmshc_pltfm_data { + const struct sdhci_pltfm_data pdata; + int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); + void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); +}; + static int dwcmshc_get_enable_other_clks(struct device *dev, struct dwcmshc_priv *priv, int num_clks, @@ -1048,39 +1054,52 @@ static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = { .platform_execute_tuning = cv18xx_sdhci_execute_tuning, }; -static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { - .ops = &sdhci_dwcmshc_ops, - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, }; #ifdef CONFIG_ACPI -static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = { - .ops = &sdhci_dwcmshc_ops, - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | - SDHCI_QUIRK2_ACMD23_BROKEN, +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_bf3_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_ACMD23_BROKEN, + }, }; #endif -static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { - .ops = &sdhci_dwcmshc_rk35xx_ops, - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | - SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | - SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_rk35xx_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, + }, + .init = dwcmshc_rk35xx_init, + .postinit = dwcmshc_rk35xx_postinit, }; -static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = { - .ops = &sdhci_dwcmshc_th1520_ops, - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_th1520_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, + .init = th1520_init, }; -static const struct sdhci_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { - .ops = &sdhci_dwcmshc_cv18xx_ops, - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_cv18xx_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, }; static const struct cqhci_host_ops dwcmshc_cqhci_ops = { @@ -1196,7 +1215,7 @@ static int dwcmshc_probe(struct platform_device *pdev) struct sdhci_pltfm_host *pltfm_host; struct sdhci_host *host; struct dwcmshc_priv *priv; - const struct sdhci_pltfm_data *pltfm_data; + const struct dwcmshc_pltfm_data *pltfm_data; int err; u32 extra, caps; @@ -1206,7 +1225,7 @@ static int dwcmshc_probe(struct platform_device *pdev) return -ENODEV; } - host = sdhci_pltfm_init(pdev, pltfm_data, + host = sdhci_pltfm_init(pdev, &pltfm_data->pdata, sizeof(struct dwcmshc_priv)); if (IS_ERR(host)) return PTR_ERR(host); @@ -1251,16 +1270,12 @@ static int dwcmshc_probe(struct platform_device *pdev) host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning; - if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { - err = dwcmshc_rk35xx_init(dev, host, priv); + if (pltfm_data->init) { + err = pltfm_data->init(&pdev->dev, host, priv); if (err) goto err_clk; } - if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) { - th1520_init(dev, host, priv); - } - #ifdef CONFIG_ACPI if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) sdhci_enable_v4_mode(host); @@ -1288,8 +1303,8 @@ static int dwcmshc_probe(struct platform_device *pdev) dwcmshc_cqhci_init(host, pdev); } - if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) - dwcmshc_rk35xx_postinit(host, priv); + if (pltfm_data->postinit) + pltfm_data->postinit(host, priv); err = __sdhci_add_host(host); if (err) From patchwork Mon Aug 5 09:19:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13753296 Received: from mail-oo1-f41.google.com (mail-oo1-f41.google.com [209.85.161.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0F0C14F104; Mon, 5 Aug 2024 09:19:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849554; cv=none; b=VW82MJ1IOn/nWDXaH82g4ZOHpkZ1IAgE+kB/HThbYjdPA9QIdek5Qz6ZUUUquvju2tJHz05nuIRNfX+g3C6BSu0SIMuebLoVOcM37sYRTS2cWm0281pNLeS6BFZdtvzD4kk3Aqa2mH3XfU/sEb6v6RP355JvxM2Fi3E9lPfcJs8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849554; c=relaxed/simple; bh=+FGlhkhwHxHnbAyHFkllHV1+6TCRzAU4acFGmNqwwWg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=m53a4DplaVVVix9aMIJGGHCJ2iisD3bUNXXb2L9QHPPRD4Azd5r3PBGyBl1OskNORR2jzlt4GuSlalOy/o3a/eziit8090Jh0nheXRIyUS0h8amDPUB4B1Bag0Uk4w5w9PtWPyPJDrGpsRdlcuEQKHRcfDhCnPs78USEs7FexN8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ODSrkxCa; arc=none smtp.client-ip=209.85.161.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ODSrkxCa" Received: by mail-oo1-f41.google.com with SMTP id 006d021491bc7-5d5c324267aso5514622eaf.0; Mon, 05 Aug 2024 02:19:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722849552; x=1723454352; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cKZKLwIrLvB9ZFsYAq1sUq9lxL9HVjwkxz7TvV3FNk8=; b=ODSrkxCanF1JFeeD1RZkpkFXu9JkGoeBPEijtc1mjLBzAnslZ2C8I0FCBnwCIiWi3z Cm+cENFIpAe6vzwV9XEFPQNdPZ/QYHKOPZKaf1qm18Yo1OJ1Lw4Y8ZyJTBcn9a1sK1Nq PoIEJ9wYk9wfXd5twZ8M0bJJl/iuM+wDZIOGogbVTeyFfFups+njUY2PXE5rx97hW5Am WzoNBLP9asGqbm6OR7LWap9QRe5cQFnZejs6SeI9lG+59kc0zJhIYl0CBTRoveXEwlLu vDITYE1ndX8feYwQKRRcyZV8vpcqcNLt+PNLgovJqN68Q7358JLQKaa9RO8WfKOXV0DL cmjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722849552; x=1723454352; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cKZKLwIrLvB9ZFsYAq1sUq9lxL9HVjwkxz7TvV3FNk8=; b=pYwOBXH0DaQ84Y7+ipLq/eEUPJ8gjdSdeNxGOws/PVv1Hg5FOIKnlIcIVKHzPfd83d eVIlfF1n/4eLjOcQ4xVGTSci8s/ms4PSuhtrIeBE/+n0ouucoPNzSvXQjsIo9zdHvVI4 YWoGzBClZhG28ry1P1IoTVPa8PZgYyIImaedRc0higKg04ckJ+UvxwpMjdVqiBTCexMG 3StDTu5GjcdXeFgLMzwE2Hr0gUWxErTEE1QmYjI81XZ/BUHiGzcBwmSv1l494Rps2H31 sHle7KFfaMzguCJQwvPy3lPDEcV1cZ4I2LWBIHemJSsfYRxRteAbtPd+bZWxT9k3vB7b Mi9A== X-Forwarded-Encrypted: i=1; AJvYcCWtKi/Ix842B49Uese2KAgoNbV/gWLI8mxKnH7wDGkrcVeZhiZuz9FJA03zV+scmHHSBH6pFpNwgLjAEtvY+MyliMeMT/V+7uNz8fIcjiduoUzxxANG8g43u3YQwRpgxQz+u1ZkN5C+XNrri9/L5KgvflgR8tVp3F58+LREf1rOicTsCw== X-Gm-Message-State: AOJu0YwdAvP8A6T0WTugbLQl/bnemHiUPfrY6H5gRrOeVHmaYAzHZU4o ADCDGeAXA8Yk7c2W9UE3QtxG1CQy3KMPr5LU0YyDfWNvEQMz2RDE X-Google-Smtp-Source: AGHT+IFpabPlu04Zp+9kW5LL/5GpnkEoFtCPrhlmJpSoDUSCC7Ht9xubRYfCNquJfjUV8vCE0qZrIA== X-Received: by 2002:a05:6820:2903:b0:5c9:d9db:6a51 with SMTP id 006d021491bc7-5d8107b74b9mr5369594eaf.0.1722849551987; Mon, 05 Aug 2024 02:19:11 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-70a3a768e12sm2884751a34.65.2024.08.05.02.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 02:19:11 -0700 (PDT) From: Chen Wang To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang , Conor Dooley Subject: [PATCH v6 6/8] dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo SG2042 support Date: Mon, 5 Aug 2024 17:19:04 +0800 Message-Id: <9ca450097e5389a38bcd7d8ddf863766df4cea10.1722847198.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang SG2042 use Synopsys dwcnshc IP for SD/eMMC controllers. SG2042 defines 3 clocks for SD/eMMC controllers. - EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), so reuse existing "core". - AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc) and blck(Core Base Clock in DWC_mshc), these 3 clocks share one source, so reuse existing "bus". - 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse existing "timer" which was added for rockchip specified. Signed-off-by: Chen Wang Reviewed-by: Conor Dooley --- .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 60 +++++++++++++------ 1 file changed, 43 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index 4d3031d9965f..80d50178d2e3 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -10,9 +10,6 @@ maintainers: - Ulf Hansson - Jisheng Zhang -allOf: - - $ref: mmc-controller.yaml# - properties: compatible: enum: @@ -21,6 +18,7 @@ properties: - snps,dwcmshc-sdhci - sophgo,cv1800b-dwcmshc - sophgo,sg2002-dwcmshc + - sophgo,sg2042-dwcmshc - thead,th1520-dwcmshc reg: @@ -31,22 +29,11 @@ properties: clocks: minItems: 1 - items: - - description: core clock - - description: bus clock for optional - - description: axi clock for rockchip specified - - description: block clock for rockchip specified - - description: timer clock for rockchip specified - + maxItems: 5 clock-names: minItems: 1 - items: - - const: core - - const: bus - - const: axi - - const: block - - const: timer + maxItems: 5 resets: maxItems: 5 @@ -63,7 +50,6 @@ properties: description: Specify the number of delay for tx sampling. $ref: /schemas/types.yaml#/definitions/uint8 - required: - compatible - reg @@ -71,6 +57,46 @@ required: - clocks - clock-names +allOf: + - $ref: mmc-controller.yaml# + + - if: + properties: + compatible: + contains: + const: sophgo,sg2042-dwcmshc + + then: + properties: + clocks: + items: + - description: core clock + - description: bus clock + - description: timer clock + clock-names: + items: + - const: core + - const: bus + - const: timer + else: + properties: + clocks: + minItems: 1 + items: + - description: core clock + - description: bus clock for optional + - description: axi clock for rockchip specified + - description: block clock for rockchip specified + - description: timer clock for rockchip specified + clock-names: + minItems: 1 + items: + - const: core + - const: bus + - const: axi + - const: block + - const: timer + unevaluatedProperties: false examples: From patchwork Mon Aug 5 09:19:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13753297 Received: from mail-oi1-f181.google.com (mail-oi1-f181.google.com [209.85.167.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B8B314B972; Mon, 5 Aug 2024 09:19:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849574; cv=none; b=a8gL58gULEqhDPdLY2sGLp/fuQnxGsAlmTJc0aJMUZFocY9B+/95b4PbTQk91T5n2HD9VRxageGC/rbU0bjP6voex+Jc6N1dwXlsFcO/6fxSoMGrIuTxrDD9FOO/35+J22q9A0dRuiQa6EWM8AHoEHf1VsIRQbHTr9l1kwZt220= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849574; c=relaxed/simple; bh=XaZLr7IoQl3tCsBD0MzKm7r3OHhzhTX9bE9XWcen/QA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=chHBd7rCjTFvVRW0/fUXH6wyviOpIoCD29TkcKte7Ou8tDZ3+goYYrmZgJYiZ2lbzx+EeLKk/gZP6Pcvimw6zo/YxYP2Tu4DM1M5VXguARncKNBtZz0rsR6xyxxhQyjTfinFHgFw5QdDLCbyJPq/VZnkjzthiVdxG3536N1PLho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=nIuyg1yi; arc=none smtp.client-ip=209.85.167.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nIuyg1yi" Received: by mail-oi1-f181.google.com with SMTP id 5614622812f47-3db19caec60so7285611b6e.1; Mon, 05 Aug 2024 02:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722849572; x=1723454372; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lp03N9q94P+b0VTfwMKBdE9lEAm1JOVbrcRtoFwvCAM=; b=nIuyg1yipcpF6tuXvmwnIsuw15mgJPK1IEn52yh9XToqjuPUgypbn2AEEB3YuxR4bw c8cqYu7b/M/DEPqNnNRhVA12v9uxE6ptBi9+Msvrzlm3ZPS0DjWZ6eeM3Bonfnb3QVJD i0Pg3NlrU31l1bMcjVFd5xs5B8+k8xgaEMLs8m4HOFqC1MzWfgFzxS1aDKaEYTIIamKS bH5rIA5TP+gxpHgzcjvTPrrK6oBq8W7Ezl/leb55yqpePOkwEsEw8r6DRzbIm/oD2BJo JZoaT/y6rJNPjFcRUSQBndK3AjFA2IFno/Xmtny2Kj5UcyW4l8KAygTimRY3WdSVASBz 6rew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722849572; x=1723454372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lp03N9q94P+b0VTfwMKBdE9lEAm1JOVbrcRtoFwvCAM=; b=nyvKsn2WErd/+UeFNxyg/PscjHFrnUXaM2S7uqIiLTsKcOEvTpvGgzj5fROhcRmEZX lMbZQGCn7pvagvOB+d5MRE4dGV4+K6iZ8yS0nxqBAIebDha3thbx3oEp7H+ZwTXAxDcg 9ChnnsmdhpUU+8AcmDO2SRd8JOpVtfxDsLc1hG4cu6DpRV7xOnB8swL8oxd5H+/1+VaM /dXekSNtuhsQ351J/MtoITXLW9TibY6yfa4e7S7zZojAjE6QzgvI2oN4ASMlh/TRtCVU UdvR99uAQolULvqcnP5mPsZnt6p0c3iuPXOT36Bwe0RAD+GH66FSPD4b4ZwBueUz+7Dx 4xtA== X-Forwarded-Encrypted: i=1; AJvYcCV8bEnwsr2UpyFyqg36D33OC61LhU7bptb/WJzEuCxOw9bnlv+JTsa8HFxzQ7nTB06+zyHR82VHQj2FEb9YVkpb6eXvNOd4XauaWNujALZGpFbPgdbkR86N4vnGbS28IUu6tjMJeZeZ3Ok1ygHyb8kqnV8+OjLMKcoFHtGBFDBUalszhg== X-Gm-Message-State: AOJu0YwBMnq4fv7PfcvyxdsuFdafC/Dmkfk1Wayb98QBAVFCM3ctk5Ym 31BNt5H+GqDHeLDnQBhYuWd4blp/zXC5ttzNvSTQHzKtXu8TvYyE X-Google-Smtp-Source: AGHT+IEfmOLizMFk5P/SrlD7UaXTnriU6WQmVeoharKwUK7VAo90vO3Sw/aoWRuOCvcRBnL4je5sFw== X-Received: by 2002:a05:6808:1444:b0:3db:25f6:a59c with SMTP id 5614622812f47-3db557fdf3amr15784856b6e.6.1722849572375; Mon, 05 Aug 2024 02:19:32 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3db563c7381sm2561166b6e.56.2024.08.05.02.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 02:19:32 -0700 (PDT) From: Chen Wang To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang Subject: [PATCH v6 7/8] mmc: sdhci-of-dwcmshc: Add support for Sophgo SG2042 Date: Mon, 5 Aug 2024 17:19:24 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Add support for the mmc controller of Sophgo SG2042. SG2042 uses Synopsys PHY the same as TH1520 so we reuse the tuning logic from TH1520. Besides this, this patch implement some SG2042 specific work, such as clocks and reset ops. Signed-off-by: Chen Wang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-dwcmshc.c | 125 ++++++++++++++++++++++++++-- 1 file changed, 118 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 16f420994519..ba8960d8b2d4 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -113,12 +113,15 @@ #define DWC_MSHC_PTR_PHY_R 0x300 /* PHY general configuration */ -#define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) -#define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ -#define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ -#define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ -#define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ -#define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ +#define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) +#define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ +#define PHY_CNFG_PHY_PWRGOOD_MASK BIT_MASK(1) /* bit [1] */ +#define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ +#define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ +#define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */ +#define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ +#define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ +#define PHY_CNFG_PAD_SN_SG2042 0x08 /* NMOS TX drive strength for SG2042 */ /* PHY command/response pad settings */ #define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) @@ -147,10 +150,12 @@ #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ #define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ +#define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */ /* PHY CLK delay line settings */ #define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) -#define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ +#define PHY_SDCLKDL_CNFG_EXTDLY_EN BIT(0) +#define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ /* PHY CLK delay line delay code */ #define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) @@ -158,10 +163,14 @@ #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ +#define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20) +#define PHY_SMPLDL_CNFG_BYPASS_EN BIT(1) + /* PHY drift_cclk_rx delay line configuration setting */ #define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) #define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ +#define PHY_ATDL_CNFG_INPSEL_SG2042 0x2 /* delay line input source for SG2042 */ /* PHY DLL control settings */ #define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) @@ -1013,6 +1022,85 @@ static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) return ret; } +static inline void sg2042_sdhci_phy_init(struct sdhci_host *host) +{ + u32 val; + + /* Asset phy reset & set tx drive strength */ + val = sdhci_readl(host, PHY_CNFG_R); + val &= ~PHY_CNFG_RSTN_DEASSERT; + val |= FIELD_PREP(PHY_CNFG_PHY_PWRGOOD_MASK, 1); + val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP_SG2042); + val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN_SG2042); + sdhci_writel(host, val, PHY_CNFG_R); + + /* Configure phy pads */ + val = PHY_PAD_RXSEL_3V3; + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val = PHY_PAD_RXSEL_3V3; + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val = PHY_PAD_RXSEL_3V3; + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); + + /* Configure delay line */ + /* Enable fixed delay */ + sdhci_writeb(host, PHY_SDCLKDL_CNFG_EXTDLY_EN, PHY_SDCLKDL_CNFG_R); + /* + * Set delay line. + * Its recommended that bit UPDATE_DC[4] is 1 when SDCLKDL_DC is being written. + * Ensure UPDATE_DC[4] is '0' when not updating code. + */ + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val |= PHY_SDCLKDL_CNFG_UPDATE; + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + /* Add 10 * 70ps = 0.7ns for output delay */ + sdhci_writeb(host, 10, PHY_SDCLKDL_DC_R); + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &= ~(PHY_SDCLKDL_CNFG_UPDATE); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + /* Set SMPLDL_CNFG, Bypass */ + sdhci_writeb(host, PHY_SMPLDL_CNFG_BYPASS_EN, PHY_SMPLDL_CNFG_R); + + /* Set ATDL_CNFG, tuning clk not use for init */ + val = FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL_SG2042); + sdhci_writeb(host, val, PHY_ATDL_CNFG_R); + + /* Deasset phy reset */ + val = sdhci_readl(host, PHY_CNFG_R); + val |= PHY_CNFG_RSTN_DEASSERT; + sdhci_writel(host, val, PHY_CNFG_R); +} + +static void sg2042_sdhci_reset(struct sdhci_host *host, u8 mask) +{ + sdhci_reset(host, mask); + + if (mask & SDHCI_RESET_ALL) + sg2042_sdhci_phy_init(host); +} + +static int sg2042_init(struct device *dev, struct sdhci_host *host, + struct dwcmshc_priv *dwc_priv) +{ + static const char * const clk_ids[] = {"timer"}; + + return dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, + ARRAY_SIZE(clk_ids), clk_ids); +} + static const struct sdhci_ops sdhci_dwcmshc_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -1054,6 +1142,16 @@ static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = { .platform_execute_tuning = cv18xx_sdhci_execute_tuning, }; +static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = dwcmshc_set_uhs_signaling, + .get_max_clock = dwcmshc_get_max_clock, + .reset = sg2042_sdhci_reset, + .adma_write_desc = dwcmshc_adma_write_desc, + .platform_execute_tuning = th1520_execute_tuning, +}; + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { .pdata = { .ops = &sdhci_dwcmshc_ops, @@ -1102,6 +1200,15 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { }, }; +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_sg2042_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, + .init = sg2042_init, +}; + static const struct cqhci_host_ops dwcmshc_cqhci_ops = { .enable = dwcmshc_sdhci_cqe_enable, .disable = sdhci_cqe_disable, @@ -1194,6 +1301,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { .compatible = "thead,th1520-dwcmshc", .data = &sdhci_dwcmshc_th1520_pdata, }, + { + .compatible = "sophgo,sg2042-dwcmshc", + .data = &sdhci_dwcmshc_sg2042_pdata, + }, {}, }; MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); From patchwork Mon Aug 5 09:19:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13753298 Received: from mail-oi1-f182.google.com (mail-oi1-f182.google.com [209.85.167.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99DA114F9D4; Mon, 5 Aug 2024 09:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849593; cv=none; b=WeN7uRJYWKkVbuWnG62PIIpoG7GbF0rQLvIDZrtmGCdXq5vbr+w4TNO5Ez0sH0IbIGXqwCB9ZqR2T+Nufa05t2Y/c7Bbh79wtoMJRpd1/ESDQuTkh9n3axByYUrbA/z6cIZW+TL5CwKI6DtwRBSb0e2fTgPaQPmhWPCCKocOsFU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722849593; c=relaxed/simple; bh=OcG6l4XKFmePQVwp6PRs5BvS9biFtJr4B9ey1kRGDJA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hkXhaaTC055lYDjbp4167NXRtEoeO+eXoXRZW9xmze1qui+n7dI29KuIWK+z5A59ERDOmfyhkLmHfOr352ZHr0oIqWDnkGVFONg3BRVaknO0ApKdITOJBSzBmNm/VUAQHEFD9nT8dSBdJ0iEqSuhMpvml8LMwrvvX3ZLGzq/2iM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SssipjaT; arc=none smtp.client-ip=209.85.167.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SssipjaT" Received: by mail-oi1-f182.google.com with SMTP id 5614622812f47-3db23a6085aso2822304b6e.1; Mon, 05 Aug 2024 02:19:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722849591; x=1723454391; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wTqIbxxugoDxIZS+wlCgd6QZms9qOuPLg9XDgZyFHpw=; b=SssipjaTpZrFOUr+LFu4fKqMFowycrrS71523oY8hu721SgiLmO+lUPc3Bb1QngE4I EQuAhX6zEHICvE1/T8X1IGBWO7cUSJlRq77xoICFcUV0yItFvZHW+eiEsgp9lVo5FnkU 23RKLWB6o1R/Zgge9KUQd8TkcB94QK7Tnk75nSntcYl3zopKmg4FCOLcE2PQ+2kGHL2Y gPl9LKe0oBn6pS/t6/fXL0kOlvx9KOqSaLBZffs6Zf9KAxA1JsNgbeNNWGG6fhJIuGo+ azvc9RvsrQSnX0Ny8eRUr2iJD+n1vyni/bZnTaNv5RVJPHxNelMtumJYJOawAXJiIjVj v7ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722849591; x=1723454391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wTqIbxxugoDxIZS+wlCgd6QZms9qOuPLg9XDgZyFHpw=; b=C6Tl3+0XZBT7k2zitxoxrop9k07KYTsmdATc4kCH1xJ2lvY/8jdwWcQ7YXmzKzj+9x p2i8ftUcfEdzepC40rc44YLFeiwI8h05a9jdd/foVI34LwM01u8xUfjpatMwmAqIKhAi LvMoygkDSQkIP7h5AkR9ZDhlO07oDN6WFMzI/nmfps6EwSsNtkrSL2WLn4Y1kvce9Ltu ecJneDC2NWnnWvhRjnGYxkVBh/CXBF4DhXucsdaKFTN+FhuNq0ZGm34JtUgILRICoSGp orRBROSEtOjRRp1UDIo+ZGfW69SCBgyKDZrQYnlAZXTc8CUyVdVJ2HtjRonGOu7K8EJV vKxQ== X-Forwarded-Encrypted: i=1; AJvYcCUAqgoLeT8y8sze8vH7U1uKr1aKBTkPSNTRpOP0dDHrJmjGezja5IZN9lvPEIIpc0CqmQaHGi3arEQHUDAe+8sE7qsud93J4t0oj470YM6ujytErd9U+zJqqBNvjo/Mjz7QBimm238M/hwQltHeJ4PaZVgJJ6Rpi/8IPGuQEhak22ct0w== X-Gm-Message-State: AOJu0YwicMTB6JDc8SR5EScVhWQuTTqZaedEZhGH9ArbkZAtitv4IjCO rvZ0c5YblbvDED6wF/b0fz/8L9/v1DlS30Cr0UD6YZIKUwmiFz7C X-Google-Smtp-Source: AGHT+IGQn28apZPLjY/cEqCd5i6fKpWv0taDd9wpuFCfINNuy5KX2wH7As+1leEZiltafu5WJpLcAA== X-Received: by 2002:a05:6808:f0a:b0:3d2:95f:da8c with SMTP id 5614622812f47-3db5381638dmr5222260b6e.18.1722849590714; Mon, 05 Aug 2024 02:19:50 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-70a31d9dd1asm2875838a34.9.2024.08.05.02.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 02:19:50 -0700 (PDT) From: Chen Wang To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang Subject: [PATCH v6 8/8] riscv: sophgo: dts: add mmc controllers for SG2042 SoC Date: Mon, 5 Aug 2024 17:19:43 +0800 Message-Id: <03ac9ec9c23bbe4c3b30271e76537bdbe5638665.1722847198.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang SG2042 has two MMC controller, one for emmc, another for sd-card. Signed-off-by: Chen Wang --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 17 +++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 28 +++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 80cb017974d8..da6596e9192e 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -26,6 +26,23 @@ &cgi_dpll1 { clock-frequency = <25000000>; }; +&emmc { + bus-width = <4>; + no-sdio; + no-sd; + non-removable; + wp-inverted; + status = "okay"; +}; + +&sd { + bus-width = <4>; + no-sdio; + no-mmc; + wp-inverted; + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 34c802bd3f9b..f0ccefecc9c3 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -399,5 +399,33 @@ uart0: serial@7040000000 { resets = <&rstgen RST_UART0>; status = "disabled"; }; + + emmc: mmc@704002a000 { + compatible = "sophgo,sg2042-dwcmshc"; + reg = <0x70 0x4002a000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <134 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkgen GATE_CLK_EMMC_100M>, + <&clkgen GATE_CLK_AXI_EMMC>, + <&clkgen GATE_CLK_100K_EMMC>; + clock-names = "core", + "bus", + "timer"; + status = "disabled"; + }; + + sd: mmc@704002b000 { + compatible = "sophgo,sg2042-dwcmshc"; + reg = <0x70 0x4002b000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <136 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkgen GATE_CLK_SD_100M>, + <&clkgen GATE_CLK_AXI_SD>, + <&clkgen GATE_CLK_100K_SD>; + clock-names = "core", + "bus", + "timer"; + status = "disabled"; + }; }; };