From patchwork Mon Aug 5 15:52:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13753804 X-Patchwork-Delegate: kieran@bingham.xyz Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B7BB015B13B; Mon, 5 Aug 2024 16:22:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722874926; cv=none; b=pMqL7NF+z+0s8yHeRw81Qac6IuQrDuo3DwD7wSIUYh3hdQ9WD+lms0k6jeKRoOGUymp9fCxqpWCyjyFttBo7lkuKSY7AMkCf2dbcyBoiPs18kCy4VMCVghQmR6+7UnsVnbF17bsR5wfH7rtQLOBCBT93C5J5FpdmN3n+pjraBsk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722874926; c=relaxed/simple; bh=PAan1aJRP8MucfPhoa+QmqqzfjZMU9RrSbuhN0XTfbw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AdDunUFN7cUtjGA5lsFjxFdglfqKlmOoNDT45sKiMOKZqk89tysw300WXS7XDkiPUXb+8ikQppJ7aOpcS0Jytd07gffCwViJODmRdsTaOU0ibV/j9tNsLg8bBP33ZZMK1hY/5nGpOwvvrIdKPPrkmTGiZO1q/jO1ossxEAafYD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.09,265,1716217200"; d="scan'208";a="214738307" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 06 Aug 2024 01:22:01 +0900 Received: from localhost.localdomain (unknown [10.226.92.197]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 19EF34009403; Tue, 6 Aug 2024 00:52:50 +0900 (JST) From: Biju Das To: Biju Das , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 1/4] dt-bindings: display: renesas,rzg2l-du: Document RZ/G2UL DU bindings Date: Mon, 5 Aug 2024 16:52:35 +0100 Message-ID: <20240805155242.151661-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240805155242.151661-1-biju.das.jz@bp.renesas.com> References: <20240805155242.151661-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document DU found in RZ/G2UL SoC. The DU block is identical to RZ/G2L SoC, but has only DPI interface. While at it, add missing required property port@1 for RZ/G2L and RZ/V2L SoCs. Currently there is no user for the DPI interface and hence there won't be any ABI breakage for adding port@1 as required property for RZ/G2L and RZ/V2L SoCs. Signed-off-by: Biju Das --- v2->v3: * Replaced ports->port property for RZ/G2UL as it supports only DPI. and retained ports property for RZ/{G2L,V2L} as it supports both DSI and DPI output interface. * Added missing blank line before example. * Dropped tags from Conor and Geert as there are new changes. v1->v2: * Updated commit description related to non ABI breakage. * Added Ack from Conor. --- .../bindings/display/renesas,rzg2l-du.yaml | 35 +++++++++++++++++-- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index 08e5b9478051..ca01bf26c4c0 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -18,6 +18,7 @@ properties: compatible: oneOf: - enum: + - renesas,r9a07g043u-du # RZ/G2UL - renesas,r9a07g044-du # RZ/G2{L,LC} - items: - enum: @@ -60,8 +61,9 @@ properties: $ref: /schemas/graph.yaml#/properties/port unevaluatedProperties: false - required: - - port@0 + port: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to the DU output video port. unevaluatedProperties: false @@ -83,11 +85,38 @@ required: - clock-names - resets - power-domains - - ports - renesas,vsps additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a07g043u-du + then: + properties: + port: + description: DPI + + required: + - port + else: + properties: + ports: + properties: + port@0: + description: DSI + port@1: + description: DPI + + required: + - port@0 + - port@1 + required: + - ports + examples: # RZ/G2L DU - | From patchwork Mon Aug 5 15:52:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13753808 X-Patchwork-Delegate: kieran@bingham.xyz Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 96DE11547DC for ; Mon, 5 Aug 2024 16:22:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722874932; cv=none; b=BAQRtsFrcB9jMLH3xMLWrGF1zQRsoBC0WQjuCvHULHU3oIuI1zoLQRHK+LlfmSI4oflalQNLBCb71XBRf9OJ7Y7vE0g0G6rVHDF60aIcT4pgCq4h/PJys2UPzkBApcUSVtJZ9jXtmTrcyBgvbPxON/qKWK3YAtJqKGfrn1Bwdp4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722874932; c=relaxed/simple; bh=OeYjNe/w5i582MPFt92xbmrQGYyYP5+9IHbF+3Iv+yQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iV9SnzfZPTNBa0OWeSoMuHpE2Q7z0CzeHgRJbTvZO25cHh1NTcCjIqtjoqxjNF5w66gnnOCX2/7aXrFsoEgcHBhbYfUI904WGfQeu0rxXYGtdIN5BfRjWeCG++B/F8eiZISQhaAnq3YQuP6FgoUTEiaYM/tBSIf+C2rZUbpgmEE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.09,265,1716217200"; d="scan'208";a="218709933" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 06 Aug 2024 01:22:01 +0900 Received: from localhost.localdomain (unknown [10.226.92.197]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 492BB4008C7C; Tue, 6 Aug 2024 00:52:56 +0900 (JST) From: Biju Das To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter Cc: Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 2/4] drm: renesas: rz-du: Add RZ/G2UL DU Support Date: Mon, 5 Aug 2024 16:52:36 +0100 Message-ID: <20240805155242.151661-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240805155242.151661-1-biju.das.jz@bp.renesas.com> References: <20240805155242.151661-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The LCD controller is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). It has DPI interface and supports a maximum resolution of WXGA along with 2 RPFs to support the blending of two picture layers and raster operations (ROPs). The DU module is connected to VSPD. Add RZ/G2UL DU support. Signed-off-by: Biju Das --- v2->v3: * Avoided the line break in rzg2l_du_start_stop() for rstate. * Replaced port->du_output in struct rzg2l_du_output_routing and dropped using the port number to indicate the output type in rzg2l_du_encoders_init(). * Updated rzg2l_du_r9a07g043u_info and rzg2l_du_r9a07g044_info v1->v2: * No change. --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 8 +++++++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 18 ++++++++++++++++-- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 5 +++-- drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 4 ++-- 4 files changed, 28 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c index 6e7aac6219be..fd7675c7f181 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c @@ -28,6 +28,7 @@ #include "rzg2l_du_vsp.h" #define DU_MCR0 0x00 +#define DU_MCR0_DPI_OE BIT(0) #define DU_MCR0_DI_EN BIT(8) #define DU_DITR0 0x10 @@ -216,9 +217,14 @@ static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rcrtc) static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start) { + struct rzg2l_du_crtc_state *rstate = to_rzg2l_crtc_state(rcrtc->crtc.state); struct rzg2l_du_device *rcdu = rcrtc->dev; + u32 val = DU_MCR0_DI_EN; - writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0); + if (rstate->outputs == BIT(RZG2L_DU_OUTPUT_DPAD0)) + val |= DU_MCR0_DPI_OE; + + writel(start ? val : 0, rcdu->mmio + DU_MCR0); } static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c index e5eca8691a33..69b8e216ee1a 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -25,21 +25,35 @@ * Device Information */ +static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = { + .channels_mask = BIT(0), + .routes = { + [RZG2L_DU_OUTPUT_DSI0] = { + .du_output = RZG2L_DU_OUTPUT_INVALID, + }, + [RZG2L_DU_OUTPUT_DPAD0] = { + .possible_outputs = BIT(0), + .du_output = RZG2L_DU_OUTPUT_DPAD0, + }, + }, +}; + static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { .channels_mask = BIT(0), .routes = { [RZG2L_DU_OUTPUT_DSI0] = { .possible_outputs = BIT(0), - .port = 0, + .du_output = RZG2L_DU_OUTPUT_DSI0, }, [RZG2L_DU_OUTPUT_DPAD0] = { .possible_outputs = BIT(0), - .port = 1, + .du_output = RZG2L_DU_OUTPUT_DPAD0, } } }; static const struct of_device_id rzg2l_du_of_table[] = { + { .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info }, { .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info }, { /* sentinel */ } }; diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h index 58806c2a8f2b..ab82b5c86d6e 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h @@ -29,7 +29,7 @@ enum rzg2l_du_output { /* * struct rzg2l_du_output_routing - Output routing specification * @possible_outputs: bitmask of possible outputs - * @port: device tree port number corresponding to this output route + * @du_output: DU output * * The DU has 2 possible outputs (DPAD0, DSI0). Output routing data * specify the valid SoC outputs, which CRTC can drive the output, and the type @@ -37,7 +37,7 @@ enum rzg2l_du_output { */ struct rzg2l_du_output_routing { unsigned int possible_outputs; - unsigned int port; + unsigned int du_output; }; /* @@ -53,6 +53,7 @@ struct rzg2l_du_device_info { #define RZG2L_DU_MAX_CRTCS 1 #define RZG2L_DU_MAX_VSPS 1 #define RZG2L_DU_MAX_DSI 1 +#define RZG2L_DU_OUTPUT_INVALID -1 struct rzg2l_du_device { struct device *dev; diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c index 07b312b6f81e..361350f2999e 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c @@ -183,8 +183,8 @@ static int rzg2l_du_encoders_init(struct rzg2l_du_device *rcdu) /* Find the output route corresponding to the port number. */ for (i = 0; i < RZG2L_DU_OUTPUT_MAX; ++i) { - if (rcdu->info->routes[i].port == ep.port) { - output = i; + if (i == rcdu->info->routes[i].du_output) { + output = rcdu->info->routes[i].du_output; break; } } From patchwork Mon Aug 5 15:52:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13753807 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5617515C133; Mon, 5 Aug 2024 16:22:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722874931; cv=none; b=u6Ua33hcGp9D6pUHn6hJbAbEL2+bZyehVoFdF+4+GBiPr+uU2AUv5s8v86qlHJeM0XVNsctty3fkYe+q60T5+RMIREnX7fU10dxcNJRQTaAAroskSxou0qXEmXSeQT/lf7gLfm3ENS0iZ7I9+5O4GMIuj04OMmr2R9GNr9pkeCY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722874931; c=relaxed/simple; bh=GlIDRhSQnul6LvCLJ/Z/ivLYh/9VDF0ohCMcEHGlmfU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YIQgL/go2PvTE//87IdiUjTqWX/q8v0V9nUP5gLK8nDhGJIUiV73E+fLOlX6ELHd81G7GgaacCPHxXGO0KQctEgm1NnvBWa1Pz4e4mPRxubw1BapiiH16yGI+FfgSq8Q5kTmHkEjy5Bm0Ip3Yi1040iy8Yuf4W4XK8PIg3QmkBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.09,265,1716217200"; d="scan'208";a="218709935" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 06 Aug 2024 01:22:01 +0900 Received: from localhost.localdomain (unknown [10.226.92.197]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 401854009408; Tue, 6 Aug 2024 00:53:01 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Prabhakar Mahadev Lad , Biju Das , Laurent Pinchart Subject: [PATCH v3 3/4] arm64: dts: renesas: r9a07g043u: Add DU node Date: Mon, 5 Aug 2024 16:52:37 +0100 Message-ID: <20240805155242.151661-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240805155242.151661-1-biju.das.jz@bp.renesas.com> References: <20240805155242.151661-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add DU node to RZ/G2UL SoC DTSI. Reviewed-by: Laurent Pinchart Signed-off-by: Biju Das --- v2->v3: * Dropped ports->port as it supports only DPI * Added Rb tag from Laurent. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index d88bf23b0782..ba88c91c66c8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -153,6 +153,25 @@ fcpvd: fcp@10880000 { resets = <&cpg R9A07G043_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g043u-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + port { + du_out_rgb: endpoint { + }; + }; + }; + irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043u-irqc", "renesas,rzg2l-irqc"; From patchwork Mon Aug 5 15:52:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13753806 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6D10515C133; Mon, 5 Aug 2024 16:22:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722874928; cv=none; b=ow/VzbS0voZRLuGRXPM9Ux6/9YFPlOr2i8nG4t1SnUnKGyLFU/FRd+6ptAyzhALNSqxuI/ktI19q5sY7m60qvPNjUUtRQ/gvEkei0pS6l3aDYt8ybgwW7rsGUcZMlhF1EJXvmjp+9NZm3SO2j5C8gIcMYek/7aUZp6nA6sVBrw8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722874928; c=relaxed/simple; bh=Fvv83yoWgMqTaYbY5iVvHu/h69nZdopCjP2naLrE0tg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kC3rWbOimQEsFrkjGgq1a/Y87oUZ1IAsBbAciU/wlyEG4rWbku3/VaIx3YvGfh/iWc25CmYqHf5BHE3rk8h3Dz1ZIoj+lp4m6BxLosEMXcjkX3+wj2QUHI/KCEx05H5g9f9EPzfHlDkASgnzM/apjSpDZmj9DPk/oexoJlhpEzs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.09,265,1716217200"; d="scan'208";a="214738518" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 06 Aug 2024 01:22:02 +0900 Received: from localhost.localdomain (unknown [10.226.92.197]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id CBB294009413; Tue, 6 Aug 2024 00:53:06 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 4/4] arm64: dts: renesas: r9a07g043u11-smarc: Enable DU Date: Mon, 5 Aug 2024 16:52:38 +0100 Message-ID: <20240805155242.151661-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240805155242.151661-1-biju.das.jz@bp.renesas.com> References: <20240805155242.151661-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable DU and link with the HDMI add-on board connected with the parallel connector on RZ/G2UL SMARC EVK. Signed-off-by: Biju Das --- v2->v3: * Replaced ports->port in du node as it support only DPI output. v1->v2: * No change. --- .../boot/dts/renesas/r9a07g043u11-smarc.dts | 109 ++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 8e0107df2d46..418902e1370e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -35,4 +35,113 @@ / { model = "Renesas SMARC EVK based on r9a07g043u11"; compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; + + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7513_out>; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + + status = "okay"; + + port { + du_out_rgb: endpoint { + remote-endpoint = <&adv7513_in>; + }; + }; +}; + +&i2c1 { + adv7513: adv7513@39 { + compatible = "adi,adv7513"; + reg = <0x39>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + dvdd-3v-supply = <®_3p3v>; + bgvdd-supply = <®_1p8v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7513_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + + adv7513_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + +&pinctrl { + du_pins: du { + data { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <2>; + }; + + sync { + pinmux = , /* HSYNC */ + ; /* VSYNC */ + drive-strength = <2>; + }; + + de { + pinmux = ; /* DE */ + drive-strength = <2>; + }; + + clk { + pinmux = ; /* CLK */ + }; + }; };