From patchwork Mon Aug 5 21:10:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawel Dembicki X-Patchwork-Id: 13754071 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0DEC143C4B; Mon, 5 Aug 2024 21:11:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722892263; cv=none; b=RdwUtVOO8f4dxHV9yd0+tXOkZ9jklCBUsutpZ1TB9WmGG5AJ/j1ZsHLX4LZ04HoEzJBQSLya0FP7t3r2YierXgAyx/mcgw9cIfD4i+iG2lu0YdDH36JbOQeZ4ocK6KOc0vj8TgJBXQMfeVV29a0EgAvh4NN0jJw8iaFcfG+N4po= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722892263; c=relaxed/simple; bh=7h5cZFkaufJdb0vRMkLXtHFo6e61k7QkyKt6QNDFMvU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eHGlH3buckeNd+uFDaOe5Shembb1L3y6LOgwLamr33DGyxyvMYbQ91ccWWwlbwkRXrkJHRKSXcHWcCqLuRWxmEJQ0BBFOECBr63WxS08rupAmE5dowdsm4UTQNsjNvl+GUH5RVlbC9yuCeecYQY8+V00wA2j04sGezB6y9CbrXA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JMEXwRhX; arc=none smtp.client-ip=209.85.208.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JMEXwRhX" Received: by mail-lj1-f181.google.com with SMTP id 38308e7fff4ca-2ef248ab2aeso56371fa.0; Mon, 05 Aug 2024 14:11:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722892260; x=1723497060; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0FkeNGgxLJlDCBPLBLDTnDJd9fYpQKo2t2Ld/HlDRnE=; b=JMEXwRhXJUCopI5gWjce8SYmtMfW2Ub6HQEF62a3UB1bZnJy9hq8TG49uOXQXTvv5+ xBY275adoQJLVcj7h/DaSn+f34ueRAq0E2tkRfAhdDQNo5OUgUYbextGrpjgonLESRRz w5gujBBdDJ11ipDG5whBa75LLKN/ZeNKsonu1BCRXWycpUMNXrzNiE9Lz1sEJelV2UlY Nc1jcBj1Cn0DYW0I2TA7tcqdRTv6izud9gUm1qJDIx0/l+Iu5rRGCxrAFWGmRDJiD29A R/t86QPqapRp0iSbXSmveBD3VE64d0rH7AMS7ULyFUPn9uJY5+5p8RhU6QTH1y/5hxMW RliQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722892260; x=1723497060; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0FkeNGgxLJlDCBPLBLDTnDJd9fYpQKo2t2Ld/HlDRnE=; b=JZdRNxKdOuOyjpvwfdVWewR5ldPQ2oMEpU23ZfL5eLknA3ihNk6bTR/KSu9TVBw+PA CQqTNBAvBsjr8N2MsX2e/FKRYef4YqJAGLQzHHlB1YsWKyGv7v4t4bhjcH1Is6TzjInc cEQ+OOfCYI3xw9Ua1x1FL+IpJ7Qc/+8dvdA76IaeQgGbazgjJsU3eCUGwku4gaiTD1+M IN40z6BN0To8kFtfMV5buWECE+UJu5QPnCPVM8SW2OQzQ5pkq1KBNVym3WVlpT4JYIP+ qUXlfXchWZwG7pCgp8cAURkdoKw0y2oCB2tIhq37WBYXrWpb8DQ2AnOhmxi2uWNt9ULP G2Uw== X-Forwarded-Encrypted: i=1; AJvYcCVa4/FOYFQs8qVwUlETMNUDH9B3yfFE3M6ETLd2GKxBbJXqDZsY8fk4fNqbDf5zEYC2z4Dyoz7tdrsCYqXbu9/eIg9utXgLqSjzP6Oi X-Gm-Message-State: AOJu0YxNcns3bcSp8lEEBEPXU2qnwePk1s396bEv10TfVX3CDBwdJifq 0ywI4P3B23IEzSBlo8YoP6cyAH1I3VBPE/7pdP6PW/4OQA+wpkn+9sLSY1Ul X-Google-Smtp-Source: AGHT+IGJ8JS4rvgadwcvP7Di1O6ysebb1EmrHLM37Mv6wVLiQBPM7jIY6/aObAFLb9So+6MhQ3UH/g== X-Received: by 2002:a2e:8050:0:b0:2ef:c8a1:ff4 with SMTP id 38308e7fff4ca-2f15aa88b8fmr104722711fa.7.1722892259217; Mon, 05 Aug 2024 14:10:59 -0700 (PDT) Received: from WBEC325.dom.lan ([2001:470:608f:0:1688:6c25:c8e4:9968]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2f15e1c623csm11875291fa.63.2024.08.05.14.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 14:10:58 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Linus Walleij , Florian Fainelli , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net v2 1/5] net: dsa: vsc73xx: fix port MAC configuration in full duplex mode Date: Mon, 5 Aug 2024 23:10:27 +0200 Message-Id: <20240805211031.1689134-2-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240805211031.1689134-1-paweldembicki@gmail.com> References: <20240805211031.1689134-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org According to the datasheet description ("Port Mode Procedure" in 5.6.2), the VSC73XX_MAC_CFG_WEXC_DIS bit is configured only for half duplex mode. The WEXC_DIS bit is responsible for MAC behavior after an excessive collision. Let's set it as described in the datasheet. Fixes: 05bd97fc559d ("net: dsa: Add Vitesse VSC73xx DSA router driver") Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli Signed-off-by: Pawel Dembicki --- v2: - Added 'Fixes' and 'Reviewed-by' to commit message. This patch came from net-next series[0]. Changes since net-next: - rebased to netdev/main only [0] https://patchwork.kernel.org/project/netdevbpf/patch/20240729210615.279952-6-paweldembicki@gmail.com/ --- drivers/net/dsa/vitesse-vsc73xx-core.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index d9d3e30fd47a..f548ed4cb23f 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -957,6 +957,11 @@ static void vsc73xx_mac_link_up(struct phylink_config *config, if (duplex == DUPLEX_FULL) val |= VSC73XX_MAC_CFG_FDX; + else + /* In datasheet description ("Port Mode Procedure" in 5.6.2) + * this bit is configured only for half duplex. + */ + val |= VSC73XX_MAC_CFG_WEXC_DIS; /* This routine is described in the datasheet (below ARBDISC register * description) @@ -967,7 +972,6 @@ static void vsc73xx_mac_link_up(struct phylink_config *config, get_random_bytes(&seed, 1); val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; val |= VSC73XX_MAC_CFG_SEED_LOAD; - val |= VSC73XX_MAC_CFG_WEXC_DIS; /* Those bits are responsible for MTU only. Kernel takes care about MTU, * let's enable +8 bytes frame length unconditionally. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net v2 2/5] net: dsa: vsc73xx: pass value in phy_write operation Date: Mon, 5 Aug 2024 23:10:28 +0200 Message-Id: <20240805211031.1689134-3-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240805211031.1689134-1-paweldembicki@gmail.com> References: <20240805211031.1689134-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org In the 'vsc73xx_phy_write' function, the register value is missing, and the phy write operation always sends zeros. This commit passes the value variable into the proper register. Fixes: 05bd97fc559d ("net: dsa: Add Vitesse VSC73xx DSA router driver") Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli Signed-off-by: Pawel Dembicki --- v2: - Fixed 'Fixes' and added 'Reviewed-by' to commit message This patch came from net-next series[0]. Changes since net-next: - rebased to netdev/main only [0] https://patchwork.kernel.org/project/netdevbpf/patch/20240729210615.279952-6-paweldembicki@gmail.com/ --- drivers/net/dsa/vitesse-vsc73xx-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index f548ed4cb23f..4b300c293dec 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -574,7 +574,7 @@ static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, return 0; } - cmd = (phy << 21) | (regnum << 16); + cmd = (phy << 21) | (regnum << 16) | val; ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); if (ret) return ret; From patchwork Mon Aug 5 21:10:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawel Dembicki X-Patchwork-Id: 13754073 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6EFA14D70B; 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Mon, 05 Aug 2024 14:11:18 -0700 (PDT) Received: from WBEC325.dom.lan ([2001:470:608f:0:1688:6c25:c8e4:9968]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2f15e1c623csm11875291fa.63.2024.08.05.14.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 14:11:18 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Linus Walleij , Florian Fainelli , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net v2 3/5] net: dsa: vsc73xx: check busy flag in MDIO operations Date: Mon, 5 Aug 2024 23:10:29 +0200 Message-Id: <20240805211031.1689134-4-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240805211031.1689134-1-paweldembicki@gmail.com> References: <20240805211031.1689134-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The VSC73xx has a busy flag used during MDIO operations. It is raised when MDIO read/write operations are in progress. Without it, PHYs are misconfigured and bus operations do not work as expected. Fixes: 05bd97fc559d ("net: dsa: Add Vitesse VSC73xx DSA router driver") Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli Signed-off-by: Pawel Dembicki --- v2: - used defines from patch moved to net-next This patch came from net-next series[0]. Changes since net-next: - removed mutex - used method poll.h to poll busy value in 'vsc73xx_mdio_busy_check' - use 'vsc73xx_mdio_busy_check' for control if mdio is ready [0] https://patchwork.kernel.org/project/netdevbpf/patch/20240729210615.279952-6-paweldembicki@gmail.com/ --- drivers/net/dsa/vitesse-vsc73xx-core.c | 40 ++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index 4b300c293dec..a9378e0512d8 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -40,6 +40,10 @@ #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */ #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ +/* MII Block subblock */ +#define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */ +#define VSC73XX_BLOCK_MII_EXTERNAL 0x1 /* External MDIO subblock */ + #define CPU_PORT 6 /* CPU port */ /* MAC Block registers */ @@ -225,6 +229,8 @@ #define VSC73XX_MII_CMD 0x1 #define VSC73XX_MII_DATA 0x2 +#define VSC73XX_MII_STAT_BUSY BIT(3) + /* Arbiter block 5 registers */ #define VSC73XX_ARBEMPTY 0x0c #define VSC73XX_ARBDISC 0x0e @@ -299,6 +305,7 @@ #define IS_739X(a) (IS_7395(a) || IS_7398(a)) #define VSC73XX_POLL_SLEEP_US 1000 +#define VSC73XX_MDIO_POLL_SLEEP_US 5 #define VSC73XX_POLL_TIMEOUT_US 10000 struct vsc73xx_counter { @@ -527,6 +534,22 @@ static int vsc73xx_detect(struct vsc73xx *vsc) return 0; } +static int vsc73xx_mdio_busy_check(struct vsc73xx *vsc) +{ + int ret, err; + u32 val; + + ret = read_poll_timeout(vsc73xx_read, err, + err < 0 || !(val & VSC73XX_MII_STAT_BUSY), + VSC73XX_MDIO_POLL_SLEEP_US, + VSC73XX_POLL_TIMEOUT_US, false, vsc, + VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, + VSC73XX_MII_STAT, &val); + if (ret) + return ret; + return err; +} + static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) { struct vsc73xx *vsc = ds->priv; @@ -534,13 +557,22 @@ static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) u32 val; int ret; + ret = vsc73xx_mdio_busy_check(vsc); + if (ret) + return ret; + /* Setting bit 26 means "read" */ cmd = BIT(26) | (phy << 21) | (regnum << 16); ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); if (ret) return ret; - msleep(2); + + ret = vsc73xx_mdio_busy_check(vsc); + if (ret) + return ret; + ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); + if (ret) return ret; if (val & BIT(16)) { @@ -561,7 +593,11 @@ static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, { struct vsc73xx *vsc = ds->priv; u32 cmd; - int ret; + int ret = 0; + + ret = vsc73xx_mdio_busy_check(vsc); + if (ret) + return ret; /* It was found through tedious experiments that this router * chip really hates to have it's PHYs reset. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net v2 4/5] net: dsa: vsc73xx: allow phy resetting Date: Mon, 5 Aug 2024 23:10:30 +0200 Message-Id: <20240805211031.1689134-5-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240805211031.1689134-1-paweldembicki@gmail.com> References: <20240805211031.1689134-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Resetting the VSC73xx PHY was problematic because the MDIO bus, without a busy check, read and wrote incorrect register values. My investigation indicates that resetting the PHY only triggers changes in configuration. However, improper register values written earlier were only exposed after a soft reset. The reset itself wasn't the issue; rather, the problem stemmed from incorrect read and write operations. A 'soft_reset' can now proceed normally. There are no reasons to keep the VSC73xx from being reset. This commit removes the reset blockade in the 'vsc73xx_phy_write' function. Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli Signed-off-by: Pawel Dembicki --- v2: - improved commit description This patch came from net-next series[0]. Changes since net-next: - rebased to netdev/main only [0] https://patchwork.kernel.org/project/netdevbpf/patch/20240729210615.279952-6-paweldembicki@gmail.com/ --- drivers/net/dsa/vitesse-vsc73xx-core.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c index a9378e0512d8..ac02927a153b 100644 --- a/drivers/net/dsa/vitesse-vsc73xx-core.c +++ b/drivers/net/dsa/vitesse-vsc73xx-core.c @@ -599,17 +599,6 @@ static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, if (ret) return ret; - /* It was found through tedious experiments that this router - * chip really hates to have it's PHYs reset. They - * never recover if that happens: autonegotiation stops - * working after a reset. Just filter out this command. - * (Resetting the whole chip is OK.) - */ - if (regnum == 0 && (val & BIT(15))) { - dev_info(vsc->dev, "reset PHY - disallowed\n"); - return 0; - } - cmd = (phy << 21) | (regnum << 16) | val; ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); if (ret) From patchwork Mon Aug 5 21:10:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawel Dembicki X-Patchwork-Id: 13754075 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 928AD16EC18; Mon, 5 Aug 2024 21:11:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722892290; cv=none; b=TxTlKHrYU9LiUMd7E9GQjWKuXKMAb8ZQX3WmutRKjheG9a5lawgHvdoyh6luwI5deu4UXfcC9cCKziAtMbsOxHR1MlrpTkA+feeSuSI3QTiTDy7giKlSu55japEEbDaIwiZPx22z/cTsR1R/FwQY6SSJMmlEp+DN3ZwBkZsROPg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722892290; c=relaxed/simple; bh=f1rYUehadIPkjV7s9GujD6nHmJnb7l1ocKF57qzrzIE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uSvqT4FnYuvb4Tx2KmnnDMEVRtyAqaFKaIB6BodKbkCsSwBonnZaJ3GNU18A0V4eLUmA6uSqEhllFjX+NUkopmeOR+Xqj1KpUJy7u8Ko1LQoLjz9n2LTpKe1BR7mHOmCXaf3kuk6QKUcllWkZpnTP/PH6cWdLaefo/p7YBFng1g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OUkH89uR; arc=none smtp.client-ip=209.85.208.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OUkH89uR" Received: by mail-lj1-f182.google.com with SMTP id 38308e7fff4ca-2ef2fbf1d14so58035571fa.1; Mon, 05 Aug 2024 14:11:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722892286; x=1723497086; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Epvcj2yDIcXIH/BhUb2YswgxSjmOdDD9OTNEx4OZgTU=; b=OUkH89uReC0l2Wm+2Z4u7uqeK3H+xk+6ma8izjg5MciSx3CJf1uYEsbzfjAqX+aA/2 i+omLBP4B1yDcnYONG4tInn9j9yhs6afIJrDOI1DokaJFOaZCSvBhaNO/hq3G/cDMQar z+6MZstkuykqlPRd0h+Yjdr55QNlX46n4GP3JcPAE+A9I/AQ6Ml3XqEnuHLTjJXf6Yq1 dHPUq+t/L1QO+X0R16rsKFkW5hMEiX+cBvdRbXByuHfMZsDzy18juskF9KlGC/ZWmkgR NWBqE5DmeLVF4B6iZPa5BKxmvqIdok5FRiOnBzGQBU5Xbcl2ScMIKd0ulUGILP6boXwF epjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722892286; x=1723497086; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Epvcj2yDIcXIH/BhUb2YswgxSjmOdDD9OTNEx4OZgTU=; b=Vy4FZ/QHkm9tQ9kwA1sKyi8IKbKEc/Rb13jk4BGUvc8r145FiDVRfqnc89MMbfHihs cKYZGtOBDm1AL6j9FEH8IydL5VRMxl8JBX5M3em7VWorTV+JxcDD2J3B/EC5HtLU97df kqTBCv3zs9Ev3mvskoXYHJy1GFLYqcLZ66JSgdehgEUav9u8HSKiRwBVw6YSvOoOxXGb W/HSMPGfTvMH8CTtZg/eNKb2p/1f0cNazHkDr38MuDyLTR7arzO9kRGSEmfFZDWMLvrd R2ZQYDd7oDyhtMqn2Uk5ETmepETEmmnwp2cL6mx98EvsfK9Aluo/jwUGjieOGhbmytfe nwPw== X-Forwarded-Encrypted: i=1; AJvYcCV3hsIpLeFpI3hLLiC0XCNZuXOMy/5ahJGNrgFQk5+HsbhSf/4rZ7sDjkwOmdv+/VK5AR7hxuNuFPMvWfMWG+dgPutOb2c0AF2kuzDG X-Gm-Message-State: AOJu0Yxb0f3dBSMJEfqECi/hKaAAfFFLWkdabu8ATBtz1QHM7sySf/vC YsbJeYOOPPDove5h55oLMxPG5dpkynJNw/KXJgiNIjzYYrfCXT+31V8pUwmI X-Google-Smtp-Source: AGHT+IH19P2uVE0wChBFrm6lKgC+LhvZ5vlEdyEgeMza4OaCOMm8cST1J4GzQ0H2oDbOJjt47jdukw== X-Received: by 2002:a2e:9450:0:b0:2f0:2026:3f71 with SMTP id 38308e7fff4ca-2f15763aa5bmr42218151fa.8.1722892286015; Mon, 05 Aug 2024 14:11:26 -0700 (PDT) Received: from WBEC325.dom.lan ([2001:470:608f:0:1688:6c25:c8e4:9968]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2f15e1c623csm11875291fa.63.2024.08.05.14.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 14:11:25 -0700 (PDT) From: Pawel Dembicki To: netdev@vger.kernel.org Cc: Pawel Dembicki , Linus Walleij , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net v2 5/5] net: phy: vitesse: repair vsc73xx autonegotiation Date: Mon, 5 Aug 2024 23:10:31 +0200 Message-Id: <20240805211031.1689134-6-paweldembicki@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240805211031.1689134-1-paweldembicki@gmail.com> References: <20240805211031.1689134-1-paweldembicki@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org When the vsc73xx mdio bus work properly, the generic autonegotiation configuration works well. Vsc73xx have auto MDI-X disabled by default in forced mode. This commit enables it. Reviewed-by: Linus Walleij Signed-off-by: Pawel Dembicki --- This patch came from net-next series[0]. Changes since net-next: - rebased to netdev/main only [0] https://patchwork.kernel.org/project/netdevbpf/patch/20240729210615.279952-6-paweldembicki@gmail.com/ --- drivers/net/phy/vitesse.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 897b979ec03c..19b7bf189be5 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -60,6 +60,11 @@ /* Vitesse Extended Page Access Register */ #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f +/* VSC73XX PHY_BYPASS_CTRL register*/ +#define MII_VSC73XX_PHY_BYPASS_CTRL MII_DCOUNTER +#define MII_PBC_FORCED_SPEED_AUTO_MDIX_DIS BIT(7) +#define MII_VSC73XX_PBC_AUTO_NP_EXCHANGE_DIS BIT(1) + /* Vitesse VSC8601 Extended PHY Control Register 1 */ #define MII_VSC8601_EPHY_CTL 0x17 #define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8) @@ -239,12 +244,20 @@ static int vsc739x_config_init(struct phy_device *phydev) static int vsc73xx_config_aneg(struct phy_device *phydev) { - /* The VSC73xx switches does not like to be instructed to - * do autonegotiation in any way, it prefers that you just go - * with the power-on/reset defaults. Writing some registers will - * just make autonegotiation permanently fail. - */ - return 0; + int ret; + + /* Enable Auto MDI-X in forced 10/100 mode */ + if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) { + ret = genphy_setup_forced(phydev); + + if (ret < 0) /* error */ + return ret; + + return phy_clear_bits(phydev, MII_VSC73XX_PHY_BYPASS_CTRL, + MII_PBC_FORCED_SPEED_AUTO_MDIX_DIS); + } + + return genphy_config_aneg(phydev); } /* This adds a skew for both TX and RX clocks, so the skew should only be