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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9ecb129sm544015566b.222.2024.08.06.05.52.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 01/28] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState Date: Tue, 6 Aug 2024 14:51:29 +0200 Message-ID: <20240806125157.91185-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao We'll have to add LoongsonIPIClass in few commits, so rename LoongsonIPI as LoongsonIPIState for clarity. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-2-philmd@linaro.org> --- include/hw/intc/loongson_ipi.h | 6 +++--- hw/intc/loongson_ipi.c | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 3f795edbf3..efb772f384 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -31,10 +31,10 @@ #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" -OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI) +OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI) typedef struct IPICore { - LoongsonIPI *ipi; + LoongsonIPIState *ipi; MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; @@ -45,7 +45,7 @@ typedef struct IPICore { qemu_irq irq; } IPICore; -struct LoongsonIPI { +struct LoongsonIPIState { SysBusDevice parent_obj; MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 682cec96f3..903483ae80 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { - LoongsonIPI *ipi = opaque; + LoongsonIPIState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, MemTxAttrs attrs) { IPICore *s = opaque; - LoongsonIPI *ipi = s->ipi; + LoongsonIPIState *ipi = s->ipi; int index = 0; uint32_t cpuid; uint8_t vector; @@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { - LoongsonIPI *ipi = opaque; + LoongsonIPIState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { static void loongson_ipi_realize(DeviceState *dev, Error **errp) { - LoongsonIPI *s = LOONGSON_IPI(dev); + LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; @@ -320,7 +320,7 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) static void loongson_ipi_unrealize(DeviceState *dev) { - LoongsonIPI *s = LOONGSON_IPI(dev); + LoongsonIPIState *s = LOONGSON_IPI(dev); g_free(s->cpu); } @@ -344,14 +344,14 @@ static const VMStateDescription vmstate_loongson_ipi = { .version_id = 2, .minimum_version_id = 2, .fields = (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu, + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu, vmstate_ipi_core, IPICore), VMSTATE_END_OF_LIST() } }; static Property ipi_properties[] = { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1), + DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -369,7 +369,7 @@ static const TypeInfo loongson_ipi_types[] = { { .name = TYPE_LOONGSON_IPI, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LoongsonIPI), + .instance_size = sizeof(LoongsonIPIState), .class_init = loongson_ipi_class_init, } }; From patchwork Tue Aug 6 12:51:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 776D7C49EA1 for ; Tue, 6 Aug 2024 12:52:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJfj-0005KG-Uw; Tue, 06 Aug 2024 08:52:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJfj-0005Hj-AZ for qemu-devel@nongnu.org; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9bc3cf3sm556585666b.13.2024.08.06.05.52.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 02/28] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize() Date: Tue, 6 Aug 2024 14:51:30 +0200 Message-ID: <20240806125157.91185-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=philmd@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao In preparation to extract common IPI code in few commits, extract loongson_ipi_common_realize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-3-philmd@linaro.org> --- hw/intc/loongson_ipi.c | 40 ++++++++++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 903483ae80..8aab7e48e8 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -275,7 +275,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static void loongson_ipi_realize(DeviceState *dev, Error **errp) +static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) { LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -301,30 +301,46 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); s->cpu = g_new0(IPICore, s->num_cpu); - if (s->cpu == NULL) { - error_setg(errp, "Memory allocation for IPICore faile"); - return; - } - for (i = 0; i < s->num_cpu; i++) { s->cpu[i].ipi = s; - s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); - g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); - memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), - &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); - sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); } } -static void loongson_ipi_unrealize(DeviceState *dev) +static void loongson_ipi_realize(DeviceState *dev, Error **errp) +{ + LoongsonIPIState *s = LOONGSON_IPI(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + Error *local_err = NULL; + + loongson_ipi_common_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + for (unsigned i = 0; i < s->num_cpu; i++) { + s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); + g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); + memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); + sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + } +} + +static void loongson_ipi_common_unrealize(DeviceState *dev) { LoongsonIPIState *s = LOONGSON_IPI(dev); g_free(s->cpu); } +static void loongson_ipi_unrealize(DeviceState *dev) +{ + loongson_ipi_common_unrealize(dev); +} + static const VMStateDescription vmstate_ipi_core = { .name = "ipi-single", .version_id = 2, From patchwork Tue Aug 6 12:51:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E41D4C49EA1 for ; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9ec7266sm547817866b.196.2024.08.06.05.52.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 03/28] hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub Date: Tue, 6 Aug 2024 14:51:31 +0200 Message-ID: <20240806125157.91185-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-4-philmd@linaro.org> --- MAINTAINERS | 4 ++++ include/hw/intc/loongson_ipi.h | 14 ++++++++++++-- include/hw/intc/loongson_ipi_common.h | 26 ++++++++++++++++++++++++++ hw/intc/loongson_ipi.c | 10 +++++++--- hw/intc/loongson_ipi_common.c | 22 ++++++++++++++++++++++ hw/intc/Kconfig | 4 ++++ hw/intc/meson.build | 1 + 7 files changed, 76 insertions(+), 5 deletions(-) create mode 100644 include/hw/intc/loongson_ipi_common.h create mode 100644 hw/intc/loongson_ipi_common.c diff --git a/MAINTAINERS b/MAINTAINERS index e34c2bd4cd..5ca701cf0c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1250,8 +1250,10 @@ F: configs/devices/loongarch64-softmmu/default.mak F: hw/loongarch/ F: include/hw/loongarch/virt.h F: include/hw/intc/loongarch_*.h +F: include/hw/intc/loongson_ipi_common.h F: include/hw/intc/loongson_ipi.h F: hw/intc/loongarch_*.c +F: hw/intc/loongson_ipi_common.c F: hw/intc/loongson_ipi.c F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c @@ -1386,11 +1388,13 @@ Loongson-3 virtual platforms M: Huacai Chen R: Jiaxun Yang S: Maintained +F: hw/intc/loongson_ipi_common.c F: hw/intc/loongson_ipi.c F: hw/intc/loongson_liointc.c F: hw/mips/loongson3_bootp.c F: hw/mips/loongson3_bootp.h F: hw/mips/loongson3_virt.c +F: include/hw/intc/loongson_ipi_common.h F: include/hw/intc/loongson_ipi.h F: include/hw/intc/loongson_liointc.h F: tests/avocado/machine_mips_loongson3v.py diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index efb772f384..9c9030761e 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -8,6 +8,8 @@ #ifndef HW_LOONGSON_IPI_H #define HW_LOONGSON_IPI_H +#include "qom/object.h" +#include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" /* Mainy used by iocsr read and write */ @@ -31,7 +33,7 @@ #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" -OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI) +OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) typedef struct IPICore { LoongsonIPIState *ipi; @@ -45,8 +47,16 @@ typedef struct IPICore { qemu_irq irq; } IPICore; +struct LoongsonIPIClass { + LoongsonIPICommonClass parent_class; + + DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; +}; + struct LoongsonIPIState { - SysBusDevice parent_obj; + LoongsonIPICommonState parent_obj; + MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; uint32_t num_cpu; diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h new file mode 100644 index 0000000000..70ac69d0ba --- /dev/null +++ b/include/hw/intc/loongson_ipi_common.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson ipi interrupt header files + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGSON_IPI_COMMON_H +#define HW_LOONGSON_IPI_COMMON_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" +OBJECT_DECLARE_TYPE(LoongsonIPICommonState, + LoongsonIPICommonClass, LOONGSON_IPI_COMMON) + +struct LoongsonIPICommonState { + SysBusDevice parent_obj; +}; + +struct LoongsonIPICommonClass { + SysBusDeviceClass parent_class; +}; + +#endif diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 8aab7e48e8..7d15c28e94 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -374,9 +374,12 @@ static Property ipi_properties[] = { static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass); - dc->realize = loongson_ipi_realize; - dc->unrealize = loongson_ipi_unrealize; + device_class_set_parent_realize(dc, loongson_ipi_realize, + &lic->parent_realize); + device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, + &lic->parent_unrealize); device_class_set_props(dc, ipi_properties); dc->vmsd = &vmstate_loongson_ipi; } @@ -384,8 +387,9 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) static const TypeInfo loongson_ipi_types[] = { { .name = TYPE_LOONGSON_IPI, - .parent = TYPE_SYS_BUS_DEVICE, + .parent = TYPE_LOONGSON_IPI_COMMON, .instance_size = sizeof(LoongsonIPIState), + .class_size = sizeof(LoongsonIPIClass), .class_init = loongson_ipi_class_init, } }; diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c new file mode 100644 index 0000000000..43002fe556 --- /dev/null +++ b/hw/intc/loongson_ipi_common.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson IPI interrupt common support + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/intc/loongson_ipi_common.h" + +static const TypeInfo loongarch_ipi_common_types[] = { + { + .name = TYPE_LOONGSON_IPI_COMMON, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(LoongsonIPICommonState), + .class_size = sizeof(LoongsonIPICommonClass), + .abstract = true, + } +}; + +DEFINE_TYPES(loongarch_ipi_common_types) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 58b6d3a710..a2a0fdca85 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -87,8 +87,12 @@ config GOLDFISH_PIC config M68K_IRQC bool +config LOONGSON_IPI_COMMON + bool + config LOONGSON_IPI bool + select LOONGSON_IPI_COMMON config LOONGARCH_PCH_PIC bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index afd1aa51ee..a09a527207 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -69,6 +69,7 @@ specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) +specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c')) From patchwork Tue Aug 6 12:51:32 2024 Content-Type: text/plain; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e8383dsm551798066b.173.2024.08.06.05.52.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 04/28] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h Date: Tue, 6 Aug 2024 14:51:32 +0200 Message-ID: <20240806125157.91185-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=philmd@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-5-philmd@linaro.org> --- include/hw/intc/loongson_ipi.h | 18 ------------------ include/hw/intc/loongson_ipi_common.h | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 9c9030761e..70e00dc1a7 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -12,24 +12,6 @@ #include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" -/* Mainy used by iocsr read and write */ -#define SMP_IPI_MAILBOX 0x1000ULL -#define CORE_STATUS_OFF 0x0 -#define CORE_EN_OFF 0x4 -#define CORE_SET_OFF 0x8 -#define CORE_CLEAR_OFF 0xc -#define CORE_BUF_20 0x20 -#define CORE_BUF_28 0x28 -#define CORE_BUF_30 0x30 -#define CORE_BUF_38 0x38 -#define IOCSR_IPI_SEND 0x40 -#define IOCSR_MAIL_SEND 0x48 -#define IOCSR_ANY_SEND 0x158 - -#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) -#define MAIL_SEND_OFFSET 0 -#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) - #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 70ac69d0ba..b43b77bda6 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -23,4 +23,23 @@ struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; }; +/* Mainy used by iocsr read and write */ +#define SMP_IPI_MAILBOX 0x1000ULL + +#define CORE_STATUS_OFF 0x0 +#define CORE_EN_OFF 0x4 +#define CORE_SET_OFF 0x8 +#define CORE_CLEAR_OFF 0xc +#define CORE_BUF_20 0x20 +#define CORE_BUF_28 0x28 +#define CORE_BUF_30 0x30 +#define CORE_BUF_38 0x38 +#define IOCSR_IPI_SEND 0x40 +#define IOCSR_MAIL_SEND 0x48 +#define IOCSR_ANY_SEND 0x158 + +#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) +#define MAIL_SEND_OFFSET 0 +#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) + #endif From patchwork Tue Aug 6 12:51:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12954C49EA1 for ; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9bcb19csm544275866b.42.2024.08.06.05.52.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 05/28] hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState Date: Tue, 6 Aug 2024 14:51:33 +0200 Message-ID: <20240806125157.91185-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=philmd@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao It is easier to manage one array of MMIO MR rather than one per vCPU. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-6-philmd@linaro.org> --- include/hw/intc/loongson_ipi.h | 2 +- hw/intc/loongson_ipi.c | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 70e00dc1a7..5a52dfbf4d 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -19,7 +19,6 @@ OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) typedef struct IPICore { LoongsonIPIState *ipi; - MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; uint32_t set; @@ -39,6 +38,7 @@ struct LoongsonIPIClass { struct LoongsonIPIState { LoongsonIPICommonState parent_obj; + MemoryRegion *ipi_mmio_mem; MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; uint32_t num_cpu; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 7d15c28e94..03878b896f 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -320,12 +320,12 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) return; } + s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu); for (unsigned i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); - memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); - sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); } } @@ -338,6 +338,10 @@ static void loongson_ipi_common_unrealize(DeviceState *dev) static void loongson_ipi_unrealize(DeviceState *dev) { + LoongsonIPIState *s = LOONGSON_IPI(dev); + + g_free(s->ipi_mmio_mem); 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9ecabb2sm541820766b.214.2024.08.06.05.52.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 06/28] hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h Date: Tue, 6 Aug 2024 14:51:34 +0200 Message-ID: <20240806125157.91185-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao Move the IPICore structure and corresponding common fields of LoongsonIPICommonState to "hw/intc/loongson_ipi_common.h". Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-7-philmd@linaro.org> --- include/hw/intc/loongson_ipi.h | 17 --------- include/hw/intc/loongson_ipi_common.h | 18 ++++++++++ hw/intc/loongson_ipi.c | 50 ++++++--------------------- hw/intc/loongson_ipi_common.c | 42 ++++++++++++++++++++++ 4 files changed, 70 insertions(+), 57 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 5a52dfbf4d..4e517cc8dc 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -12,22 +12,9 @@ #include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" -#define IPI_MBX_NUM 4 - #define TYPE_LOONGSON_IPI "loongson_ipi" OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) -typedef struct IPICore { - LoongsonIPIState *ipi; - uint32_t status; - uint32_t en; - uint32_t set; - uint32_t clear; - /* 64bit buf divide into 2 32bit buf */ - uint32_t buf[IPI_MBX_NUM * 2]; - qemu_irq irq; -} IPICore; - struct LoongsonIPIClass { LoongsonIPICommonClass parent_class; @@ -39,10 +26,6 @@ struct LoongsonIPIState { LoongsonIPICommonState parent_obj; MemoryRegion *ipi_mmio_mem; - MemoryRegion ipi_iocsr_mem; - MemoryRegion ipi64_iocsr_mem; - uint32_t num_cpu; - IPICore *cpu; }; #endif diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index b43b77bda6..967c70ad1c 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -11,12 +11,30 @@ #include "qom/object.h" #include "hw/sysbus.h" +#define IPI_MBX_NUM 4 + #define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" OBJECT_DECLARE_TYPE(LoongsonIPICommonState, LoongsonIPICommonClass, LOONGSON_IPI_COMMON) +typedef struct IPICore { + LoongsonIPICommonState *ipi; + uint32_t status; + uint32_t en; + uint32_t set; + uint32_t clear; + /* 64bit buf divide into 2 32-bit buf */ + uint32_t buf[IPI_MBX_NUM * 2]; + qemu_irq irq; +} IPICore; + struct LoongsonIPICommonState { SysBusDevice parent_obj; + + MemoryRegion ipi_iocsr_mem; + MemoryRegion ipi64_iocsr_mem; + uint32_t num_cpu; + IPICore *cpu; }; struct LoongsonIPICommonClass { diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 03878b896f..347bc26729 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { - LoongsonIPIState *ipi = opaque; + LoongsonIPICommonState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, MemTxAttrs attrs) { IPICore *s = opaque; - LoongsonIPIState *ipi = s->ipi; + LoongsonIPICommonState *ipi = s->ipi; int index = 0; uint32_t cpuid; uint8_t vector; @@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { - LoongsonIPIState *ipi = opaque; + LoongsonIPICommonState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) { - LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; @@ -310,6 +310,7 @@ static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) static void loongson_ipi_realize(DeviceState *dev, Error **errp) { + LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev); LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); Error *local_err = NULL; @@ -320,18 +321,19 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) return; } - s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu); - for (unsigned i = 0; i < s->num_cpu; i++) { + s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu); + for (unsigned i = 0; i < sc->num_cpu; i++) { g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); + memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), - &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); + &loongson_ipi_core_ops, &sc->cpu[i], name, 0x48); sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); } } static void loongson_ipi_common_unrealize(DeviceState *dev) { - LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); g_free(s->cpu); } @@ -345,36 +347,6 @@ static void loongson_ipi_unrealize(DeviceState *dev) loongson_ipi_common_unrealize(dev); } -static const VMStateDescription vmstate_ipi_core = { - .name = "ipi-single", - .version_id = 2, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_UINT32(status, IPICore), - VMSTATE_UINT32(en, IPICore), - VMSTATE_UINT32(set, IPICore), - VMSTATE_UINT32(clear, IPICore), - VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription vmstate_loongson_ipi = { - .name = TYPE_LOONGSON_IPI, - .version_id = 2, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu, - vmstate_ipi_core, IPICore), - VMSTATE_END_OF_LIST() - } -}; - -static Property ipi_properties[] = { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), -}; - static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -384,8 +356,6 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) &lic->parent_realize); device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, &lic->parent_unrealize); - device_class_set_props(dc, ipi_properties); - dc->vmsd = &vmstate_loongson_ipi; } static const TypeInfo loongson_ipi_types[] = { diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 43002fe556..47796f7ece 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -8,6 +8,47 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +static const VMStateDescription vmstate_ipi_core = { + .name = "ipi-single", + .version_id = 2, + .minimum_version_id = 2, + .fields = (const VMStateField[]) { + VMSTATE_UINT32(status, IPICore), + VMSTATE_UINT32(en, IPICore), + VMSTATE_UINT32(set, IPICore), + VMSTATE_UINT32(clear, IPICore), + VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_loongson_ipi_common = { + .name = "loongson_ipi", + .version_id = 2, + .minimum_version_id = 2, + .fields = (const VMStateField[]) { + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPICommonState, + num_cpu, vmstate_ipi_core, + IPICore), + VMSTATE_END_OF_LIST() + } +}; + +static Property ipi_common_properties[] = { + DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + device_class_set_props(dc, ipi_common_properties); + dc->vmsd = &vmstate_loongson_ipi_common; +} static const TypeInfo loongarch_ipi_common_types[] = { { @@ -15,6 +56,7 @@ static const TypeInfo loongarch_ipi_common_types[] = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(LoongsonIPICommonState), .class_size = sizeof(LoongsonIPICommonClass), + .class_init = loongson_ipi_common_class_init, .abstract = true, } }; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e83ec1sm545106766b.182.2024.08.06.05.52.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 07/28] hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data() Date: Tue, 6 Aug 2024 14:51:35 +0200 Message-ID: <20240806125157.91185-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao In order to get LoongsonIPICommonClass in send_ipi_data() in the next commit, propagate LoongsonIPICommonState. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-8-philmd@linaro.org> --- hw/intc/loongson_ipi.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 347bc26729..8bf16f26d4 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -88,8 +88,8 @@ static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) return NULL; } -static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, - MemTxAttrs attrs) +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, + uint64_t val, hwaddr addr, MemTxAttrs attrs) { int i, mask = 0, data = 0; AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu); @@ -119,7 +119,8 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, return MEMTX_OK; } -static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) +static MemTxResult mail_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) { uint32_t cpuid; hwaddr addr; @@ -134,10 +135,11 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) /* override requester_id */ addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); attrs.requester_id = cs->cpu_index; - return send_ipi_data(cs, val, addr, attrs); + return send_ipi_data(ipi, cs, val, addr, attrs); } -static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) +static MemTxResult any_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) { uint32_t cpuid; hwaddr addr; @@ -152,7 +154,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) /* override requester_id */ addr = val & 0xffff; attrs.requester_id = cs->cpu_index; - return send_ipi_data(cs, val, addr, attrs); + return send_ipi_data(ipi, cs, val, addr, attrs); } static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, @@ -249,15 +251,16 @@ static const MemoryRegionOps loongson_ipi_iocsr_ops = { static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { + LoongsonIPICommonState *ipi = opaque; MemTxResult ret = MEMTX_OK; addr &= 0xfff; switch (addr) { case MAIL_SEND_OFFSET: - ret = mail_send(val, attrs); + ret = mail_send(ipi, val, attrs); break; case ANY_SEND_OFFSET: - ret = any_send(val, attrs); + ret = any_send(ipi, val, attrs); break; default: break; From patchwork Tue Aug 6 12:51:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C723BC49EA1 for ; Tue, 6 Aug 2024 12:53:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJgQ-000803-6E; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5b83b82c068sm5896520a12.60.2024.08.06.05.52.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 08/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler Date: Tue, 6 Aug 2024 14:51:36 +0200 Message-ID: <20240806125157.91185-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao Allow Loongson IPI implementations to have their own get_iocsr_as() handler. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-9-philmd@linaro.org> --- include/hw/intc/loongson_ipi_common.h | 2 ++ hw/intc/loongson_ipi.c | 16 ++++++++++++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 967c70ad1c..1a2ee41cc9 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -39,6 +39,8 @@ struct LoongsonIPICommonState { struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; + + AddressSpace *(*get_iocsr_as)(CPUState *cpu); }; /* Mainy used by iocsr read and write */ diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 8bf16f26d4..eb99de9068 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -75,24 +75,30 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, return loongson_ipi_core_readl(s, addr, data, size, attrs); } -static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) -{ #ifdef TARGET_LOONGARCH64 +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ return LOONGARCH_CPU(cpu)->env.address_space_iocsr; +} #endif + #ifdef TARGET_MIPS +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { return &MIPS_CPU(cpu)->env.iocsr.as; } -#endif + return NULL; } +#endif static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, uint64_t val, hwaddr addr, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); int i, mask = 0, data = 0; - AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu); + AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); if (!iocsr_as) { return MEMTX_DECODE_ERROR; @@ -354,11 +360,13 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass); + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); device_class_set_parent_realize(dc, loongson_ipi_realize, &lic->parent_realize); device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, &lic->parent_unrealize); + licc->get_iocsr_as = get_iocsr_as; } static const TypeInfo loongson_ipi_types[] = { From patchwork Tue Aug 6 12:51:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B234EC49EA1 for ; Tue, 6 Aug 2024 12:53:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJgY-0000Op-VF; Tue, 06 Aug 2024 08:53:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJgW-0000Cc-2R for qemu-devel@nongnu.org; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e83eccsm543566666b.184.2024.08.06.05.52.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 09/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler Date: Tue, 6 Aug 2024 14:51:37 +0200 Message-ID: <20240806125157.91185-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=philmd@linaro.org; helo=mail-lj1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao Allow Loongson IPI implementations to have their own cpu_by_arch_id() handler. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-10-philmd@linaro.org> --- include/hw/intc/loongson_ipi_common.h | 1 + hw/intc/loongson_ipi.c | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 1a2ee41cc9..8997676f0d 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -41,6 +41,7 @@ struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; AddressSpace *(*get_iocsr_as)(CPUState *cpu); + CPUState *(*cpu_by_arch_id)(int64_t id); }; /* Mainy used by iocsr read and write */ diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index eb99de9068..4a8e743528 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -128,12 +128,13 @@ static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, static MemTxResult mail_send(LoongsonIPICommonState *ipi, uint64_t val, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); uint32_t cpuid; hwaddr addr; CPUState *cs; cpuid = extract32(val, 16, 10); - cs = cpu_by_arch_id(cpuid); + cs = licc->cpu_by_arch_id(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; } @@ -147,12 +148,13 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi, static MemTxResult any_send(LoongsonIPICommonState *ipi, uint64_t val, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); uint32_t cpuid; hwaddr addr; CPUState *cs; cpuid = extract32(val, 16, 10); - cs = cpu_by_arch_id(cpuid); + cs = licc->cpu_by_arch_id(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; } @@ -169,6 +171,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, { IPICore *s = opaque; LoongsonIPICommonState *ipi = s->ipi; + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); int index = 0; uint32_t cpuid; uint8_t vector; @@ -203,7 +206,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, cpuid = extract32(val, 16, 10); /* IPI status vector */ vector = extract8(val, 0, 5); - cs = cpu_by_arch_id(cpuid); + cs = licc->cpu_by_arch_id(cpuid); if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { return MEMTX_DECODE_ERROR; } @@ -367,6 +370,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, &lic->parent_unrealize); licc->get_iocsr_as = get_iocsr_as; + licc->cpu_by_arch_id = cpu_by_arch_id; } static const TypeInfo loongson_ipi_types[] = { From patchwork Tue Aug 6 12:51:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3716C52D73 for ; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9c61575sm546609166b.92.2024.08.06.05.53.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 10/28] hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers Date: Tue, 6 Aug 2024 14:51:38 +0200 Message-ID: <20240806125157.91185-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao In order to access loongson_ipi_core_read/write helpers from loongson_ipi_common.c in the next commit, make their prototype declaration public. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-11-philmd@linaro.org> --- include/hw/intc/loongson_ipi_common.h | 6 ++++++ hw/intc/loongson_ipi.c | 10 ++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 8997676f0d..65f8ef7957 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -10,6 +10,7 @@ #include "qom/object.h" #include "hw/sysbus.h" +#include "exec/memattrs.h" #define IPI_MBX_NUM 4 @@ -44,6 +45,11 @@ struct LoongsonIPICommonClass { CPUState *(*cpu_by_arch_id)(int64_t id); }; +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs); +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs); + /* Mainy used by iocsr read and write */ #define SMP_IPI_MAILBOX 0x1000ULL diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 4a8e743528..c13cb5a1d2 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -24,9 +24,8 @@ #endif #include "trace.h" -static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { IPICore *s = opaque; uint64_t ret = 0; @@ -165,9 +164,8 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi, return send_ipi_data(ipi, cs, val, addr, attrs); } -static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) { IPICore *s = opaque; LoongsonIPICommonState *ipi = s->ipi; From patchwork Tue Aug 6 12:51:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7374C3DA64 for ; Tue, 6 Aug 2024 12:54:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJgs-0001zJ-Hc; Tue, 06 Aug 2024 08:53:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJgj-0001Cq-Bl for qemu-devel@nongnu.org; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5b83c22db88sm5838766a12.95.2024.08.06.05.53.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 11/28] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c Date: Tue, 6 Aug 2024 14:51:39 +0200 Message-ID: <20240806125157.91185-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philmd@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao Move the common code from loongson_ipi.c to loongson_ipi_common.c, call parent_realize() instead of loongson_ipi_common_realize() in loongson_ipi_realize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-12-philmd@linaro.org> --- include/hw/intc/loongson_ipi_common.h | 2 + hw/intc/loongson_ipi.c | 279 +------------------------ hw/intc/loongson_ipi_common.c | 283 ++++++++++++++++++++++++++ 3 files changed, 289 insertions(+), 275 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 65f8ef7957..df9d9c5168 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -41,6 +41,8 @@ struct LoongsonIPICommonState { struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; + DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; AddressSpace *(*get_iocsr_as)(CPUState *cpu); CPUState *(*cpu_by_arch_id)(int64_t id); }; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index c13cb5a1d2..0b88ae3230 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -24,56 +24,6 @@ #endif #include "trace.h" -MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s = opaque; - uint64_t ret = 0; - int index = 0; - - addr &= 0xff; - switch (addr) { - case CORE_STATUS_OFF: - ret = s->status; - break; - case CORE_EN_OFF: - ret = s->en; - break; - case CORE_SET_OFF: - ret = 0; - break; - case CORE_CLEAR_OFF: - ret = 0; - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index = (addr - CORE_BUF_20) >> 2; - ret = s->buf[index]; - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); - break; - } - - trace_loongson_ipi_read(size, (uint64_t)addr, ret); - *data = ret; - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - IPICore *s; - - if (attrs.requester_id >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s = &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_readl(s, addr, data, size, attrs); -} - #ifdef TARGET_LOONGARCH64 static AddressSpace *get_iocsr_as(CPUState *cpu) { @@ -92,148 +42,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) } #endif -static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, - uint64_t val, hwaddr addr, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - int i, mask = 0, data = 0; - AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); - - if (!iocsr_as) { - return MEMTX_DECODE_ERROR; - } - - /* - * bit 27-30 is mask for byte writing, - * if the mask is 0, we need not to do anything. - */ - if ((val >> 27) & 0xf) { - data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); - for (i = 0; i < 4; i++) { - /* get mask for byte writing */ - if (val & (0x1 << (27 + i))) { - mask |= 0xff << (i * 8); - } - } - } - - data &= mask; - data |= (val >> 32) & ~mask; - address_space_stl_le(iocsr_as, addr, data, attrs, NULL); - - return MEMTX_OK; -} - -static MemTxResult mail_send(LoongsonIPICommonState *ipi, - uint64_t val, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id = cs->cpu_index; - return send_ipi_data(ipi, cs, val, addr, attrs); -} - -static MemTxResult any_send(LoongsonIPICommonState *ipi, - uint64_t val, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr = val & 0xffff; - attrs.requester_id = cs->cpu_index; - return send_ipi_data(ipi, cs, val, addr, attrs); -} - -MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s = opaque; - LoongsonIPICommonState *ipi = s->ipi; - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - int index = 0; - uint32_t cpuid; - uint8_t vector; - CPUState *cs; - - addr &= 0xff; - trace_loongson_ipi_write(size, (uint64_t)addr, val); - switch (addr) { - case CORE_STATUS_OFF: - qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); - break; - case CORE_EN_OFF: - s->en = val; - break; - case CORE_SET_OFF: - s->status |= val; - if (s->status != 0 && (s->status & s->en) != 0) { - qemu_irq_raise(s->irq); - } - break; - case CORE_CLEAR_OFF: - s->status &= ~val; - if (s->status == 0 && s->en != 0) { - qemu_irq_lower(s->irq); - } - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index = (addr - CORE_BUF_20) >> 2; - s->buf[index] = val; - break; - case IOCSR_IPI_SEND: - cpuid = extract32(val, 16, 10); - /* IPI status vector */ - vector = extract8(val, 0, 5); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, - BIT(vector), 4, attrs); - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); - break; - } - - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - IPICore *s; - - if (attrs.requester_id >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s = &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_writel(s, addr, val, size, attrs); -} - static const MemoryRegionOps loongson_ipi_core_ops = { .read_with_attrs = loongson_ipi_core_readl, .write_with_attrs = loongson_ipi_core_writel, @@ -244,88 +52,15 @@ static const MemoryRegionOps loongson_ipi_core_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static const MemoryRegionOps loongson_ipi_iocsr_ops = { - .read_with_attrs = loongson_ipi_iocsr_readl, - .write_with_attrs = loongson_ipi_iocsr_writel, - .impl.min_access_size = 4, - .impl.max_access_size = 4, - .valid.min_access_size = 4, - .valid.max_access_size = 8, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -/* mail send and any send only support writeq */ -static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - MemTxResult ret = MEMTX_OK; - - addr &= 0xfff; - switch (addr) { - case MAIL_SEND_OFFSET: - ret = mail_send(ipi, val, attrs); - break; - case ANY_SEND_OFFSET: - ret = any_send(ipi, val, attrs); - break; - default: - break; - } - - return ret; -} - -static const MemoryRegionOps loongson_ipi64_ops = { - .write_with_attrs = loongson_ipi_writeq, - .impl.min_access_size = 8, - .impl.max_access_size = 8, - .valid.min_access_size = 8, - .valid.max_access_size = 8, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) -{ - LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - int i; - - if (s->num_cpu == 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } - - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), - &loongson_ipi_iocsr_ops, - s, "loongson_ipi_iocsr", 0x48); - - /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ - s->ipi_iocsr_mem.disable_reentrancy_guard = true; - - sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); - - memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), - &loongson_ipi64_ops, - s, "loongson_ipi64_iocsr", 0x118); - sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); - - s->cpu = g_new0(IPICore, s->num_cpu); - for (i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi = s; - - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); - } -} - static void loongson_ipi_realize(DeviceState *dev, Error **errp) { LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev); LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPIClass *lic = LOONGSON_IPI_GET_CLASS(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); Error *local_err = NULL; - loongson_ipi_common_realize(dev, &local_err); + lic->parent_realize(dev, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -341,20 +76,14 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) } } -static void loongson_ipi_common_unrealize(DeviceState *dev) -{ - LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); - - g_free(s->cpu); -} - static void loongson_ipi_unrealize(DeviceState *dev) { LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPIClass *k = LOONGSON_IPI_GET_CLASS(dev); g_free(s->ipi_mmio_mem); - loongson_ipi_common_unrealize(dev); + k->parent_unrealize(dev); } static void loongson_ipi_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 47796f7ece..a6ce0181f6 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -8,8 +8,286 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/irq.h" #include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/log.h" #include "migration/vmstate.h" +#include "trace.h" + +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s = opaque; + uint64_t ret = 0; + int index = 0; + + addr &= 0xff; + switch (addr) { + case CORE_STATUS_OFF: + ret = s->status; + break; + case CORE_EN_OFF: + ret = s->en; + break; + case CORE_SET_OFF: + ret = 0; + break; + case CORE_CLEAR_OFF: + ret = 0; + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index = (addr - CORE_BUF_20) >> 2; + ret = s->buf[index]; + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); + break; + } + + trace_loongson_ipi_read(size, (uint64_t)addr, ret); + *data = ret; + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + IPICore *s; + + if (attrs.requester_id >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s = &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_readl(s, addr, data, size, attrs); +} + +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, + uint64_t val, hwaddr addr, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + int i, mask = 0, data = 0; + AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); + + if (!iocsr_as) { + return MEMTX_DECODE_ERROR; + } + + /* + * bit 27-30 is mask for byte writing, + * if the mask is 0, we need not to do anything. + */ + if ((val >> 27) & 0xf) { + data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); + for (i = 0; i < 4; i++) { + /* get mask for byte writing */ + if (val & (0x1 << (27 + i))) { + mask |= 0xff << (i * 8); + } + } + } + + data &= mask; + data |= (val >> 32) & ~mask; + address_space_stl_le(iocsr_as, addr, data, attrs, NULL); + + return MEMTX_OK; +} + +static MemTxResult mail_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid = extract32(val, 16, 10); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); + attrs.requester_id = cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +static MemTxResult any_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid = extract32(val, 16, 10); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr = val & 0xffff; + attrs.requester_id = cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s = opaque; + LoongsonIPICommonState *ipi = s->ipi; + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + int index = 0; + uint32_t cpuid; + uint8_t vector; + CPUState *cs; + + addr &= 0xff; + trace_loongson_ipi_write(size, (uint64_t)addr, val); + switch (addr) { + case CORE_STATUS_OFF: + qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); + break; + case CORE_EN_OFF: + s->en = val; + break; + case CORE_SET_OFF: + s->status |= val; + if (s->status != 0 && (s->status & s->en) != 0) { + qemu_irq_raise(s->irq); + } + break; + case CORE_CLEAR_OFF: + s->status &= ~val; + if (s->status == 0 && s->en != 0) { + qemu_irq_lower(s->irq); + } + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index = (addr - CORE_BUF_20) >> 2; + s->buf[index] = val; + break; + case IOCSR_IPI_SEND: + cpuid = extract32(val, 16, 10); + /* IPI status vector */ + vector = extract8(val, 0, 5); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + BIT(vector), 4, attrs); + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); + break; + } + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + IPICore *s; + + if (attrs.requester_id >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s = &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_writel(s, addr, val, size, attrs); +} + +static const MemoryRegionOps loongson_ipi_iocsr_ops = { + .read_with_attrs = loongson_ipi_iocsr_readl, + .write_with_attrs = loongson_ipi_iocsr_writel, + .impl.min_access_size = 4, + .impl.max_access_size = 4, + .valid.min_access_size = 4, + .valid.max_access_size = 8, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +/* mail send and any send only support writeq */ +static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + MemTxResult ret = MEMTX_OK; + + addr &= 0xfff; + switch (addr) { + case MAIL_SEND_OFFSET: + ret = mail_send(ipi, val, attrs); + break; + case ANY_SEND_OFFSET: + ret = any_send(ipi, val, attrs); + break; + default: + break; + } + + return ret; +} + +static const MemoryRegionOps loongson_ipi64_ops = { + .write_with_attrs = loongson_ipi_writeq, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) +{ + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + int i; + + if (s->num_cpu == 0) { + error_setg(errp, "num-cpu must be at least 1"); + return; + } + + memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), + &loongson_ipi_iocsr_ops, + s, "loongson_ipi_iocsr", 0x48); + + /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ + s->ipi_iocsr_mem.disable_reentrancy_guard = true; + + sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); + + memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), + &loongson_ipi64_ops, + s, "loongson_ipi64_iocsr", 0x118); + sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); + + s->cpu = g_new0(IPICore, s->num_cpu); + for (i = 0; i < s->num_cpu; i++) { + s->cpu[i].ipi = s; + + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); + } +} + +static void loongson_ipi_common_unrealize(DeviceState *dev) +{ + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); + + g_free(s->cpu); +} static const VMStateDescription vmstate_ipi_core = { .name = "ipi-single", @@ -45,7 +323,12 @@ static Property ipi_common_properties[] = { static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); + device_class_set_parent_realize(dc, loongson_ipi_common_realize, + &licc->parent_realize); + device_class_set_parent_unrealize(dc, loongson_ipi_common_unrealize, + &licc->parent_unrealize); device_class_set_props(dc, ipi_common_properties); dc->vmsd = &vmstate_loongson_ipi_common; } From patchwork Tue Aug 6 12:51:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E408C52D70 for ; Tue, 6 Aug 2024 12:53:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJgt-0002Dd-TO; Tue, 06 Aug 2024 08:53:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJgm-0001QQ-N6 for qemu-devel@nongnu.org; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9d433fesm553882366b.142.2024.08.06.05.53.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 12/28] hw/intc/loongarch_ipi: Add loongarch IPI support Date: Tue, 6 Aug 2024 14:51:40 +0200 Message-ID: <20240806125157.91185-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao Loongarch IPI is added here, it inherits from class TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can be used when ipi is emulated in userspace with KVM mode. Signed-off-by: Bibo Mao [PMD: Rebased and simplified] Co-Developed-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Signed-off-by: Philippe Mathieu-Daudé Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-13-philmd@linaro.org> --- include/hw/intc/loongarch_ipi.h | 25 ++++++++++++ hw/intc/loongarch_ipi.c | 68 +++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 4 ++ hw/intc/meson.build | 1 + 4 files changed, 98 insertions(+) create mode 100644 include/hw/intc/loongarch_ipi.h create mode 100644 hw/intc/loongarch_ipi.c diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h new file mode 100644 index 0000000000..276b3040a3 --- /dev/null +++ b/include/hw/intc/loongarch_ipi.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch IPI interrupt header files + * + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGARCH_IPI_H +#define HW_LOONGARCH_IPI_H + +#include "qom/object.h" +#include "hw/intc/loongson_ipi_common.h" + +#define TYPE_LOONGARCH_IPI "loongarch_ipi" +OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI) + +struct LoongarchIPIState { + LoongsonIPICommonState parent_obj; +}; + +struct LoongarchIPIClass { + LoongsonIPICommonClass parent_class; +}; + +#endif diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c new file mode 100644 index 0000000000..2ae1a42c46 --- /dev/null +++ b/hw/intc/loongarch_ipi.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch IPI interrupt support + * + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "hw/intc/loongarch_ipi.h" +#include "target/loongarch/cpu.h" + +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ + return LOONGARCH_CPU(cpu)->env.address_space_iocsr; +} + +static int archid_cmp(const void *a, const void *b) +{ + CPUArchId *archid_a = (CPUArchId *)a; + CPUArchId *archid_b = (CPUArchId *)b; + + return archid_a->arch_id - archid_b->arch_id; +} + +static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) +{ + CPUArchId apic_id, *found_cpu; + + apic_id.arch_id = id; + found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, + ms->possible_cpus->len, + sizeof(*ms->possible_cpus->cpus), + archid_cmp); + + return found_cpu; +} + +static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id) +{ + MachineState *machine = MACHINE(qdev_get_machine()); + CPUArchId *archid; + + archid = find_cpu_by_archid(machine, arch_id); + if (archid) { + return CPU(archid->cpu); + } + + return NULL; +} + +static void loongarch_ipi_class_init(ObjectClass *klass, void *data) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); + + licc->get_iocsr_as = get_iocsr_as; + licc->cpu_by_arch_id = loongarch_cpu_by_arch_id; +} + +static const TypeInfo loongarch_ipi_types[] = { + { + .name = TYPE_LOONGARCH_IPI, + .parent = TYPE_LOONGSON_IPI_COMMON, + .class_init = loongarch_ipi_class_init, + } +}; + +DEFINE_TYPES(loongarch_ipi_types) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index a2a0fdca85..dd405bdb5d 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -94,6 +94,10 @@ config LOONGSON_IPI bool select LOONGSON_IPI_COMMON +config LOONGARCH_IPI + bool + select LOONGSON_IPI_COMMON + config LOONGARCH_PCH_PIC bool select UNIMP diff --git a/hw/intc/meson.build b/hw/intc/meson.build index a09a527207..f4d81eb8e4 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -71,6 +71,7 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c')) +specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c')) From patchwork Tue Aug 6 12:51:41 2024 Content-Type: text/plain; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5b83b7245f8sm5968354a12.74.2024.08.06.05.53.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 13/28] hw/loongarch/virt: Replace Loongson IPI with LoongArch IPI Date: Tue, 6 Aug 2024 14:51:41 +0200 Message-ID: <20240806125157.91185-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=philmd@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao Loongarch IPI inherits from class LoongsonIPICommonClass, and it only contains Loongarch 3A5000 virt machine specific interfaces, rather than mix different machine implementations together. Signed-off-by: Bibo Mao [PMD: Rebased] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-14-philmd@linaro.org> --- include/hw/loongarch/virt.h | 1 - hw/loongarch/virt.c | 4 ++-- hw/loongarch/Kconfig | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 603c1cebdb..c373e48f27 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -11,7 +11,6 @@ #include "target/loongarch/cpu.h" #include "hw/boards.h" #include "qemu/queue.h" -#include "hw/intc/loongson_ipi.h" #include "hw/block/flash.h" #include "hw/loongarch/boot.h" diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e592b1b6b7..29040422aa 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -23,7 +23,7 @@ #include "net/net.h" #include "hw/loader.h" #include "elf.h" -#include "hw/intc/loongson_ipi.h" +#include "hw/intc/loongarch_ipi.h" #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" @@ -788,7 +788,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms) */ /* Create IPI device */ - ipi = qdev_new(TYPE_LOONGSON_IPI); + ipi = qdev_new(TYPE_LOONGARCH_IPI); qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 89be737726..0de713a439 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -12,7 +12,7 @@ config LOONGARCH_VIRT select SERIAL select VIRTIO_PCI select PLATFORM_BUS - select LOONGSON_IPI + select LOONGARCH_IPI select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI From patchwork Tue Aug 6 12:51:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7B36C49EA1 for ; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5bb9b99f19fsm205716a12.92.2024.08.06.05.53.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 14/28] hw/intc/loongson_ipi: Restrict to MIPS Date: Tue, 6 Aug 2024 14:51:42 +0200 Message-ID: <20240806125157.91185-15-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=philmd@linaro.org; helo=mail-lj1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bibo Mao Now than LoongArch target can use the TYPE_LOONGARCH_IPI model, restrict TYPE_LOONGSON_IPI to MIPS. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-15-philmd@linaro.org> --- MAINTAINERS | 2 -- hw/intc/loongson_ipi.c | 14 -------------- 2 files changed, 16 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 5ca701cf0c..74a85360fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1251,10 +1251,8 @@ F: hw/loongarch/ F: include/hw/loongarch/virt.h F: include/hw/intc/loongarch_*.h F: include/hw/intc/loongson_ipi_common.h -F: include/hw/intc/loongson_ipi.h F: hw/intc/loongarch_*.c F: hw/intc/loongson_ipi_common.c -F: hw/intc/loongson_ipi.c F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c F: gdb-xml/loongarch*.xml diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 0b88ae3230..8382ceca67 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -16,22 +16,9 @@ #include "exec/address-spaces.h" #include "exec/memory.h" #include "migration/vmstate.h" -#ifdef TARGET_LOONGARCH64 -#include "target/loongarch/cpu.h" -#endif -#ifdef TARGET_MIPS #include "target/mips/cpu.h" -#endif #include "trace.h" -#ifdef TARGET_LOONGARCH64 -static AddressSpace *get_iocsr_as(CPUState *cpu) -{ - return LOONGARCH_CPU(cpu)->env.address_space_iocsr; -} -#endif - -#ifdef TARGET_MIPS static AddressSpace *get_iocsr_as(CPUState *cpu) { if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { @@ -40,7 +27,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) return NULL; } -#endif static const MemoryRegionOps loongson_ipi_core_ops = { .read_with_attrs = loongson_ipi_core_readl, From patchwork Tue Aug 6 12:51:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C6C1C49EA1 for ; Tue, 6 Aug 2024 12:54:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJh5-0004Q5-HN; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9d43920sm542964866b.102.2024.08.06.05.53.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 15/28] hw/sd/sdcard: Explicit dummy byte value Date: Tue, 6 Aug 2024 14:51:43 +0200 Message-ID: <20240806125157.91185-16-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On error the DAT lines are left unmodified to their previous states. QEMU returns 0x00 for convenience. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240730092138.32443-2-philmd@linaro.org> --- hw/sd/sd.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 07cb97d88c..de27e34fc8 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -2478,20 +2478,22 @@ void sd_write_byte(SDState *sd, uint8_t value) uint8_t sd_read_byte(SDState *sd) { /* TODO: Append CRCs */ + const uint8_t dummy_byte = 0x00; uint8_t ret; uint32_t io_len; if (!sd->blk || !blk_is_inserted(sd->blk) || !sd->enable) - return 0x00; + return dummy_byte; if (sd->state != sd_sendingdata_state) { qemu_log_mask(LOG_GUEST_ERROR, "%s: not in Sending-Data state\n", __func__); - return 0x00; + return dummy_byte; } - if (sd->card_status & (ADDRESS_ERROR | WP_VIOLATION)) - return 0x00; + if (sd->card_status & (ADDRESS_ERROR | WP_VIOLATION)) { + return dummy_byte; + } io_len = sd_blk_len(sd); @@ -2517,7 +2519,7 @@ uint8_t sd_read_byte(SDState *sd) if (sd->data_offset == 0) { if (!address_in_range(sd, "READ_MULTIPLE_BLOCK", sd->data_start, io_len)) { - return 0x00; + return dummy_byte; } sd_blk_read(sd, sd->data_start, io_len); } From patchwork Tue Aug 6 12:51:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69E20C3DA64 for ; Tue, 6 Aug 2024 12:56:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJhC-0005Jn-MI; Tue, 06 Aug 2024 08:53:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJhA-00053h-4j for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:53:44 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJh8-0000BY-2u for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:53:43 -0400 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a7a843bef98so62018366b.2 for ; Tue, 06 Aug 2024 05:53:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948820; x=1723553620; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fSCuGHe+AmukzYVW/13LuZhAtRaauQM2euUp0akLJd4=; b=pFbcNHRWTZKYaYVh0tCeTb5UU84l4HQhvSzXnHPChULI55tkvl3HQxSPC/NujbKZRM GhfNl+jAk8curiNNx/ag91Nn8xDZwvdoMTDtzFfBap0rFSdTBIXu6lUVUi7fbYTsog8+ QR8qAQFl1HtwDi+Ql92Eu2nIHX1Wz0cILKfb1/RAQKQ4gUpGfQGFcx/9ZjErQRESzy1i CQHgPAz9xyDOaXp5aGX0/fBwIM06zjsBKIcX1RY5wRqyPawnWQN/xpQY2IQnoUABb5ed hEu4Fh5aF30cP2I1xAAzVtdEq0OsrWovTQcaNcRPjeeCy/fib7ZaGEDOwH6mquRb/d57 hNLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948820; x=1723553620; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fSCuGHe+AmukzYVW/13LuZhAtRaauQM2euUp0akLJd4=; b=FtOky26WFB8fexx10Pk6utQ06Y3V2Xao2YeYv7HxP08PSRXsnkAQlNUlEsGdqz3+fm 1GZ2WhmTYYBCKCGhLnZPwP9hoXaFiOLKERW5k2U55bJrelYBmpuC2pR1L1hLgLwwT/Fu EmdzkRnLEGLUkCoX2X0mTYGtBZqkDgy693rjy8AXhbuUndutam+VwixYyRn2/jgPGFIz a8y8HVvNUI4jCXJkOFB5qz+S4avY8h4QJGUWf/7LDttYRnzV2q7yuuCzyNTQ9HYOkgzh 4F0QV+gvWTy3jGa0lx00VBZOliwrTw+sAC+YRuhdfvDL8LeOoAev++e9B68M55SFtriK KmOg== X-Gm-Message-State: AOJu0Yy9X2Izo1ZEq1xA8E9CxUfEEDe9cFHpBIA1ikAs4K8gzXLBNn0R DIIuQFwMjMtkgpF25OgAWQmxRbKDE7wvYTOEeLXLN9fZDW49+Xd6SR9GEiCbi9NMqak/WinLL00 N X-Google-Smtp-Source: AGHT+IH/qbh6cT/QUfP3qWT8WPfo8GgsqC45i9V/3IaqLMDpJUQ3EKvajzC2OFAwFi4tfeMLDpYTnQ== X-Received: by 2002:a17:906:f598:b0:a7d:e84c:a9e7 with SMTP id a640c23a62f3a-a7de84cb5bbmr539226066b.53.1722948820221; Tue, 06 Aug 2024 05:53:40 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9c0c0e0sm549658566b.67.2024.08.06.05.53.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:39 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Zheyu Ma , Richard Henderson Subject: [PULL 16/28] hw/sd/sdcard: Do not abort when reading DAT lines on invalid cmd state Date: Tue, 6 Aug 2024 14:51:44 +0200 Message-ID: <20240806125157.91185-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Guest should not try to read the DAT lines from invalid command state. If it still insists to do so, return a dummy value. Cc: qemu-stable@nongnu.org Fixes: e2dec2eab0 ("hw/sd/sdcard: Remove default case in read/write on DAT lines") Reported-by: Zheyu Ma Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2454 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240730092138.32443-3-philmd@linaro.org> --- hw/sd/sd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index de27e34fc8..a140a32ccd 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -2540,7 +2540,9 @@ uint8_t sd_read_byte(SDState *sd) break; default: - g_assert_not_reached(); + qemu_log_mask(LOG_GUEST_ERROR, "%s: DAT read illegal for command %s\n", + __func__, sd->last_cmd_name); + return dummy_byte; } return ret; From patchwork Tue Aug 6 12:51:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04771C52D73 for ; Tue, 6 Aug 2024 12:56:17 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJhI-0006CN-V0; Tue, 06 Aug 2024 08:53:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJhF-0005n8-WA for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:53:50 -0400 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJhD-0000H5-SW for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:53:49 -0400 Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-5a156557026so601245a12.2 for ; Tue, 06 Aug 2024 05:53:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948826; x=1723553626; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qVol/losEhIcWq2r2tAtbopJaOl9RLGh9SWaxvA4wzc=; b=J6JVPJ0XQ5uN+ZsELFsdsiDAMrbd0+7F3iDFAT9V+44ciHkgpMAJP7da0u/T36UzlR VHwt+Bd5OAaeXElOsqeYmSClSlihXrkuJlsM+FUY2TAcDUzy1/WcTuv8RRi/GZRl8av3 w3UtEha3VI+eUwXGDY7ndswrP7zUBkhIg2gwStPirONjIedMjWqKYGZ0MPFlSkJ9sMoW 93mpwB1W8uv8QT44exYTH2o8yGgWWnQxwuP2BNltmfyCseL1tWHs/+fHlgxYO2nYJOTo GkDEFK/VyJRfn8oXYSKDwQynxIkfEIkiI+wMWdj7GN9iSVbHR8ODU6a4mymu86j2zSZQ sm3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948826; x=1723553626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qVol/losEhIcWq2r2tAtbopJaOl9RLGh9SWaxvA4wzc=; b=vgFb6tvu+AYeFzIt1pCFCWByxfUN3F3+5qgvEgjvl2e3t/tk93el2y+5gd6nX7ciWj LYRC9AOG/cKRearmVEzRaZExHhFM5VtE+ctuigQikeIfi9k3kzn59xqx0tV2q4LOnkpx /y71Ijx+sQ/wt2MgebIu0X411otemLAw4YadIC9RUxNRZaynBGJ+qFdbGRfmQesHOfWc Tti1edglQ4rTAHt5ogR//HfUGL9qkdbbTBRYo+o9NBMAW7NkXuhcOSlxmW+TjfaT6BLO w/8u8VwxUJzffSBRL8dTH8LPd4yR+JuKg0ImZlYJnXLr6jmUh89FW407ccKQKcA1bHPW ALOg== X-Gm-Message-State: AOJu0YwrdvfdAL1n3JPq+W749GowUsHHoyEmhq8qujy509EVqg0QC5TP EYVg8UjVzwDTlIgdeysVd2b+pXuATxm/5r6h3nlQp+u74taAgqF5GZDy4FCjFZ+FdyfmqKVS8bH z X-Google-Smtp-Source: AGHT+IGHHerP54nv4N2NYCyun0uQwMPHkgF8j7yp/Tgw8ZIHbU1PZuDcHpxJviX7jlEOJ1HcZnjnPw== X-Received: by 2002:a05:6402:31a3:b0:5ba:83d:3294 with SMTP id 4fb4d7f45d1cf-5ba083d343cmr6726452a12.2.1722948825908; Tue, 06 Aug 2024 05:53:45 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5baa6b916b8sm3653114a12.22.2024.08.06.05.53.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Zheyu Ma , Richard Henderson Subject: [PULL 17/28] hw/sd/sdhci: Reset @data_count index on invalid ADMA transfers Date: Tue, 6 Aug 2024 14:51:45 +0200 Message-ID: <20240806125157.91185-18-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=philmd@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We neglected to clear the @data_count index on ADMA error, allowing to trigger assertion in sdhci_read_dataport() or sdhci_write_dataport(). Cc: qemu-stable@nongnu.org Fixes: d7dfca0807 ("hw/sdhci: introduce standard SD host controller") Reported-by: Zheyu Ma Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2455 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240730092138.32443-4-philmd@linaro.org> --- hw/sd/sdhci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index d02c3e3963..8293d83556 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -846,6 +846,7 @@ static void sdhci_do_adma(SDHCIState *s) } } if (res != MEMTX_OK) { + s->data_count = 0; if (s->errintstsen & SDHC_EISEN_ADMAERR) { trace_sdhci_error("Set ADMA error flag"); s->errintsts |= SDHC_EIS_ADMAERR; From patchwork Tue Aug 6 12:51:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 653B2C3DA64 for ; Tue, 6 Aug 2024 12:57:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJhT-0007KG-NU; Tue, 06 Aug 2024 08:54:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJhN-0006t0-NO for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:53:57 -0400 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJhL-0000Jp-Vl for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:53:57 -0400 Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-a7aac70e30dso58972166b.1 for ; Tue, 06 Aug 2024 05:53:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948832; x=1723553632; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QOLg5Vi3ZKfkY84yToih/WZzzIJIKq2Y34KfZXOpYeQ=; b=no95ZLQvcosJocWsWEj/XtQfQt5OhX5b12WmRhZDr2TQi/p5Eyh94yXljaFqM/SMVs upFhbVVwfK+Pj02lYbLGR3IDWzdHB/NKKLITYa6mDZCpBLhwhQP7gBfQnfiW9e4l79F+ 4wERMAefTaPLv2OSSkbY0X+tCyAxIGNkebVBX77O9Srwnmqlxu6jJeoOqb1OH6Ry53o9 OVi15bmJuHQ42fGRHQG0m2ZXIN9XgXBXLJha+l9mkFGJE8UU4+f0WDYk2PTl2sbfFpMj JbaJOnXKtsBPMexIDO0+IbDxl6vZf/8a70L/SbLU+YKQ+FbCJf1R5BHyqB3hlKjYnIS2 2W3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948832; x=1723553632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QOLg5Vi3ZKfkY84yToih/WZzzIJIKq2Y34KfZXOpYeQ=; b=bx3JDFQ8FzvKpgiXlYc9Mc1cHATT2ZT1vMSSmS06R6Pa3cFPXGFsEw2MgmtWiRqq2m t4J9uq8A1EvtIE1UgKNqgxIGHTbLsREjMb4CwV9+gYDZFIt6u9WvLokldTMC0etLesvF zdvl3BKpWdVkF5luUbvw4rwmYi9JErQa/uEUbZBI5dTrrplZflc3pTKa8FekMJfzZWaq Mme+FeRpns9LYlrcojLHwFX2plrwnKoeLmG5w9aRMmsfoKlnKhy/V6BhRX7WCvKe4Q9F rEZorkcyv2nUqYzt43UBUAmWEbvm6H9nKkHL2zBeZjoxrwKmTdz2gUuD2Yxab2cQA1tM g0Hg== X-Gm-Message-State: AOJu0Yy20wbC31CQh4y1I3UwQHy22aBh8u3iBu+7/xiq9n0z8w6qa6O1 h6kWiJZubhAVdzFgDgWVELzxpuUEsblPowskT2aSjmVRqavbCjTlmIsmAYKKRF8JlUVsniINkjR k X-Google-Smtp-Source: AGHT+IGRaM4WMc9qgogB5AShB+bzTSo/cHkQ3V4A+4cH5o1QooY7YebFilHRAhzKUkqJtd4l6SCNXg== X-Received: by 2002:a17:906:d262:b0:a7a:9f78:fef with SMTP id a640c23a62f3a-a7dc5179f86mr1164585766b.45.1722948831676; Tue, 06 Aug 2024 05:53:51 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9c0ca00sm545543866b.68.2024.08.06.05.53.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Kevin Wolf , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 18/28] hw/block/pflash_cfi01: Don't decrement pfl->counter below 0 Date: Tue, 6 Aug 2024 14:51:46 +0200 Message-ID: <20240806125157.91185-19-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Peter Maydell In pflash_write() Coverity points out that we can decrement the unsigned pfl->counter below zero, which makes it wrap around. In fact this is harmless, because if pfl->counter is 0 at this point we also increment pfl->wcycle to 3, and the wcycle == 3 handling doesn't look at counter; the only way back into code which looks at the counter value is via wcycle == 1, which will reinitialize the counter. But it's arguably a little clearer to break early in the "counter == 0" if(), to avoid the decrement-below-zero. Resolves: Coverity CID 1547611 Signed-off-by: Peter Maydell Reviewed-by: Kevin Wolf Message-ID: <20240731143617.3391947-4-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index c8f1cf5a87..2f3d1dd509 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -614,6 +614,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, if (!pfl->counter) { trace_pflash_write(pfl->name, "block write finished"); pfl->wcycle++; + break; } pfl->counter--; From patchwork Tue Aug 6 12:51:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754834 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4B6BC3DA64 for ; Tue, 6 Aug 2024 13:01:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJhX-0007oK-GQ; Tue, 06 Aug 2024 08:54:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJhS-0007Lk-Jj for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:03 -0400 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJhQ-0000K7-OL for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:02 -0400 Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-52fc14d6689so515672e87.1 for ; Tue, 06 Aug 2024 05:53:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948838; x=1723553638; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AMipe/hXLqtb3Ef8XbFqx4kLNXFlOJjSHmZuoVlilTA=; b=M7lEONhJ7UuMoo/Pk40/xnfDfkIbohUZBK37LDkikZYgrUTgICk9WW9OjaUgbIPuuJ DqtJJkkS2nMl6w//T72jOS1AXaMd3jGGpA/z4838SxkL41ytFtAxAH3ukBXDuuneJ0PM E17JWlixB8bnGhK/w+7c2yMvYEjz3Sw+sXSjQo7akuLiJrrLqGsbG6i0heSWbRm2DLDg iUPO8QrUsYFjBOhWVsd5FCHXrFduF85n5ZPr6ZS5+prXw/JRCa9QFezSSpHwhiEg6Qt9 UUIH+LGVeTzALzk+oExwIdO9Ad6k+9GEMA3Bx6hSq2PGMFftXguE0PO4ZsyuEdU2mQO4 d7aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948838; x=1723553638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AMipe/hXLqtb3Ef8XbFqx4kLNXFlOJjSHmZuoVlilTA=; b=p9FI8bzQxHS8aLuvSegv7ybbnBHn9OASF+x8yzzF3SOj3Aq2Zp/oEJ7pNVqkbtlNRQ 7+iQ0bLwiucKDQGmpJMge1izs2UAIHpBRacc1b4dHzaf49X4ifmqAPA6+gcLa09P1kOX Eg0Yo02jzZHXGaARYP894f8n//9rA9eb9jMPNGNzfaPOs3R63IEnGt0ymxlcwuPf8bF9 EU6wbw8mVlrEU7sBFNDh2+irvv2AbC1idjieLyGo7oq90loMnJz/1q+76I/FHylupty7 a9osMi9AB/tYin0qPcWm2P+24JeQKQOHKs8LwGbW1jRkTo1EBVvgTSnSq0mz81qzLzfm RF0g== X-Gm-Message-State: AOJu0Yy0MzCjdze1xLCpHTmZBazX9K0SufKz+f8BLlv2+Zg/wa2KdNxb zHtOOryO6AHZRy2Xome1bEXB/IQRBit4vN1KgD80ewtnLsQ9cWTkZ1BrEGh9HVuUOuKX5DZiLlQ s X-Google-Smtp-Source: AGHT+IH8G0ZoABRlxKVigalJQip/AR4YTB9XiD8/200FTJozro7KFpdNnKVWQEkmHPtGccX+VtEQeQ== X-Received: by 2002:a05:6512:ba9:b0:52e:9481:eaa1 with SMTP id 2adb3069b0e04-530bb37425dmr10667974e87.23.1722948837724; Tue, 06 Aug 2024 05:53:57 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e7fe3csm539363066b.162.2024.08.06.05.53.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Markus Armbruster , Kevin Wolf , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 19/28] hw/ide/atapi: Be explicit that assigning to s->lcyl truncates Date: Tue, 6 Aug 2024 14:51:47 +0200 Message-ID: <20240806125157.91185-20-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Peter Maydell In ide_atapi_cmd_reply_end() we calculate a 16-bit size, and then assign its two halves to s->lcyl and s->hcyl like this: s->lcyl = size; s->hcyl = size >> 8; Coverity warns that the first line here can overflow the 8-bit s->lcyl variable. This is true, and in this case we're deliberately only after the low 8 bits of the value. The code is clearer to both humans and Coverity if we're explicit that we only wanted the low 8 bits, though. Resolves: Coverity CID 1547621 Signed-off-by: Peter Maydell Reviewed-by: Markus Armbruster Reviewed-by: Kevin Wolf Message-ID: <20240731143617.3391947-5-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/ide/atapi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c index fcb6cca157..e82959dc2d 100644 --- a/hw/ide/atapi.c +++ b/hw/ide/atapi.c @@ -265,7 +265,7 @@ void ide_atapi_cmd_reply_end(IDEState *s) byte_count_limit--; size = byte_count_limit; } - s->lcyl = size; + s->lcyl = size & 0xff; s->hcyl = size >> 8; s->elementary_transfer_size = size; /* we cannot transmit more than one sector at a time */ From patchwork Tue Aug 6 12:51:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BD99C52D70 for ; Tue, 6 Aug 2024 13:02:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJhZ-00082e-Jj; Tue, 06 Aug 2024 08:54:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJhX-0007m2-61 for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:07 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJhV-0000KX-8J for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:06 -0400 Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-a7a83a968ddso68664166b.0 for ; Tue, 06 Aug 2024 05:54:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948843; x=1723553643; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T2BNzJT5/rzAun9sis8NChUOI8pg5PZFtzu3546w0iw=; b=luom6VsDG7eJb/MsC2Emug3Dip+gUBk0+vtOqRnikMkTlCSOIYHp8TNeuSQGA3gmuu VXrS5mTGYjt8MLYCHKuTKXxT+eyTD7OnfgyJhT/YsCn8npp/UTuIXrFS7zQuqZ97GqgQ gXcP9D+U/JdccXbFubb7KdSVU0f/sZOJWI048fsCs8Y5ic3ztc/wRwxuWr8aqyWnVSNb L8Bfc8VblSJDMdSyaX1/KlIXLclbHsqRx+KYjMElpasigQud4qpXFqmj1N9HAzbWUIY9 ygUFhhf2UCGEwd6zSAPT4Jj9R3khezu6TCfVzpGx0iSsY42S2sh7snEPNw/+WXZAPkuK 8Nuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948843; x=1723553643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T2BNzJT5/rzAun9sis8NChUOI8pg5PZFtzu3546w0iw=; b=QLCWZr5dDiri+X6FPfCQxfrH4K4XLVpIazSDL7TzTu7xGDJIZQj2CFmtXYRWbkbV3z cWE8Ka3wUJ/y7T7smO4rf0AXSEI+xRKvZyKxKloyvfE57Q9vNhOHnxHvVN1/ln1TClC0 kW5Y+urGDGmCxbA/2IKFAtawSKJs4Wu7cOdLLsgT6vAM93CFnkGAx1APzxu9UwKMsmBa 80H8J1CpeV5rCvrI1ELtlhZ2koZH0F85NKa03CQx7b7miTHGyUg7J9K/t8mrraQhfQr6 U5EbinrSfr7KZGkkLgemWsQV0lpLNzxRlKUGWzMq8WZ7YiBscj57/9N8kEWpwql/Xt7x CskA== X-Gm-Message-State: AOJu0Yw4+vFCftluAr1xHqouh8PgC/C9vHdaqv2F04se/GMbWvvIGnD1 snd4CSBdW6V7vmC8aYaA9pvxIhQ7H2ermgu5oxsg6veLRjjjUIu8T/fL6OmZu0VDNvtnWK0GELc l X-Google-Smtp-Source: AGHT+IG+moa5CelR4wcWKiPrSXr92jlFBykqrBUANqj/NP10lZca8tLDfw7h0yzZPG8/tpjwCGMWHQ== X-Received: by 2002:a17:907:1b10:b0:a7d:3ab9:6a5d with SMTP id a640c23a62f3a-a7dc5130c90mr891231866b.69.1722948843425; Tue, 06 Aug 2024 05:54:03 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9ec7575sm539465766b.205.2024.08.06.05.54.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Markus Armbruster , Kevin Wolf , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 20/28] hw/block/fdc-isa: Assert that isa_fdc_get_drive_max_chs() found something Date: Tue, 6 Aug 2024 14:51:48 +0200 Message-ID: <20240806125157.91185-21-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Peter Maydell Coverity complains about an overflow in isa_fdc_get_drive_max_chs() that can happen if the loop over fd_formats never finds a match, because we initialize *maxc to 0 and then at the end of the function decrement it. This can't ever actually happen because fd_formats has at least one entry for each FloppyDriveType, so we must at least once find a match and update *maxc, *maxh and *maxs. Assert that we did find a match, which should keep Coverity happy and will also detect possible bugs in the data in fd_formats. Resolves: Coverity CID 1547663 Signed-off-by: Peter Maydell Reviewed-by: Markus Armbruster Reviewed-by: Kevin Wolf Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240731143617.3391947-6-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/fdc-isa.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c index e43dc532af..796835f57b 100644 --- a/hw/block/fdc-isa.c +++ b/hw/block/fdc-isa.c @@ -147,6 +147,8 @@ static void isa_fdc_get_drive_max_chs(FloppyDriveType type, uint8_t *maxc, *maxs = fdf->last_sect; } } + /* fd_formats must contain at least one entry per FloppyDriveType */ + assert(*maxc); (*maxc)--; } From patchwork Tue Aug 6 12:51:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2EDDC3DA64 for ; Tue, 6 Aug 2024 13:02:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJi2-0001Ym-2g; Tue, 06 Aug 2024 08:54:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJhg-0000F4-Oa for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:24 -0400 Received: from mail-lj1-x231.google.com ([2a00:1450:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJhb-0000MA-TZ for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:13 -0400 Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2ef32fea28dso6962461fa.2 for ; Tue, 06 Aug 2024 05:54:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948849; x=1723553649; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gv+R0AOxTRNRr/YYta1DbILbzN2/ozjvln37VG+akqw=; b=pMqQlNuhvjAjZ/LZtahOeUPMpwtwcsQFzPfPSHOwHYr8IkA18U5kfNmpnN2Hs9I2Ef fr/v13JgebmIAV/bw843V47ESuhVkL12S4hxqUwtWbAssE0ywieUrlHQaq6HCzf5el2e cRXzgVkOoOwhbP916+veJqzy+OU1gSZWeDyoZfBGrbCGFy58R33bIFDghUpbiwX63SkC 9Y6jgtdUOLDF7ySuw8RCpx/BfO8pwNKfEo9hFExBAomWwQA7foD8s+W1ZhgaqOMQTgYV 37Z+hoDKoxyl1s9V1cuhAmQQdWa+crysZ5qP0NaKYYBNsDNrGDPxgz4hOHXlZ0xAdseU H4Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948849; x=1723553649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gv+R0AOxTRNRr/YYta1DbILbzN2/ozjvln37VG+akqw=; b=n01DbxhFfyrmFQpo/prEma1sy7EMVZvkRNcrqOHXPq1WOdEHomwIg+gZzy+anNeSLp qA5AZsIeE97j0GQeIyWWcJLgtJA1kNlYkYfxnq8llA16OLlCdHulvDnWvqAeZDWTFB7w 9unmV2kubi2nX/i3T7zWEe8URs6QxDA7sqj+WJbVNeQOCzbgH5Imdy+rhN0Ub1DAaA+E qAU89IQAGPdhp2ybRzdYsY3GHmwPePek2gmwC+sZeR5ZQI4WTpocgRJe/X1drpDjurev IbTsw7DIBOeSo/IOMdZGszDAfMke/GBC1Xy2gxvuRF8IBrpkqEZVOB+ItxfhNht36Jjy 5MHQ== X-Gm-Message-State: AOJu0Yydo86uBHraLbzIH4r7b1wbciCrtXTOLMorZ+JDTO5sitOsIefq sx3p0XdzhF7S/GgvTdEMx6Kx9yCONDV74N8MHMpIIXOP1vMMYh8czuWQ0UmAtP6S5QqLSY+4rVR S X-Google-Smtp-Source: AGHT+IEjUA7XHVQZQ9IKvGvDk1ZhAIr83KVOzxwR2ijFBWm9ba6PraKB14zqi/sY1NsIg+m0hfzMvA== X-Received: by 2002:a2e:98c3:0:b0:2ef:2b06:e554 with SMTP id 38308e7fff4ca-2f15aa87375mr99364231fa.15.1722948849227; Tue, 06 Aug 2024 05:54:09 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5bb88d1d9a3sm2558061a12.26.2024.08.06.05.54.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Kevin Wolf , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 21/28] hw/ide/pci: Remove dead code from bmdma_prepare_buf() Date: Tue, 6 Aug 2024 14:51:49 +0200 Message-ID: <20240806125157.91185-22-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Peter Maydell Coverity notes that the code at the end of the loop in bmdma_prepare_buf() is unreachable. This is because in commit 9fbf0fa81fca8f527 ("ide: remove hardcoded 2GiB transactional limit") we removed the only codepath in the loop which could "break" out of it, but didn't notice that this meant we should also remove the code at the end of the loop. Remove the dead code. Resolves: Coverity CID 1547772 Signed-off-by: Peter Maydell Reviewed-by: Kevin Wolf Reviewed-by: Philippe Mathieu-Daudé [PMD: Break and return once at EOF] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240805182419.22239-1-philmd@linaro.org> --- hw/ide/pci.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 4675d079a1..a008fe7316 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -237,7 +237,7 @@ static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit) /* end of table (with a fail safe of one page) */ if (bm->cur_prd_last || (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) { - return s->sg.size; + break; } pci_dma_read(pci_dev, bm->cur_addr, &prd, 8); bm->cur_addr += 8; @@ -266,10 +266,7 @@ static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit) s->io_buffer_size += l; } } - - qemu_sglist_destroy(&s->sg); - s->io_buffer_size = 0; - return -1; + return s->sg.size; } /* return 0 if buffer completed */ From patchwork Tue Aug 6 12:51:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A67FEC49EA1 for ; Tue, 6 Aug 2024 12:58:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJj3-00054t-98; Tue, 06 Aug 2024 08:55:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJhj-0000TS-Ew for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:24 -0400 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJhh-0000N2-H5 for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:19 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-a7a9a369055so54930866b.3 for ; Tue, 06 Aug 2024 05:54:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948855; x=1723553655; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nMm3A0DabsjolGXhyPhZ1sZzpOJXfaTPvfWzaUzLVvw=; b=SmbFAtbBPrGEkMuqRRb54s1Mewcnumej2DweE3kd3GdlqyW1uheRnTWocWgZHvBPbj 2YvBY5T+24pigPU4uJoRzPfbmWwpcWdTnO0OqaOeNQSjz74jRs2kMOGRRfOemwVuphYh 756EoKTqB/+jk2vgF6b05Gc7EHDly/PxF6p9G5qSmh2nQaqLJQ2O9pj+ITMTfL5yVKi6 EoZVpgbG6cmUEdDWff5jcHtM7p8SwxOr6D+S/c8lAMOQsFJ+0k9Sgi8myjfEKlWIw8VG /gP5syLzgR38PUNIVhLp7q+eeiBtGUKMGxv/n+kmn3nsNytHpiYXeUaRAS4x/QKexbFQ HG2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948855; x=1723553655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nMm3A0DabsjolGXhyPhZ1sZzpOJXfaTPvfWzaUzLVvw=; b=p4mQlJBJS+xEsoPDd4JorTAXV6vsN/HnOk8QRWplEnLT2SVoo7fEEvduK/ryPRNSo7 Fj89u8UVTC94jBvuAqdc8PIOtlC0r6WejwwpwOtmtY8scVYsoVTuvlEdimwu2V+STUdU uOnsXM85JgQZ5ISkl05s7L6rgBH2RpQRE2V9JcGjsqwxIizafr/U4j7LzuVpsZ1vWUgA eBhtSjFcsAgwukfvvGC98M3+gd9ozgikMeWnY3CYwQp6g7EK7Aps7P6tL4B1oxX3ZKWe sNcAp8VYvKpBhh8ph7h67SAY53Wrr+NwnZzjdg10RASvEkQLuIYFMMXX6Imb8eSrCMZi Q9Nw== X-Gm-Message-State: AOJu0YzSCl1bX2nMfdOHCX9prx3pq/QwoIxcU2oAIGqaz8dOLspB2zUk oFJ9NhrEECMsJ6a+s2wID7IYqiZUvZz0VqGPu67abQ0/tkW8g+QannIZYy8Vc4W0Xrld7A0xzzH D X-Google-Smtp-Source: AGHT+IH24eR79lDqIaE2q6DNcV5o2zg5AdeRNNb2Klp0VvlkZeCQ8kqmCVHJWCRJCsLUmt8xuxUqZg== X-Received: by 2002:a17:907:724b:b0:a77:b516:3023 with SMTP id a640c23a62f3a-a7dc4db2a1emr1035988366b.4.1722948855304; Tue, 06 Aug 2024 05:54:15 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9bc3c7asm558455666b.14.2024.08.06.05.54.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PULL 22/28] hw/display/virtio-gpu: Improve "opengl is not available" error message Date: Tue, 6 Aug 2024 14:51:50 +0200 Message-ID: <20240806125157.91185-23-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Peter Maydell If the user tries to use the virtio-gpu-gl device but the display backend doesn't have OpenGL support enabled, we currently print a rather uninformative error message: $ qemu-system-aarch64 -M virt -device virtio-gpu-gl qemu-system-aarch64: -device virtio-gpu-gl: opengl is not available Since OpenGL is not enabled on display frontends by default, users are quite likely to run into this. Improve the error message to be more specific and to suggest to the user a path forward. Note that the case of "user tried to enable OpenGL but the display backend doesn't handle it" is caught elsewhere first, so we can assume that isn't the problem: $ qemu-system-aarch64 -M virt -device virtio-gpu-gl -display curses,gl=on qemu-system-aarch64: OpenGL is not supported by the display (Use of error_append_hint() requires us to add an ERRP_GUARD() to the function, as noted in include/qapi/error.h.) With this commit we now produce the hopefully more helpful error: $ ./build/x86/qemu-system-aarch64 -M virt -device virtio-gpu-gl qemu-system-aarch64: -device virtio-gpu-gl: The display backend does not have OpenGL support enabled It can be enabled with '-display BACKEND,gl=on' where BACKEND is the name of the display backend to use. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2443 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Acked-by: Marc-André Lureau Message-ID: <20240731154136.3494621-2-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/display/virtio-gpu-gl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/display/virtio-gpu-gl.c b/hw/display/virtio-gpu-gl.c index 952820a425..29d20b0132 100644 --- a/hw/display/virtio-gpu-gl.c +++ b/hw/display/virtio-gpu-gl.c @@ -106,6 +106,7 @@ static void virtio_gpu_gl_reset(VirtIODevice *vdev) static void virtio_gpu_gl_device_realize(DeviceState *qdev, Error **errp) { + ERRP_GUARD(); VirtIOGPU *g = VIRTIO_GPU(qdev); #if HOST_BIG_ENDIAN @@ -119,7 +120,12 @@ static void virtio_gpu_gl_device_realize(DeviceState *qdev, Error **errp) } if (!display_opengl) { - error_setg(errp, "opengl is not available"); + error_setg(errp, + "The display backend does not have OpenGL support enabled"); + error_append_hint(errp, + "It can be enabled with '-display BACKEND,gl=on' " + "where BACKEND is the name of the display backend " + "to use.\n"); return; } From patchwork Tue Aug 6 12:51:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D758CC3DA64 for ; Tue, 6 Aug 2024 13:00:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJiH-0001pI-Di; Tue, 06 Aug 2024 08:54:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJho-0000nB-Mp for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:29 -0400 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJhn-0000Nw-0p for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:24 -0400 Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-a7a83a968ddso68694666b.0 for ; Tue, 06 Aug 2024 05:54:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948861; x=1723553661; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0GHmHGgb11iYqcqPSgHHl5+4znvZdtn/oYi94we9BmQ=; b=F8p8PwSPMjqiDf1fjeafK20HfvSm7LyuWBdJZ8gbuaJGz+jcgfKlzRNYtpki3l8gSQ 6Uu/jb90k/quNvwTvT6RVv1xTvbF+4tpKSLgRHW9BoZkqPLLCUtER2Vn+ECT/DNf6aq7 BNNdcsrPBMIfNO5SlitGn6HV1C+PtHM1LqmvsZ0NEFODUfh1RsKIAx6UAu4EW/8UGDc2 mKHN1+30IdZNRjTJGVGWSP//CJcQ3Wwwrp8PL9WU90S27Uhx9MTliMo6+RYRjhqnpXCg Jtk4fAcFYXrb4jcNtNQszsChBlA4nkXTYDOy72YZ9denSKz3kqFX35e+R/HAuOMgRl7N lVcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948861; x=1723553661; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0GHmHGgb11iYqcqPSgHHl5+4znvZdtn/oYi94we9BmQ=; b=pq6ZFaKsa7r1S3rQWfCSFiPa5lynIMK1t6NRGxFD648SIxG7tX9cM4RqcZNM0fq0az 0hk3hDb8dUn8aFSmDhRFTMzVUKlTsK1pgywqTukL3msZtO4sbd62H8HocxlGjTMP+HwG oFB4HwpKlyCtFLnCbVdi65XbvPEP6H7pXFq27x5/SBxQTuTdynggwuL3kOw7YwHs0IV9 21F8XdNpgW4b6BG8Sl0FGpG8MBAHLyZdJTrACEJoocrNnwQrJHNPuNAc0wYKRMCovdQ8 9zb0xXui9msscmWrod+as5LQP9L90oZelyqWVFV0bgH+ebMXu/N5oAuIVkAdyqsAM2ua nXFw== X-Gm-Message-State: AOJu0Yyf0+dHWLfnN97NBnuBMRJTZqjeLStM3wgf+qbrl+vbbIyoIuBj AXyX3PG0rk0JBp4uUFFJqSEjEXVVPYQfVznP5FzmgpJooAWO5uRsSdMEZLpp7h2kO4jqL8uJzmb M X-Google-Smtp-Source: AGHT+IEAf1tc9+rVm04xWKxc+tXJ/ZBu8kXaFWJuaACS5HoEF/5xW6tCR12NB/1uYawe4HF32jWj9w== X-Received: by 2002:a17:906:7312:b0:a7d:a680:23b5 with SMTP id a640c23a62f3a-a7dc50007bamr1077254966b.33.1722948861023; Tue, 06 Aug 2024 05:54:21 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9bc9d7dsm547291966b.9.2024.08.06.05.54.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PULL 23/28] system/vl.c: Expand OpenGL related errors Date: Tue, 6 Aug 2024 14:51:51 +0200 Message-ID: <20240806125157.91185-24-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Peter Maydell Expand the OpenGL related error messages we produce for various "OpenGL not present/not supported" cases, to hopefully guide the user towards how to fix things. Now if the user tries to enable GL on a backend that doesn't support it the error message is a bit more precise: $ qemu-system-aarch64 -M virt -device virtio-gpu-gl -display curses,gl=on qemu-system-aarch64: OpenGL is not supported by display backend 'curses' Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Acked-by: Marc-André Lureau Message-ID: <20240731154136.3494621-3-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- system/vl.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/system/vl.c b/system/vl.c index 9e8f16f155..213ee6a6a9 100644 --- a/system/vl.c +++ b/system/vl.c @@ -1973,9 +1973,10 @@ static void qemu_create_early_backends(void) if (dpy.has_gl && dpy.gl != DISPLAYGL_MODE_OFF && display_opengl == 0) { #if defined(CONFIG_OPENGL) - error_report("OpenGL is not supported by the display"); + error_report("OpenGL is not supported by display backend '%s'", + DisplayType_str(dpy.type)); #else - error_report("OpenGL support is disabled"); + error_report("OpenGL support was disabled when QEMU was compiled"); #endif exit(1); } From patchwork Tue Aug 6 12:51:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4C5DC49EA1 for ; Tue, 6 Aug 2024 12:55:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJiM-0002rV-Tc; Tue, 06 Aug 2024 08:55:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJhu-0001Be-8P for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:31 -0400 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJhs-0000OS-EL for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:29 -0400 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-a7a9a7af0d0so56649466b.3 for ; Tue, 06 Aug 2024 05:54:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948866; x=1723553666; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lTDAhFeBz9GijM5OI6/yGi13UeAA7K13kn7Zuxhnv+U=; b=NPNVgoVsqnWR2wGTYEo/+XHOwqUPR3N8M418/RJfFh5xb6Oa+gJa5OQol9pg3IfO+t 2DSpRtTdGFKTdEJW8lxAb9D74M9RzcSRllFM0SE+Pre68K3nUNhi23N+WQ+CkF/tjIMv tUtpkgySAQNa07F8ha9/4bTLSW/vnYPQUvUQZnUIuW1XSfjWyvBdb+Gk8VL0WnUVzcsP XbERr7kiJdmQIySGXINcFhFMCv3mI5yfrVkpuUjeytx8IjC9IxbkZvPEUCCIdjl+qAHZ Ck7zlrnF/tb5Lv9oR0sQVZZ8vQfH7w31iD1eF8Uy9+BxVMOO7zJ1QG5B8y+qrn14iSp/ upFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948866; x=1723553666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lTDAhFeBz9GijM5OI6/yGi13UeAA7K13kn7Zuxhnv+U=; b=Tm5bjljQq/O+hDD0zvyXKBf9Ygr6u8/j23INt+3pCDVCfB25Ft+PcOvjTl6X1xWaur RwOOBwuIXw0auVglmo7/nUZ9LNKw7uedXfOv0UxY9cFrBLXVp+SZvPAbjZdKDiGDquAp 4MuGoQs6jhubYslLoaGAs0/chfrSOy8Fg/y0bSfFjrz1Km5alfsPwRHiZDEOShu0YPyD Gamj//18+x5RkEKMpBgS+uZFHuQ4hKcHbPrmPjYvt+peYTs/RYCTOE+78bydAicCdczR M4S/VxbPOfXDhCSgKR2KOyVGRCkbz55h8Bp9UgKfN+mQN7haKU+3R8orpcCQWdGYFNo8 NpZg== X-Gm-Message-State: AOJu0Yw5u6D7fsnpbFIeo/HMASJNJH1bQjGwTpqFfJOE55Yh8MmnT21d Vdeo03krPuRpIcDxbJUqJmGvWZyPR7Stb3tHebmJmMPtYHKEpi3U3hey+QG6Kz+5iMTA6v+Fh7L M X-Google-Smtp-Source: AGHT+IGomE15Wo24DJ7lRF9r2AdwMtkLdlxkaxrrJGCGSbJvrkwY5lYMVoVzNmiweJgvYZedJRXyAg== X-Received: by 2002:a17:907:7ea4:b0:a7a:a06b:eebf with SMTP id a640c23a62f3a-a7dc4e86892mr989659866b.22.1722948866623; Tue, 06 Aug 2024 05:54:26 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7de2d923ccsm423738866b.79.2024.08.06.05.54.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:26 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PULL 24/28] ui/console: Note in '-display help' that some backends support suboptions Date: Tue, 6 Aug 2024 14:51:52 +0200 Message-ID: <20240806125157.91185-25-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Peter Maydell Currently '-display help' only prints the available backends. Some of those backends support suboptions (e.g. '-display gtk,gl=on'). Mention that in the help output, and point the user to where they might be able to find more information about the suboptions. The new output looks like this: $ qemu-system-aarch64 -display help Available display backend types: none gtk sdl egl-headless curses spice-app dbus Some display backends support suboptions, which can be set with -display backend,option=value,option=value... For a short list of the suboptions for each display, see the top-level -help output; more detail is in the documentation. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Acked-by: Marc-André Lureau Message-ID: <20240731154136.3494621-4-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- ui/console.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/ui/console.c b/ui/console.c index e8f0083af7..105a0e2c70 100644 --- a/ui/console.c +++ b/ui/console.c @@ -1632,4 +1632,9 @@ void qemu_display_help(void) printf("%s\n", DisplayType_str(dpys[idx]->type)); } } + printf("\n" + "Some display backends support suboptions, which can be set with\n" + " -display backend,option=value,option=value...\n" + "For a short list of the suboptions for each display, see the " + "top-level -help output; more detail is in the documentation.\n"); } From patchwork Tue Aug 6 12:51:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A4DCC52D70 for ; Tue, 6 Aug 2024 12:56:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJjz-0001Jv-E8; Tue, 06 Aug 2024 08:56:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJi0-0001fi-7B for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:38 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJhy-0000P5-BN for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:35 -0400 Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-a7a9cf7d3f3so77308166b.1 for ; Tue, 06 Aug 2024 05:54:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948872; x=1723553672; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ypdbeuI3/3zkqxrrQlfqtvt5UnR+ONpIVnv+X7Sc7F4=; b=UOwVR5EUu5a2N+T0yWbOTY3Z1t0/daSYxvlHH6vbtNMi24zwRz1UrQYquzrRCv2zi1 TjZicPov6itbsZ1JowtklgUZnDVuMeMw7S5cYQMIMcUpa8RHpiRACxpRhVuoBgZicRza Mzxkno0EKv48aTBXyo5iCXvQVruEOawD1RYsHWLshOmnSaZO+ObM+KeZn2No3FfnE6g9 pHiVFo6WuI9y5+9ZOghfkZHqQsi01SPoeJgmdiV7TqZG8NabflJsrcJVSdNRr+vnP56P DumRxeP5jBaBW8b2dm5YGNnVDbFiP2tEbkqY1kG2dBKmp1HQfjFA6JRkEyfRZZ1qeB9B MFcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948872; x=1723553672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ypdbeuI3/3zkqxrrQlfqtvt5UnR+ONpIVnv+X7Sc7F4=; b=EOnVbjSfbHEEhqOm/6g6OFK5FANXzKi41e/M9vcTHiREygpmd3VB09Qfq/OHSAHJai NtJGQ6Hv+Wtd4PpZyyWhtcoW1tdxTinDRfAtJesmeiFzsko/WHgtk8wuIykmEFWEqMnj qfT3UlcHf/3JLuyisrXaktcMIO8K3TnV7cHdZO/MM+tF0UmBs0h9BtgEskwrKHavJsAY 3XVClVEoNwqBvDWmGot9+1aBkXpooj6RW0A0My/1EDqCAf8FEEOGq0tfv9qfIMl/3dyk mFhqZgV25s/mICdFgvR/yk18rEZuwdhF7vdPSUw7vaLgvAhDmdEnS3Btes+WOhR92QXs mhuQ== X-Gm-Message-State: AOJu0Yxieg7tgF1zqp6nLX2cyaWIoN6q4PDgw4G70hv7IEF75a38pgKA 5Zpr36Fid7Xf42H8dGUUO7AC9K82/lIdCTV5J4ElE7XXAOim90CxvSzfddc1ZtsflHME67qkWUK V X-Google-Smtp-Source: AGHT+IGL/4huUwzcaLaq6PgwpIBAIzK6jpN8ZZXtAH1L3lKCQWPQ2lA7CiO9A/Y6o0KABCklX7vuug== X-Received: by 2002:a17:907:3e1a:b0:a75:2781:a5c4 with SMTP id a640c23a62f3a-a7dc4ea9ebdmr1048774766b.29.1722948872256; Tue, 06 Aug 2024 05:54:32 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9c0c0d5sm545644666b.48.2024.08.06.05.54.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , BALATON Zoltan Subject: [PULL 25/28] hw/pci-host/gt64120: Set PCI base address register write mask Date: Tue, 6 Aug 2024 14:51:53 +0200 Message-ID: <20240806125157.91185-26-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When booting Linux we see: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) This is due to missing base address register write mask. Add it to get: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000fff] Since this device is only used by MIPS machines which aren't versioned, we don't need to update migration compat machinery. Mention the datasheet referenced. Remove the "Malta assumptions ahead" comment since the reset values from the datasheet are used. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan Message-Id: <20240802213122.86852-2-philmd@linaro.org> --- hw/pci-host/gt64120.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index e02efc9e2e..573d2619ee 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1,6 +1,8 @@ /* * QEMU GT64120 PCI host * + * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999) + * * Copyright (c) 2006,2007 Aurelien Jarno * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -1213,17 +1215,27 @@ static void gt64120_realize(DeviceState *dev, Error **errp) static void gt64120_pci_realize(PCIDevice *d, Error **errp) { - /* FIXME: Malta specific hw assumptions ahead */ + /* Values from chapter 17.16 "PCI Configuration" */ + pci_set_word(d->config + PCI_COMMAND, 0); pci_set_word(d->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_prog_interface(d->config, 0); + + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */ + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */ + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */ + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */ + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */ + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */ + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); + pci_set_byte(d->config + 0x3d, 0x01); } From patchwork Tue Aug 6 12:51:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1705C52D73 for ; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e80e04sm553901866b.175.2024.08.06.05.54.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S . Tsirkin" , BALATON Zoltan Subject: [PULL 26/28] hw/pci-host/gt64120: Reset config registers during RESET phase Date: Tue, 6 Aug 2024 14:51:54 +0200 Message-ID: <20240806125157.91185-27-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reset config values in the device RESET phase, not only once when the device is realized, because otherwise the device can use unknown values at reset. Since we are adding a new reset method, use the preferred Resettable API (for a simple leaf device reset, a DeviceClass::reset method and a ResettableClass::reset_hold method are essentially identical). Reported-by: Michael S. Tsirkin Reviewed-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240802213122.86852-3-philmd@linaro.org> --- hw/pci-host/gt64120.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index 573d2619ee..33607dfbec 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1217,17 +1217,24 @@ static void gt64120_pci_realize(PCIDevice *d, Error **errp) { /* Values from chapter 17.16 "PCI Configuration" */ - pci_set_word(d->config + PCI_COMMAND, 0); - pci_set_word(d->config + PCI_STATUS, - PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); - pci_config_set_prog_interface(d->config, 0); - pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */ pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */ pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */ pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */ pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */ pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */ +} + +static void gt64120_pci_reset_hold(Object *obj, ResetType type) +{ + PCIDevice *d = PCI_DEVICE(obj); + + /* Values from chapter 17.16 "PCI Configuration" */ + + pci_set_word(d->config + PCI_COMMAND, 0); + pci_set_word(d->config + PCI_STATUS, + PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); + pci_config_set_prog_interface(d->config, 0); pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); @@ -1243,7 +1250,9 @@ static void gt64120_pci_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + rc->phases.hold = gt64120_pci_reset_hold; k->realize = gt64120_pci_realize; k->vendor_id = PCI_VENDOR_ID_MARVELL; k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; From patchwork Tue Aug 6 12:51:55 2024 Content-Type: text/plain; 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Signed-off-by: George Matsumura Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240805031012.16547-2-gorg@gorgnet.net> Signed-off-by: Philippe Mathieu-Daudé --- docs/specs/pci-ids.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst index c0a3dec2e7..0de13de1e4 100644 --- a/docs/specs/pci-ids.rst +++ b/docs/specs/pci-ids.rst @@ -82,8 +82,12 @@ PCI devices (other than virtio): PCI-PCI bridge (multiseat) 1b36:000b PCIe Expander Bridge (-device pxb-pcie) +1b36:000c + PCIe Root Port (``-device pcie-root-port``) 1b36:000d PCI xhci usb host adapter +1b36:000e + PCIe-to-PCI bridge (``-device pcie-pci-bridge``) 1b36:000f mdpy (mdev sample device), ``linux/samples/vfio-mdev/mdpy.c`` 1b36:0010 From patchwork Tue Aug 6 12:51:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13754833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DC01C49EA1 for ; Tue, 6 Aug 2024 13:01:14 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbJk8-0002Rz-Oi; Tue, 06 Aug 2024 08:56:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbJiI-0002no-0v for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:55 -0400 Received: from mail-lj1-x231.google.com ([2a00:1450:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sbJiF-0000UT-IL for qemu-devel@nongnu.org; Tue, 06 Aug 2024 08:54:53 -0400 Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2f16d2f2b68so10343971fa.3 for ; Tue, 06 Aug 2024 05:54:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948889; x=1723553689; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=77mKDDwsQ4N9EU0OpMBcpTovtWIwsiedBtivnY0Iukw=; b=Qu2lRgvtWUoBdhyQV+WuXtEl9UdPNHwrsSQ8XP9xCBMeBlGAUeFrIMD+i83YjlUpGT yPelIYWqg/yXP4VKDsHyLmk/mag4luvj6xtakq/DNWFXLkSsaPd6gqmDJ5o2S4YVlu4b S73st1jgwnPifxnuZbFYhF8bwEE6Tj4cd6ukZ88GKfqX4fG336I99e6VCb+bsftIKOjz t+C7fjYr2g/DAlgLPCFT4rmc8pVKea/CLVcLKSNM3tZz6zW6YLh0FTJkAiLGTgMcfKop u2/SRWqzEBrvVuGTKTW8MU5I4GxkrGY5abGm8+NWqvax0DXjK7rbOVzym4N6k6v6vKyg DgeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948889; x=1723553689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=77mKDDwsQ4N9EU0OpMBcpTovtWIwsiedBtivnY0Iukw=; b=gMuQ91hw0nW6aXKgNic9I0BOP1mLN2sS12c4euzWllle+O44XAYsANuaDX4MITTyxc PBS4GjPi3UCAA5/l5CVSIepnY5ukNHZfKvIgk5Z0Z+tppXbmAbQtKtEOpMoLEJRNUuGx 3JXK8yrA/LrDvj2PEJta63YdzyDZmmV+NQl/P3v2XBipQrMM22ssnWqWCtLyjk8UthH+ xDuSSgHgQN2sUGuWdYEq+53Ui//gfTsKKHMUCg9vxN45nnacoTNn8epEWcfIas6BKO02 h0GnOfRLZwrU6RmRXue9OC4tX6yty9n0oWPKkVnTHqi57/mhDTfU/3W7Dv/VHvanKxXb yNUA== X-Gm-Message-State: AOJu0YxPg82aq7W6pDCBn/oGqel0q0LgHAxo4jDBUOgdnTGtf/Vl/4Rh jTOz/7cJ/tFke8Q5LxdN1fQZUKlusExi8B+63v8sQEQv9TjHVfeLWviLH6Ih0LajFZrgFkwrCJQ V X-Google-Smtp-Source: AGHT+IGPJ76mc/UQH9XLaxpy2CfyQDntSF5wjLya5+pAlsgmZ8swYga5cElYxvfYK29b00l582g1iQ== X-Received: by 2002:a2e:8703:0:b0:2ef:1b1b:7f42 with SMTP id 38308e7fff4ca-2f15ab2a580mr118277291fa.36.1722948889440; Tue, 06 Aug 2024 05:54:49 -0700 (PDT) Received: from m1x-phil.lan (cor91-h02-176-184-30-206.dsl.sta.abo.bbox.fr. [176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e7fe2fsm548850866b.178.2024.08.06.05.54.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:49 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: George Matsumura , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 28/28] docs/specs/pci-ids: Fix markup Date: Tue, 6 Aug 2024 14:51:56 +0200 Message-ID: <20240806125157.91185-29-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: George Matsumura This fixes the markup of the PCI and PCIe Expander Bridge entries to be consistent with the rest of the file. Signed-off-by: George Matsumura Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240805031012.16547-4-gorg@gorgnet.net> Signed-off-by: Philippe Mathieu-Daudé --- docs/specs/pci-ids.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst index 0de13de1e4..328ab31fe8 100644 --- a/docs/specs/pci-ids.rst +++ b/docs/specs/pci-ids.rst @@ -77,11 +77,11 @@ PCI devices (other than virtio): 1b36:0008 PCIe host bridge 1b36:0009 - PCI Expander Bridge (-device pxb) + PCI Expander Bridge (``-device pxb``) 1b36:000a PCI-PCI bridge (multiseat) 1b36:000b - PCIe Expander Bridge (-device pxb-pcie) + PCIe Expander Bridge (``-device pxb-pcie``) 1b36:000c PCIe Root Port (``-device pcie-root-port``) 1b36:000d