From patchwork Tue Aug 6 12:58:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13754867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 009B6C49EA1 for ; Tue, 6 Aug 2024 12:57:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A080610E35D; Tue, 6 Aug 2024 12:57:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="A3PGAI8M"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 215EC10E35C; Tue, 6 Aug 2024 12:57:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722949035; x=1754485035; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OsDsUuKd93lZrxXkSmQtJrfezNYDohp7kOFzmSmYvmY=; b=A3PGAI8MH71H6jXsJ9JFFJlSlYCe3UaYnB48D3styUGnfdx7KO4g1r6I bnDKr22ep8Amb5e7KVACqDorcEddMa823tkZ4xCuMl+PWy1OFTSC4760R PlNvOXD34z1LNUyM860E5kl60fNDwEYU/arku8llGU/JBAbvjit7SJvpl TQ6LC8B3QN4znw1hgQxPCBeqMuAqG7rFsWrDDzocM0IedHHXgP5w4M0Pt TDibbYQPkSgx6ezPxa6oG4+YilCZUuhz5a7K1qr1moJqaSipUu/Cr27WW 6kJ5m03X1jVmYUDLIEmBRJzfs6iO1Ssbu5VRVsKQqpfj6QTMbCbV+G+Yu Q==; X-CSE-ConnectionGUID: S8MpZtnFQDCBua4cOPRF9Q== X-CSE-MsgGUID: +f6sqkpsQ+mz7nUjFP/Czw== X-IronPort-AV: E=McAfee;i="6700,10204,11156"; a="21142069" X-IronPort-AV: E=Sophos;i="6.09,267,1716274800"; d="scan'208";a="21142069" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2024 05:57:15 -0700 X-CSE-ConnectionGUID: GJ1uitcOSpSaXwT1huhPUw== X-CSE-MsgGUID: aImapNGEToGtYW5fa8L2Zw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,267,1716274800"; d="scan'208";a="79762905" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2024 05:57:13 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com Subject: [PATCH 1/5] drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2 Date: Tue, 6 Aug 2024 18:28:22 +0530 Message-ID: <20240806125827.2183899-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125827.2183899-1-ankit.k.nautiyal@intel.com> References: <20240806125827.2183899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add helper _intel_phy_compute_hdmi_tmds_pll to calculate the necessary parameters for configuring the HDMI PLL for SNPS MPLLB and C10 PHY. The pll parameters are computed for desired pixel clock, curve data and other inputs used for interpolation and finally stored in the pll_state. Bspec:54032 Currently the helper is used to compute PLLs for DG2 SNPS PHY. Support for computing Plls for C10 PHY is added in subsequent patches. v2: -Used kernel types instead of C99 types. (Jani) -Fixed styling issues and renamed few variables to more meaningful names. (Jani) -Added Xe make file changes. (Jani) -Fixed build errors reported by kernel test robot Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/Makefile | 1 + .../drm/i915/display/intel_snps_hdmi_pll.c | 286 ++++++++++++++++++ .../drm/i915/display/intel_snps_hdmi_pll.h | 15 + drivers/gpu/drm/xe/Makefile | 1 + 4 files changed, 303 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c create mode 100644 drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index c63fa2133ccb..85f924bc297e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -338,6 +338,7 @@ i915-y += \ display/intel_pps.o \ display/intel_qp_tables.o \ display/intel_sdvo.o \ + display/intel_snps_hdmi_pll.o \ display/intel_snps_phy.o \ display/intel_tv.o \ display/intel_vdsc.o \ diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c new file mode 100644 index 000000000000..d2e1f42e1a5a --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Synopsys, Inc., Intel Corporation + */ + +#include + +#include "intel_display_types.h" +#include "intel_snps_phy.h" +#include "intel_snps_phy_regs.h" +#include "intel_snps_hdmi_pll.h" + +#define INTEL_SNPS_PHY_HDMI_4999MHZ 4999999900ULL +#define INTEL_SNPS_PHY_HDMI_16GHZ 16000000000ULL +#define INTEL_SNPS_PHY_HDMI_9999MHZ (2 * INTEL_SNPS_PHY_HDMI_4999MHZ) + +#define CURVE0_MULTIPLIER 1000000000 +#define CURVE1_MULTIPLIER 100 +#define CURVE2_MULTIPLIER 1000000000000ULL + +struct pll_output_params { + u32 ssc_up_spread; + u32 mpll_div5_en; + u32 hdmi_div; + u32 ana_cp_int; + u32 ana_cp_prop; + u32 refclk_postscalar; + u32 tx_clk_div; + u32 fracn_quot; + u32 fracn_rem; + u32 fracn_den; + u32 fracn_en; + u32 pmix_en; + u32 multiplier; + int mpll_ana_v2i; + int ana_freq_vco; +}; + +static s64 interp(s64 x, s64 x1, s64 x2, s64 y1, s64 y2) +{ + s64 dydx; + + dydx = DIV_ROUND_UP_ULL((y2 - y1) * 100000, (x2 - x1)); + + return (y1 + DIV_ROUND_UP_ULL(dydx * (x - x1), 100000)); +} + +static void get_ana_cp_int_prop(u32 vco_clk, + u32 refclk_postscalar, + int mpll_ana_v2i, + int c, int a, + const u64 curve_freq_hz[2][8], + const u64 curve_0[2][8], + const u64 curve_1[2][8], + const u64 curve_2[2][8], + u32 *ana_cp_int, + u32 *ana_cp_prop) +{ + u64 vco_div_refclk_float; + u64 curve_0_interpolated; + u64 curve_2_interpolated; + u64 curve_1_interpolated; + u64 curve_2_scaled1; + u64 curve_2_scaled2; + u64 adjusted_vco_clk1; + u64 adjusted_vco_clk2; + u64 curve_2_scaled_int; + u64 interpolated_product; + u64 scaled_interpolated_sqrt; + u64 scaled_vco_div_refclk1; + u64 scaled_vco_div_refclk2; + u64 temp; + + vco_div_refclk_float = vco_clk * DIV_ROUND_DOWN_ULL(1000000000000ULL, refclk_postscalar); + + /* Interpolate curve values at the target vco_clk frequency */ + curve_0_interpolated = interp(vco_clk, curve_freq_hz[c][a], curve_freq_hz[c][a + 1], + curve_0[c][a], curve_0[c][a + 1]); + + curve_2_interpolated = interp(vco_clk, curve_freq_hz[c][a], curve_freq_hz[c][a + 1], + curve_2[c][a], curve_2[c][a + 1]); + + curve_1_interpolated = interp(vco_clk, curve_freq_hz[c][a], curve_freq_hz[c][a + 1], + curve_1[c][a], curve_1[c][a + 1]); + + curve_1_interpolated = DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE1_MULTIPLIER); + + /* + * Scale curve_2_interpolated based on mpll_ana_v2i, for integer part + * ana_cp_int and for the proportional part ana_cp_prop + */ + temp = curve_2_interpolated * (4 - mpll_ana_v2i); + curve_2_scaled1 = DIV_ROUND_DOWN_ULL(temp, 16000); + curve_2_scaled2 = DIV_ROUND_DOWN_ULL(temp, 160); + + /* Scale vco_div_refclk for ana_cp_int */ + scaled_vco_div_refclk1 = 112008301 * DIV_ROUND_DOWN_ULL(vco_div_refclk_float, 100000); + + adjusted_vco_clk1 = CURVE2_MULTIPLIER * + DIV_ROUND_DOWN_ULL(scaled_vco_div_refclk1, (curve_0_interpolated * + DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE0_MULTIPLIER))); + + *ana_cp_int = DIV_ROUND_CLOSEST_ULL(DIV_ROUND_DOWN_ULL(adjusted_vco_clk1, curve_2_scaled1), + CURVE2_MULTIPLIER); + *ana_cp_int = max(1, min(*ana_cp_int, 127)); + + curve_2_scaled_int = curve_2_scaled1 * (*ana_cp_int); + + interpolated_product = curve_1_interpolated * + (curve_2_scaled_int * DIV_ROUND_DOWN_ULL(curve_0_interpolated, + CURVE0_MULTIPLIER)); + + scaled_interpolated_sqrt = + int_sqrt(DIV_ROUND_UP_ULL(interpolated_product, vco_div_refclk_float) * + DIV_ROUND_DOWN_ULL(1000000000000ULL, 55)); + + /* Scale vco_div_refclk for ana_cp_int */ + scaled_vco_div_refclk2 = DIV_ROUND_UP_ULL(vco_div_refclk_float, 1000000); + adjusted_vco_clk2 = 1460281 * DIV_ROUND_UP_ULL(scaled_interpolated_sqrt * + scaled_vco_div_refclk2, + curve_1_interpolated); + + *ana_cp_prop = DIV_ROUND_UP_ULL(adjusted_vco_clk2, curve_2_scaled2); + *ana_cp_prop = max(1, min(*ana_cp_prop, 127)); +} + +static void compute_hdmi_tmds_pll(u64 pixel_clock, u32 refclk, + u32 ref_range, + u32 ana_cp_int_gs, + u32 ana_cp_prop_gs, + const u64 curve_freq_hz[2][8], + const u64 curve_0[2][8], + const u64 curve_1[2][8], + const u64 curve_2[2][8], + u32 prescaler_divider, + struct pll_output_params *pll_params) +{ + /* datarate 10khz */ + u64 datarate = pixel_clock * 10000; + u32 ssc_up_spread = 1; + u32 mpll_div5_en = 1; + u32 hdmi_div = 1; + u32 ana_cp_int; + u32 ana_cp_prop; + u32 refclk_postscalar = refclk >> prescaler_divider; + u32 tx_clk_div; + u64 vco_clk; + u64 vco_clk_do_div; + u32 vco_div_refclk_integer; + u32 vco_div_refclk_fracn; + u32 fracn_quot; + u32 fracn_rem; + u32 fracn_den; + u32 fracn_en; + u32 pmix_en; + u32 multiplier; + int mpll_ana_v2i; + int ana_freq_vco = 0; + int c, a = 0; + int i; + + /* Select appropriate v2i point */ + if (datarate <= INTEL_SNPS_PHY_HDMI_9999MHZ) { + mpll_ana_v2i = 2; + tx_clk_div = ilog2(DIV_ROUND_DOWN_ULL(INTEL_SNPS_PHY_HDMI_9999MHZ, datarate)); + } else { + mpll_ana_v2i = 3; + tx_clk_div = ilog2(DIV_ROUND_DOWN_ULL(INTEL_SNPS_PHY_HDMI_16GHZ, datarate)); + } + vco_clk = (datarate << tx_clk_div) >> 1; + + vco_div_refclk_integer = DIV_ROUND_DOWN_ULL(vco_clk, refclk_postscalar); + vco_clk_do_div = do_div(vco_clk, refclk_postscalar); + vco_div_refclk_fracn = DIV_ROUND_DOWN_ULL(vco_clk_do_div << 32, refclk_postscalar); + + fracn_quot = vco_div_refclk_fracn >> 16; + fracn_rem = vco_div_refclk_fracn & 0xffff; + fracn_rem = fracn_rem - (fracn_rem >> 15); + fracn_den = 0xffff; + fracn_en = (fracn_quot != 0 || fracn_rem != 0) ? 1 : 0; + pmix_en = fracn_en; + multiplier = (vco_div_refclk_integer - 16) * 2; + /* Curve selection for ana_cp_* calculations. One curve hardcoded per v2i range */ + c = mpll_ana_v2i - 2; + + /* Find the right segment of the table */ + for (i = 0; i < 8; i += 2) { + if (vco_clk <= curve_freq_hz[c][i + 1]) { + a = i; + ana_freq_vco = 3 - (a >> 1); + break; + } + } + + get_ana_cp_int_prop(vco_clk, refclk_postscalar, mpll_ana_v2i, c, a, + curve_freq_hz, curve_0, curve_1, curve_2, + &ana_cp_int, &ana_cp_prop); + + pll_params->ssc_up_spread = ssc_up_spread; + pll_params->mpll_div5_en = mpll_div5_en; + pll_params->hdmi_div = hdmi_div; + pll_params->ana_cp_int = ana_cp_int; + pll_params->refclk_postscalar = refclk_postscalar; + pll_params->tx_clk_div = tx_clk_div; + pll_params->fracn_quot = fracn_quot; + pll_params->fracn_rem = fracn_rem; + pll_params->fracn_den = fracn_den; + pll_params->fracn_en = fracn_en; + pll_params->pmix_en = pmix_en; + pll_params->multiplier = multiplier; + pll_params->ana_cp_prop = ana_cp_prop; + pll_params->mpll_ana_v2i = mpll_ana_v2i; + pll_params->ana_freq_vco = ana_freq_vco; +} + +void intel_snps_phy_compute_hdmi_tmds_pll(struct intel_mpllb_state *pll_state, u64 pixel_clock) +{ + /* x axis frequencies. One curve in each array per v2i point */ + static const u64 dg2_curve_freq_hz[2][8] = { + { 2500000000ULL, 3000000000ULL, 3000000000ULL, 3500000000ULL, 3500000000ULL, + 4000000000ULL, 4000000000ULL, 5000000000ULL }, + { 4000000000ULL, 4600000000ULL, 4601000000ULL, 5400000000ULL, 5401000000ULL, + 6600000000ULL, 6601000000ULL, 8001000000ULL } + }; + + /* y axis heights multiplied with 1000000000 */ + static const u64 dg2_curve_0[2][8] = { + { 34149871, 39803269, 36034544, 40601014, 35646940, 40016109, 35127987, 41889522 }, + { 70000000, 78770454, 70451838, 80427119, 70991400, 84230173, 72945921, 87064218 } + }; + + /* Multiplied with 100 */ + static const u64 dg2_curve_1[2][8] = { + { 85177000000000ULL, 79385227160000ULL, 95672603580000ULL, 88857207160000ULL, + 109379790900000ULL, 103528193900000ULL, 131941242400000ULL, 117279000000000ULL }, + { 60255000000000ULL, 55569000000000ULL, 72036000000000ULL, 69509000000000ULL, + 81785000000000ULL, 731030000000000ULL, 96591000000000ULL, 69077000000000ULL } + }; + + /* Multiplied with 1000000000000 */ + static const u64 dg2_curve_2[2][8] = { + { 2186930000ULL, 2835287134ULL, 2395395343ULL, 2932270687ULL, 2351887545ULL, + 2861031697ULL, 2294149152ULL, 3091730000ULL }, + { 4560000000ULL, 5570000000ULL, 4610000000ULL, 5770000000ULL, 4670000000ULL, + 6240000000ULL, 4890000000ULL, 6600000000ULL } + }; + + struct pll_output_params pll_params; + u32 refclk = 100000000; + u32 prescaler_divider = 1; + u32 ref_range = 3; + u32 ana_cp_int_gs = 64; + u32 ana_cp_prop_gs = 124; + + compute_hdmi_tmds_pll(pixel_clock, refclk, ref_range, ana_cp_int_gs, ana_cp_prop_gs, + dg2_curve_freq_hz, dg2_curve_0, dg2_curve_1, dg2_curve_2, + prescaler_divider, &pll_params); + + pll_state->clock = pixel_clock; + pll_state->ref_control = + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, ref_range); + pll_state->mpllb_cp = + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, pll_params.ana_cp_int) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, pll_params.ana_cp_prop) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, ana_cp_int_gs) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, ana_cp_prop_gs); + pll_state->mpllb_div = + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, pll_params.mpll_div5_en) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_params.tx_clk_div) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, pll_params.pmix_en) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, pll_params.mpll_ana_v2i) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, pll_params.ana_freq_vco); + pll_state->mpllb_div2 = + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, prescaler_divider) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, pll_params.multiplier) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, pll_params.hdmi_div); + pll_state->mpllb_fracn1 = + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, pll_params.fracn_en) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, pll_params.fracn_den); + pll_state->mpllb_fracn2 = + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, pll_params.fracn_quot) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, pll_params.fracn_rem); + pll_state->mpllb_sscen = + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, pll_params.ssc_up_spread); +} diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h new file mode 100644 index 000000000000..9f60bd9bacbe --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Synopsys, Inc., Intel Corporation + */ + +#ifndef __INTEL_SNPS_HDMI_PLL_H__ +#define __INTEL_SNPS_HDMI_PLL_H__ + +#include + +struct intel_mpllb_state; + +void intel_snps_phy_compute_hdmi_tmds_pll(struct intel_mpllb_state *pll_state, u64 pixel_clock); + +#endif /* __INTEL_SNPS_HDMI_PLL_H__ */ diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 1ff9602a52f6..feabbd476bb1 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -258,6 +258,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_psr.o \ i915-display/intel_qp_tables.o \ i915-display/intel_quirks.o \ + i915-display/intel_snps_hdmi_pll.o \ i915-display/intel_snps_phy.o \ i915-display/intel_tc.o \ i915-display/intel_vblank.o \ From patchwork Tue Aug 6 12:58:23 2024 Content-Type: text/plain; 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d="scan'208";a="79762915" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2024 05:57:15 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com Subject: [PATCH 2/5] drm/i915/snps_phy: Use HDMI PLL algorithm for DG2 Date: Tue, 6 Aug 2024 18:28:23 +0530 Message-ID: <20240806125827.2183899-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125827.2183899-1-ankit.k.nautiyal@intel.com> References: <20240806125827.2183899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Try SNPS_PHY HDMI alogorithm, if there are no pre-computed tables. Also get rid of the helper to get rate for HDMI snps phy, as we no longer depend only on pre-computed tables. v2: -Prefer pre-computed tables over computed values from algorithm. (Jani) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 - drivers/gpu/drm/i915/display/intel_snps_phy.c | 37 +++++-------------- drivers/gpu/drm/i915/display/intel_snps_phy.h | 1 - 3 files changed, 9 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 19498ee455fa..bed54a3588d9 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1887,8 +1887,6 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, */ if (DISPLAY_VER(dev_priv) >= 14) return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock); - else if (IS_DG2(dev_priv)) - return intel_snps_phy_check_hdmi_link_rate(clock); return MODE_OK; } diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index e6df1f92def5..2e7e281625e8 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -10,6 +10,7 @@ #include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_snps_hdmi_pll.h" #include "intel_snps_phy.h" #include "intel_snps_phy_regs.h" @@ -1787,24 +1788,9 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state, int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); const struct intel_mpllb_state * const *tables; int i; - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { - if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) - != MODE_OK) { - /* - * FIXME: Can only support fixed HDMI frequencies - * until we have a proper algorithm under a valid - * license. - */ - drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n", - crtc_state->port_clock); - return -EINVAL; - } - } - tables = intel_mpllb_tables_get(crtc_state, encoder); if (!tables) return -EINVAL; @@ -1816,6 +1802,14 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, } } + /* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { + intel_snps_phy_compute_hdmi_tmds_pll(&crtc_state->dpll_hw_state.mpllb, + crtc_state->port_clock); + + return 0; + } + return -EINVAL; } @@ -1981,19 +1975,6 @@ void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN; } -int intel_snps_phy_check_hdmi_link_rate(int clock) -{ - const struct intel_mpllb_state * const *tables = dg2_hdmi_tables; - int i; - - for (i = 0; tables[i]; i++) { - if (clock == tables[i]->clock) - return MODE_OK; - } - - return MODE_CLOCK_RANGE; -} - void intel_mpllb_state_verify(struct intel_atomic_state *state, struct intel_crtc *crtc) { diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h index bc08b92a7cd9..1dd564ed9fa8 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h @@ -30,7 +30,6 @@ void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, const struct intel_mpllb_state *pll_state); -int intel_snps_phy_check_hdmi_link_rate(int clock); void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_mpllb_state_verify(struct intel_atomic_state *state, From patchwork Tue Aug 6 12:58:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13754869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7433C52D73 for ; Tue, 6 Aug 2024 12:57:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 74B4310E362; Tue, 6 Aug 2024 12:57:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="T9wy2whx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A0E610E361; Tue, 6 Aug 2024 12:57:18 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="79762925" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2024 05:57:16 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com Subject: [PATCH 3/5] drm/i915/cx0_phy_regs: Add C10 registers bits Date: Tue, 6 Aug 2024 18:28:24 +0530 Message-ID: <20240806125827.2183899-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125827.2183899-1-ankit.k.nautiyal@intel.com> References: <20240806125827.2183899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add C10 register bits to be used for computing HDMI PLLs with algorithm. Signed-off-by: Ankit Nautiyal --- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index ab3ae110b68f..56443bf3e7cf 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -202,10 +202,34 @@ /* C10 Vendor Registers */ #define PHY_C10_VDR_PLL(idx) (0xC00 + (idx)) +#define C10_PLL0_SSC_EN REG_BIT8(0) +#define C10_PLL0_DIVCLK_EN REG_BIT8(1) +#define C10_PLL0_DIV5CLK_EN REG_BIT8(2) +#define C10_PLL0_WORDDIV2_EN REG_BIT8(3) #define C10_PLL0_FRACEN REG_BIT8(4) +#define C10_PLL0_PMIX_EN REG_BIT8(5) +#define C10_PLL0_ANA_FREQ_VCO_MASK REG_GENMASK8(7, 6) +#define C10_PLL1_DIV_MULTIPLIER_MASK REG_GENMASK8(7, 0) +#define C10_PLL2_MULTIPLIERL_MASK REG_GENMASK8(7, 0) #define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0) +#define C10_PLL8_SSC_UP_SPREAD REG_BIT(5) +#define C10_PLL9_FRACN_DENL_MASK REG_GENMASK8(7, 0) +#define C10_PLL10_FRACN_DENH_MASK REG_GENMASK8(7, 0) +#define C10_PLL11_FRACN_QUOT_L_MASK REG_GENMASK8(7, 0) +#define C10_PLL12_FRACN_QUOT_H_MASK REG_GENMASK8(7, 0) +#define C10_PLL13_FRACN_REM_L_MASK REG_GENMASK8(7, 0) +#define C10_PLL14_FRACN_REM_H_MASK REG_GENMASK8(7, 0) #define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0) #define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3) +#define C10_PLL15_PIXELCLKDIV_MASK REG_GENMASK8(7, 6) +#define C10_PLL16_ANA_CPINT REG_GENMASK8(6, 0) +#define C10_PLL16_ANA_CPINTGS_L REG_BIT(7) +#define C10_PLL17_ANA_CPINTGS_H_MASK REG_GENMASK8(5, 0) +#define C10_PLL17_ANA_CPPROP_L_MASK REG_GENMASK8(7, 6) +#define C10_PLL18_ANA_CPPROP_H_MASK REG_GENMASK8(4, 0) +#define C10_PLL18_ANA_CPPROPGS_L_MASK REG_GENMASK8(7, 5) +#define C10_PLL19_ANA_CPPROPGS_H_MASK REG_GENMASK8(3, 0) +#define C10_PLL19_ANA_V2I_MASK REG_GENMASK8(5, 4) #define PHY_C10_VDR_CMN(idx) (0xC20 + (idx)) #define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1) From patchwork Tue Aug 6 12:58:25 2024 Content-Type: text/plain; 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d="scan'208";a="79762939" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2024 05:57:18 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com Subject: [PATCH 4/5] drm/i915/pll_algorithm: Compute C10 HDMI PLLs with algorithm Date: Tue, 6 Aug 2024 18:28:25 +0530 Message-ID: <20240806125827.2183899-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125827.2183899-1-ankit.k.nautiyal@intel.com> References: <20240806125827.2183899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add support for computing C10 HDMI PLLS using the HDMI PLL algorithm. v2: -Fixed styling issues. (Jani) Signed-off-by: Ankit Nautiyal --- .../drm/i915/display/intel_snps_hdmi_pll.c | 76 +++++++++++++++++++ .../drm/i915/display/intel_snps_hdmi_pll.h | 2 + 2 files changed, 78 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c index d2e1f42e1a5a..03a6aedf7276 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c @@ -5,6 +5,7 @@ #include +#include "intel_cx0_phy_regs.h" #include "intel_display_types.h" #include "intel_snps_phy.h" #include "intel_snps_phy_regs.h" @@ -284,3 +285,78 @@ void intel_snps_phy_compute_hdmi_tmds_pll(struct intel_mpllb_state *pll_state, u pll_state->mpllb_sscen = REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, pll_params.ssc_up_spread); } + +void intel_c10_phy_compute_hdmi_tmds_pll(struct intel_c10pll_state *pll_state, u64 pixel_clock) +{ + /* x axis frequencies. One curve in each array per v2i point */ + static const u64 c10_curve_freq_hz[2][8] = { + { 2500000000ULL, 3000000000ULL, 3000000000ULL, 3500000000ULL, 3500000000ULL, + 4000000000ULL, 4000000000ULL, 5000000000ULL }, + { 4000000000ULL, 4600000000ULL, 4601000000ULL, 5400000000ULL, 5401000000ULL, + 6600000000ULL, 6601000000ULL, 8001000000ULL } + }; + + /* y axis heights multiplied with 1000000000 */ + static const u64 c10_curve_0[2][8] = { + { 41174500, 48605500, 42973700, 49433100, 42408600, 47681900, 40297400, 49131400 }, + { 82056800, 94420700, 82323400, 96370600, 81273300, 98630100, 81728700, 99105700} + }; + + static const u64 c10_curve_1[2][8] = { + { 73300000000000ULL, 66000000000000ULL, 83100000000000ULL, 75300000000000ULL, + 99700000000000ULL, 92300000000000ULL, 125000000000000ULL, 110000000000000ULL }, + { 53700000000000ULL, 47700000000000ULL, 62200000000000ULL, 54400000000000ULL, + 75100000000000ULL, 63400000000000ULL, 90600000000000ULL, 76300000000000ULL } + }; + + /* Multiplied with 1000000000000 */ + static const u64 c10_curve_2[2][8] = { + { 2415790000ULL, 3136460000ULL, 2581990000ULL, 3222670000ULL, 2529330000ULL, + 3042020000ULL, 2336970000ULL, 3191460000ULL}, + { 4808390000ULL, 5994250000ULL, 4832730000ULL, 6193730000ULL, 4737700000ULL, + 6428750000ULL, 4779200000ULL, 6479340000ULL } + }; + + struct pll_output_params pll_params; + u32 refclk = 38400000; + u32 prescaler_divider = 0; + u32 ref_range = 1; + u32 ana_cp_int_gs = 30; + u32 ana_cp_prop_gs = 28; + + compute_hdmi_tmds_pll(pixel_clock, refclk, ref_range, + ana_cp_int_gs, ana_cp_prop_gs, + c10_curve_freq_hz, c10_curve_0, + c10_curve_1, c10_curve_2, prescaler_divider, + &pll_params); + + pll_state->tx = 0x10; + pll_state->cmn = 0x1; + pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) | + REG_FIELD_PREP(C10_PLL0_FRACEN, pll_params.fracn_en) | + REG_FIELD_PREP(C10_PLL0_PMIX_EN, pll_params.pmix_en) | + REG_FIELD_PREP(C10_PLL0_ANA_FREQ_VCO_MASK, pll_params.ana_freq_vco); + pll_state->pll[2] = REG_FIELD_PREP(C10_PLL2_MULTIPLIERL_MASK, pll_params.multiplier); + pll_state->pll[3] = REG_FIELD_PREP(C10_PLL3_MULTIPLIERH_MASK, pll_params.multiplier >> 8); + pll_state->pll[8] = REG_FIELD_PREP(C10_PLL8_SSC_UP_SPREAD, pll_params.ssc_up_spread); + pll_state->pll[9] = REG_FIELD_PREP(C10_PLL9_FRACN_DENL_MASK, pll_params.fracn_den); + pll_state->pll[10] = REG_FIELD_PREP(C10_PLL10_FRACN_DENH_MASK, pll_params.fracn_den >> 8); + pll_state->pll[11] = REG_FIELD_PREP(C10_PLL11_FRACN_QUOT_L_MASK, pll_params.fracn_quot); + pll_state->pll[12] = REG_FIELD_PREP(C10_PLL12_FRACN_QUOT_H_MASK, + pll_params.fracn_quot >> 8); + + pll_state->pll[13] = REG_FIELD_PREP(C10_PLL13_FRACN_REM_L_MASK, pll_params.fracn_rem); + pll_state->pll[14] = REG_FIELD_PREP(C10_PLL14_FRACN_REM_H_MASK, pll_params.fracn_rem >> 8); + pll_state->pll[15] = REG_FIELD_PREP(C10_PLL15_TXCLKDIV_MASK, pll_params.tx_clk_div) | + REG_FIELD_PREP(C10_PLL15_HDMIDIV_MASK, pll_params.hdmi_div); + pll_state->pll[16] = REG_FIELD_PREP(C10_PLL16_ANA_CPINT, pll_params.ana_cp_int) | + REG_FIELD_PREP(C10_PLL16_ANA_CPINTGS_L, ana_cp_int_gs); + pll_state->pll[17] = REG_FIELD_PREP(C10_PLL17_ANA_CPINTGS_H_MASK, ana_cp_int_gs >> 1) | + REG_FIELD_PREP(C10_PLL17_ANA_CPPROP_L_MASK, pll_params.ana_cp_prop); + pll_state->pll[18] = + REG_FIELD_PREP(C10_PLL18_ANA_CPPROP_H_MASK, pll_params.ana_cp_prop >> 2) | + REG_FIELD_PREP(C10_PLL18_ANA_CPPROPGS_L_MASK, ana_cp_prop_gs); + + pll_state->pll[19] = REG_FIELD_PREP(C10_PLL19_ANA_CPPROPGS_H_MASK, ana_cp_prop_gs >> 3) | + REG_FIELD_PREP(C10_PLL19_ANA_V2I_MASK, pll_params.mpll_ana_v2i); +} diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h index 9f60bd9bacbe..288289ec593f 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h @@ -8,8 +8,10 @@ #include +struct intel_c10pll_state; struct intel_mpllb_state; void intel_snps_phy_compute_hdmi_tmds_pll(struct intel_mpllb_state *pll_state, u64 pixel_clock); +void intel_c10_phy_compute_hdmi_tmds_pll(struct intel_c10pll_state *pll_state, u64 pixel_clock); #endif /* __INTEL_SNPS_HDMI_PLL_H__ */ From patchwork Tue Aug 6 12:58:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13754871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 838E2C52D70 for ; Tue, 6 Aug 2024 12:57:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2848B10E365; Tue, 6 Aug 2024 12:57:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LLXKAils"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id B199810E367; Tue, 6 Aug 2024 12:57:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722949041; x=1754485041; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K49QUZ7c/wBLECYVYX6YFsWbazoR+STKljVi1BfB+Yc=; b=LLXKAilsIMPKdxJsERnaaNn/mGY3fZQ2//kdDrGSgNN/7X2h6zwZLcIe z8Ype9TqcTGwIiZygv2aNVlzASRB392lCADgH/LN8ZLHUFxRv2kCkKk4o mzGPADO0gZFc3xQEpEAJ5rHoiQ0WN4asosjNGHEWCn0Nj7HA3x0X1eXY0 +JyvTo3+VmYM+HsfVvEFCGIZKig/wvzYZ/ME54pqFjmSlFOFBA8rG5Kd2 QpKD9gwAZ33sUUGCidNbqiGALiwSylroVwsiRCzD/1dbrGWNWjxnS10N0 StYLQkG2CRvFas/XFytSSfbtj6YdNNZ4V7YvWcP99RT2Vg+O+jdilYKeE w==; X-CSE-ConnectionGUID: w0sRS69TR0WsI2BXkCnDMQ== X-CSE-MsgGUID: XtClBFH3TwuyHGElgQnEHg== X-IronPort-AV: E=McAfee;i="6700,10204,11156"; a="21142087" X-IronPort-AV: E=Sophos;i="6.09,267,1716274800"; d="scan'208";a="21142087" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2024 05:57:21 -0700 X-CSE-ConnectionGUID: lYI2SIOXS7akS9OVSMN22A== X-CSE-MsgGUID: NMZe+NJ1SkiZNsgDcYFe7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,267,1716274800"; d="scan'208";a="79762954" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2024 05:57:20 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com Subject: [PATCH 5/5] drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY Date: Tue, 6 Aug 2024 18:28:26 +0530 Message-ID: <20240806125827.2183899-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125827.2183899-1-ankit.k.nautiyal@intel.com> References: <20240806125827.2183899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Try HDMI PLL alogorithm for C10 PHY, if there are no pre-computed tables. Also get rid of the helpers to get rate for HDMI for C10/20 PHY, as we no longer depend only on pre-computed tables. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 49 +++++--------------- drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 - drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ---- 3 files changed, 11 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 4a6c3040ca15..8ae290268233 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -16,6 +16,7 @@ #include "intel_hdmi.h" #include "intel_panel.h" #include "intel_psr.h" +#include "intel_snps_hdmi_pll.h" #include "intel_tc.h" #define MB_WRITE_COMMITTED true @@ -1970,19 +1971,6 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = { NULL, }; -static int intel_c10_phy_check_hdmi_link_rate(int clock) -{ - const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables; - int i; - - for (i = 0; tables[i]; i++) { - if (clock == tables[i]->clock) - return MODE_OK; - } - - return MODE_CLOCK_RANGE; -} - static const struct intel_c10pll_state * const * intel_c10pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) @@ -2044,6 +2032,16 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state, } } + /* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { + intel_c10_phy_compute_hdmi_tmds_pll(&crtc_state->dpll_hw_state.cx0pll.c10, + crtc_state->port_clock); + intel_c10pll_update_pll(crtc_state, encoder); + crtc_state->dpll_hw_state.cx0pll.use_c10 = true; + + return 0; + } + return -EINVAL; } @@ -2210,31 +2208,6 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_ return 0; } -static int intel_c20_phy_check_hdmi_link_rate(int clock) -{ - const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables; - int i; - - for (i = 0; tables[i]; i++) { - if (clock == tables[i]->clock) - return MODE_OK; - } - - if (clock >= 25175 && clock <= 594000) - return MODE_OK; - - return MODE_CLOCK_RANGE; -} - -int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock) -{ - struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi); - - if (intel_encoder_is_c10phy(&dig_port->base)) - return intel_c10_phy_check_hdmi_link_rate(clock); - return intel_c20_phy_check_hdmi_link_rate(clock); -} - static const struct intel_c20pll_state * const * intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index 9004b99bb51f..2e3076261d30 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -43,7 +43,6 @@ bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, const struct intel_cx0pll_state *b); void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); -int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); #endif /* __INTEL_CX0_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index bed54a3588d9..4706adf54dfa 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1878,16 +1878,6 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) return MODE_CLOCK_RANGE; - /* - * SNPS PHYs' MPLLB table-based programming can only handle a fixed - * set of link rates. - * - * FIXME: We will hopefully get an algorithmic way of programming - * the MPLLB for HDMI in the future. - */ - if (DISPLAY_VER(dev_priv) >= 14) - return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock); - return MODE_OK; }