From patchwork Tue Aug 6 12:57:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754913 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2080.outbound.protection.outlook.com [40.107.236.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 485541D47A2 for ; Tue, 6 Aug 2024 13:50:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.80 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952237; cv=fail; b=ZWnKK78vESiKu4URmbMvh0MqIyb+IHJZzqIIoT30PjLXp6XatCBeKTE8MNRCiITJUDswV1hWx2L80Kf3AhIgeT2F+zhAq+NZkX/gKn9mqiF2PTyQtt9b+Z0D+f2VwfA+a2dzoWlHTVzcvV+y25KuRjkVASq1z1HJT1N8y/NnJ2Q= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952237; c=relaxed/simple; bh=XZPzHc79aEcc8hIOXjBmUvuRL52CB58rCIXLN+I8mCg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=esJ3fvTcG/mZxqsIaICbrF9dyMZfnm8U3Eq78cOKqVKEpXHb5VcKXC06Rp9K0NcQddZ7Gx/3dBIc/8CEVgq+ipAqv8DRcHz1VuYTTwcOJ2fwC+12SJT/bDl816WpHiiFZkLM8vhUFdYtHA/iZn8iP9eZeNUDh5HqUgChMFYU4lc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Ow+by+J6; arc=fail smtp.client-ip=40.107.236.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Ow+by+J6" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=spoHGoaTVpVOykd4XEwKbO3Tjv7joCSjFi3tACYE6v+Cbs59CPdbGgDD9K1d3SxCgCy18pMnMDYfLTNPlFjh1z0OZ6id1SChcRtNOZkE0/nOVOOJCokD39eKsPMCKM5XXEye4hqmIeuZh05o/Bjdn4Y61XIV9Rm4olJYKaZyZiuAo5GL0OhzSgh+8w/l0xo01xOjkA6U2iDrMsCbkP1Y3YCP8hRu6YDIApLXzNVMOEzRgDY4RaBAbkADPV6bgM7QimUMxN5Kjb0yrp8FY8Oiw7jQ2z3L+CsgCIyYWLfoXRHEJhKQwr3DngHAdhFEcDibU/4uNjhlHu+Y0yh9DeSJEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=DifpBBpLegKOciyEyO0MkTLjDbgdi31gvoClxiT5XS8=; b=baFxuze8bVUSHujmPZDzR+iQvWr73/GLEcaVP5IvRp7/hKEHd4In1DCZO4QizzDS/XdCg3t3KDM2ZeIWIdswNKMOjvhnmh3RF9B62uC/4Lzfv1GYZC1Aw37eucLgMnFRNooVH5Lj6IJUVgVTYDLKFq/bU9DATblrrnMa8rl4CrVAT6KeJxXDYyp0aK29iJHZj9nuNdMUUVHArgYKktHqgYOgCADLE/a3eUgtgVjqATfUXPQwBiGD9ZNlSpCZjh2GlT/hWBfR7SxbeHBIIQX6O3hZWIYxgxdgrjo0tu91hGnQsCJ5Dy/9g2fipHqhUOmtJyUbkpwxHUC9VvKBUHHYQg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DifpBBpLegKOciyEyO0MkTLjDbgdi31gvoClxiT5XS8=; b=Ow+by+J6DMMzBNdhqTHGbpPjW9czg+SDzRgKpJcfwIUhkMgxkcYv1a7nyPFtlrNaEnDKCuw+DV0UItbDZekVgicxLIyK3C1IYfVXEe+pZh5A47BwwTb3KV1RMC9Ik17pLllNs/pItGJHmNjg4XoJZGs6kO1S85cD/98bIJOllpyG4Hs6JJ05LeBgSt5XuhyZgyFj8pIwugwxJsFd4l3gujF/+KzaKknE7gND7BU9Cy3F+Ru0TKhNtGT14STh/dmgkyyZucRQjugp5MjlEujs+HZSz/BBgWUUE1rbzO6Gl8LAQO6qFmlqnYWoyjlmCkW/r+W+/d2d5HTg+q2bwRWFng== Received: from CH0PR03CA0259.namprd03.prod.outlook.com (2603:10b6:610:e5::24) by SJ2PR12MB8011.namprd12.prod.outlook.com (2603:10b6:a03:4c8::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7762.33; Tue, 6 Aug 2024 13:50:28 +0000 Received: from CH2PEPF0000009E.namprd02.prod.outlook.com (2603:10b6:610:e5:cafe::8) by CH0PR03CA0259.outlook.office365.com (2603:10b6:610:e5::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.28 via Frontend Transport; Tue, 6 Aug 2024 13:50:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH2PEPF0000009E.mail.protection.outlook.com (10.167.244.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Tue, 6 Aug 2024 13:50:27 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:39 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:39 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 05:59:36 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Chris Mi , Roi Dayan , Tariq Toukan Subject: [PATCH net-next 01/11] net/mlx5: E-Switch, Increase max int port number for offload Date: Tue, 6 Aug 2024 15:57:54 +0300 Message-ID: <20240806125804.2048753-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009E:EE_|SJ2PR12MB8011:EE_ X-MS-Office365-Filtering-Correlation-Id: 2fd27016-b287-409a-90a0-08dcb61ebaab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: fRtykhpAVNqoDiemQQSulQ+z5Ji3wAtlfepVcUiNtLMWoiwf15nEx3qdHEttq/WRn6KZ7H4Pk6OR+ofxOBWmrPcNHjMHV6ORR7MznFrZjdgDuC4deoik09sDX0TzUDWIdxUWWMbhjpwlS5XlUWzscCjn21w9h96Brj2wAvY/ozBWnxighiGNE5qlOCDK0UUJJfptrgUgJm0PKY/1/OAb/ngjUyQa+d+Mi6hBb+L2a2LzWLwpeQ/dFA81wg68+2ZTqS40PuuCBqHcQACmtayNJsYIcWCN2hTTAsWfadYGwqWwncBggtMkLWKsPksvIQezkaY1yuUGN13Mfi5J5MVzhUFtaexxpmbzmU1zKrJdSH5OmXhsPudkjutvtPcHDnmH8JfhKfsW74MZhT/Srm43qSWWgh/G7nmHzV+hGCqzAX/Yzr5KIyT2NqFAVyrYGIWvWlj6EEk/OjvZH4zSgWBEpPhRf0Rw9rRYBuSCcz2T3uhvZXJpyQiuPbjt+IIL18nrjRYgccCffLRHXd0tIqzWuNMr5VN8M+JfHK8sllGOmtSVY7m25fDDUle+tW6gCj8KEh+IBazVOCoEsjldTtXf1V7tU+93/aK4S+JUkhfXrEgczCPl0ZN/2QNifQRSFcL4CZOmD1FkLZed53M4QH0NZcakGyuoAb3fDZbMZnTeKhLYUjY3gdLcAzuX1FnJtrM5jKTTSkhqoJ9Za+4gcIY4xtBKhXF1B9NUw0v9L4gNtJdVeaFHNXi0HjUof0vawMel2XbE3zrruNDpbLDbwwXY4ejMSSldmnsVj2to08Ki4r2wpC1gukNDh0NoT35Fysyj0Qg+v3LlKEi/prIh4mgqVyRQ3LaoGxqpl6S40ADRDtMLeYEJ2wAC5iMJkAGATxk/LZHSfEeG1vz/mkrwLZ81WEBz+Hn5E2x1qdKsQzMRXGTKMirZzyTtCPBtPQ9xV/Cv0uTAGYL1813m0FqihIMhom5++/6PkX8wBnUV5X+TaONieo1/ixWqC3NAMHn7YqPmrp4FA6nq0rGsKIVvqjXy4bbbOq3fXBH8hvNqEvEgWHXBAPqee+A5XlzoL9mA8kL/QfZ6IRFMlaqYru0AI3/qVUvKayAepK0eLqkZvVuKUDK6h+MV4tXW2sxloJQLYZNRSIXS+4tMBWyeF+cYcvZnJO6HUAuGnh9pUPp5M/DeJ0YwkMD6Br8CFY0CCMuTCcBMNOn1WHchOkIZfKhE72wkDa7o5N6f2r1cOZjQZ24eWMIXBGF6OuJPbB1fLoeTKh355PYl4YmHodSFEf94HhM45g06MK8phlDXxZMLd3nvNeOPCKoNJPtD6ARsMNlg1hDP0OQqyKnulUCgPoWvE73vWqFqGQWI3bT7erchGa8c3zrsnDdvFn4DBXnVXsNFspdJdGXCpgtf2OFgwmFHgRkQUPp+nMdrc6oIW2TeKd9LJMwraT7hPSYw1iQN4v/NPggY X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:50:27.5285 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2fd27016-b287-409a-90a0-08dcb61ebaab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8011 X-Patchwork-Delegate: kuba@kernel.org From: Chris Mi Currently MLX5E_TC_MAX_INT_PORT_NUM is 8. Usually int port has one ingress and one egress rules. But sometimes, a temporary rule can be offloaded as well, eg: recirc_id(0),in_port(br-phy),eth(src=10:70:fd:87:57:c0,dst=33:33:00:00:00:16), eth_type(0x86dd),ipv6(frag=no), packets:2, bytes:180, used:0.060s, actions:enp8s0f0 If one int port device offloads 3 rules, only 2 devices can offload. Other devices will hit the limit and fail to offload. Actually it is insufficient for customers. So increase the number to 32. Signed-off-by: Chris Mi Reviewed-by: Roi Dayan Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_tc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h index c24bda56b2b5..b982e648ea48 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h @@ -139,7 +139,7 @@ struct mlx5_rx_tun_attr { #define MLX5E_TC_TABLE_CHAIN_TAG_BITS 16 #define MLX5E_TC_TABLE_CHAIN_TAG_MASK GENMASK(MLX5E_TC_TABLE_CHAIN_TAG_BITS - 1, 0) -#define MLX5E_TC_MAX_INT_PORT_NUM (8) +#define MLX5E_TC_MAX_INT_PORT_NUM (32) #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) From patchwork Tue Aug 6 12:57:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754906 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2051.outbound.protection.outlook.com [40.107.101.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB2F31E7A5A for ; Tue, 6 Aug 2024 13:50:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.101.51 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952233; cv=fail; b=FQAl75SHIuOhIZJ18AB9iJ09hCgakrIspu5ggTRSRXsOJGquuMDwrB9VZJcRaqNYAgkXK/7RG+ia0As5pum2tG1HrNBwMecxy9a2aQjHNkVUtPaSp3aXL7ayBE4qSV9X6gBZ/7jCS8kTOzbdxURNsE3EdnaPJ2+11cyPEIvuZLY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952233; c=relaxed/simple; bh=14Mfjx2KYmGcKHUeF6uAMhKJStDDKIhRsIkub5fbIis=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KfN5b5/PGgc/tIy39T6ib9ZaClD4bCXhtWDakYUmHexDFurmOdQplQjLKVw6289VjPP51bNwf8WWuz5rfAN7Wfb4Qr47U9mSrGe9CDSeSr99pe/afjQQuLsJJpjC4K/mlmEpTF3RlMjHxSdEcILTsttxgIDeTrSsqniFYuh6bvA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=cLzuFqOi; arc=fail smtp.client-ip=40.107.101.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="cLzuFqOi" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DEbv+816GZjDqCo95pPGZI6aLFKRvcqER7/b1Mmg0ie3sd2a0Hau/jqQI8o1VnzQYFGSDh5PJum7UX+wkX5PUtYHZtUHX57TaNI0nFVPMw9XpWlf2c+54R/GU84Xl/16hqwyTQWkHv9sEcCCQmAv5w1CykezMMGODy3SK0R932aq19MsFVteET+FdQ0xlsQkDEsaJPQopbwrJMO/6fhYv17GbCpq7fzdygA0NG2KPLBwcLylZeKUQNJW8XfDLiG6tyoSsp58OJsPCAl5jP7G2lA9Nq/al6m6FkNcrn7vg0d6PbagsdYDLkcq3KEzSjRI8LuldBKSrRAneWi7SbtFGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0HgOyTCRBIFb8iH+CNAlb69+yaguk3+v+7d8wvveXdI=; b=gcpx7g0oLiESkWV54MAk9s1Vzl51/LOh6OZjt732w7CdSZGAD7400wXoD5Z1N/AqIYgJxaSxdnqqSLs63LKOZi0Jrvb+SeqH2x+PfMeJraCZKQXpFdG1omMV51SMDj2CKBZfVc2uCCE1pPovM5qIs/5G731WZlr5lVoNdv1rUisQm1OefAfIUtcSvu7oHHre0DgBMDu/avFnEZTH2gYMPmODSWQ3lBGR6uzFrqSFOZHReq18StJXSS7+J5c+nSG2BzewSa0MrCwvKsckMAuUGatkvZ6El1ssE+omrKeffJaLLNbbSjaQsNb2wsBQhVJEbXE3Uyo43To0pdtVmty+pQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0HgOyTCRBIFb8iH+CNAlb69+yaguk3+v+7d8wvveXdI=; b=cLzuFqOiFNDxSewUlblBfmj/uFH7HyfxgoTghhYen/WGchgPaygmIXGYsLTFhSYZkbDFtVG8PAq+WnjskCyiGEJKdWfcFjW/s4/XJ6lb2dWTPmA3oCI3BTbPvLj/rL3bzltFkJ+J2Am0LVVXEDw3VpbzeAtl2p79nl+Q9fwn1Uxtb/P5WTPhuofjHrSQQGCK0QAs2B5VMWl3g0+8Gfq+XWUmHh39CZgFz2wrRZ55C8bKPX9xkR5Ip5XT0dCNqAemuiF6qMP9Xzzbm+j3/ApQY/pS6Q5rbXHctm4hcjrlQixu1G1EgbHWN31ivszaDoUHYNDENlA3V1Mx0zX5HESUVA== Received: from CH0PR03CA0055.namprd03.prod.outlook.com (2603:10b6:610:b3::30) by SN7PR12MB6743.namprd12.prod.outlook.com (2603:10b6:806:26d::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.21; Tue, 6 Aug 2024 13:50:28 +0000 Received: from CH2PEPF0000009B.namprd02.prod.outlook.com (2603:10b6:610:b3:cafe::27) by CH0PR03CA0055.outlook.office365.com (2603:10b6:610:b3::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.29 via Frontend Transport; Tue, 6 Aug 2024 13:50:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH2PEPF0000009B.mail.protection.outlook.com (10.167.244.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Tue, 6 Aug 2024 13:50:27 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:43 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:42 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 05:59:39 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Jianbo Liu , Tariq Toukan Subject: [PATCH net-next 02/11] net/mlx5e: Enable remove flow for hard packet limit Date: Tue, 6 Aug 2024 15:57:55 +0300 Message-ID: <20240806125804.2048753-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009B:EE_|SN7PR12MB6743:EE_ X-MS-Office365-Filtering-Correlation-Id: 7619f6e3-bc1a-4af8-aa50-08dcb61ebac0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: K9/+HnHxEwJE0Kmt6jIAUzVBE9whnno+oorCurndCqpy1yJNPmGq7ZAUW4Aa07CTkiG3NerP2zuBU9O/D2v5gTpmmqntCtgH3j4rHd94sz2dq96WljCCh+UJ6ab46+u9ZREOt4SW7gOSrCsOQ1yRUBHkjyE5ORrYZjwe+HE2cnGhMyRMpYGL3C07R+xuYerk6QrMQIWRNW4ydWNTz/OSMQ2JBFgfP/QYrU6PsWPcHF+tHJts5aNq5nl+j8RbYhH9GP3BWgQPy5knJ/QLDnyzduhFeOwvVbP7aJ/6V9yLZ4iBI0M5M4grzgPwzUHthBZrKeMIMk7zqKS6b9PNqub2qI7ekrTatfxCZi2oSxaCyni/Y7EYfxifUr1dGxylYO0StQJnzkFOH/YZPDORvxhPfpcht8XEZGejMNa7WT5KxQ4FlKNAkCsYmj7/N7NRAMQz4P6fjHJZp2yNw1lhrhDRejbdU+tOf10D6BoQQYXSPS9u/fwPs8IeuJlDC0rBbWKS7GYvYQr6Rk7gCA0k/heEwp+YYngPaRBvcyPXEZkuqk/w0ZywWg0zrrLJFdYcdEgWXSRUi28cyLmLWgwPJtzD8A2UTCqxpFvuLrowFUrplEMQN2RJIPsqml7FF8gqV/qzQyhQu/ltF1NzFKRjETdoeyjkwkVC3134mKh1SlkpBSzwlCgbFt6G1C0RNPCuQOZaBX91EaFtxC8h0zlLlWJD4w+sTWeuHFfU5BbRJPTYRZVi+EI1ZdngHe8+8M5AUTiiXgcBgjxokqvOyHufuCKjBygpwTiS2cewGoBPGErOzMqtnDcWpe8PJxKZnnY/Vd/NjUlR4kJsjFXl9nzCM3PfOSzGuYxI+JhUBU2eHuxDYIN+ogzvEW8tR0M7/1cdhHr7+DmhGvWoFNqM7Q0nop3X2AtnVUM7Is35Gii8BHBgIbVJWSg4ZF9IIwyvWh40JHdVtNJNlEE3ycNUq/Ycy92k4CSpujoAn1xL0g8xa5xnZzUftAR7v5Y4zSu2NkFSLWjQOIQEbR6d3ksMgIrGkAu9DnXccrPU6o0sYTMN0oVr3To96KgFwUz8SYquL+LcbR3FPy9IvyCyXZSSBfGELwntmOy/eYTHgd5Uo9WBVzF2yY61jz6vQyEamAIPdGUe2nTOeuCvzM2GWcH/uUX69BDWS0a8EwdsQP0tZIHS8tfgSupGxlLmRtJf+92glvMkGJIqqETwWkgQEoK3mFS0GPWSFaHsKg4G7pQlxnEHBeap0j4BzJHzujCglZOHaAavT3Z2Mmerl1Y8ZPNJVwC5uaXfV81u9JCmUtTdmCJWfXW7MFepoC1Cx3zbNrEAkmWglxYIlQnCY+dW7KK0rWKa8KipSWjB8zS1AwNJS+6ZoWySLIoYWo+prsd4+2HrniJaDVmzvab4iPscVxW8/0utF1oaJYi9an2nDmeMfLof8YVnBJYQi3uFmh0yCtoFkl+XJuEj X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:50:27.6668 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7619f6e3-bc1a-4af8-aa50-08dcb61ebac0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6743 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu In the commit a2a73ea14b1a ("net/mlx5e: Don't listen to remove flows event"), remove_flow_enable event is removed, and the hard limit usually relies on software mechanism added in commit b2f7b01d36a9 ("net/mlx5e: Simulate missing IPsec TX limits hardware functionality"). But the delayed work is rescheduled every one second, which is slow for fast traffic. As a result, traffic can't be blocked even reaches the hard limit, which usually happens when soft and hard limits are very close. In reality it won't happen because soft limit is much lower than hard limit. But, as an optimization for RX to block traffic when reaching hard limit, need to set remove_flow_enable. When remove flow is enabled, IPSEC HARD_LIFETIME ASO syndrome will be set in the metadata defined in the ASO return register if packets reach hard lifetime threshold. And those packets are dropped immediately by the steering table. Signed-off-by: Jianbo Liu Reviewed-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c index 797db853de36..53cfa39188cb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c @@ -127,6 +127,7 @@ static void mlx5e_ipsec_packet_setup(void *obj, u32 pdn, MLX5_SET(ipsec_aso, aso_ctx, remove_flow_pkt_cnt, attrs->lft.hard_packet_limit); MLX5_SET(ipsec_aso, aso_ctx, hard_lft_arm, 1); + MLX5_SET(ipsec_aso, aso_ctx, remove_flow_enable, 1); } if (attrs->lft.soft_packet_limit != XFRM_INF) { From patchwork Tue Aug 6 12:57:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754908 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2058.outbound.protection.outlook.com [40.107.243.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15DE21D6181 for ; Tue, 6 Aug 2024 13:50:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952234; cv=fail; b=fkvfF9OO1gyAHndJc0nwjw7QqX6H9nAxLlRENLGosiydoIAbigZOA9O3nhH8jhxoPmGKkCsJetuxP1vYrtEkWzxJjLaLRLoEX9YPtVWPn+r/aw6eQa36YmSDUwElehRMjEt3/ZWzNeNEKgN+flK9fQTc0R7eD+thVI4HYyj3D2o= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952234; c=relaxed/simple; bh=FQYvjhZWDp7sAQAPINj7cYImL9blQyjDw2CPfmZ+gUc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uDfQWJzREOCjhFp0vt42541S8nuxRatxuiEhIB3bFvznU9bcWVaqoLeJJiHgwPsQdmcjGJWXPTPM8J4/KK1J/g/3uww8sD45TZ+mosXUvc2r/w9yQmz5bQ6e4C9QveZ4kKj9RQw13p2GrtyA0DDd9yRg97dSkHDCTxSo94seYbA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=lReU5af3; arc=fail smtp.client-ip=40.107.243.58 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="lReU5af3" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=g+sAjh6DwWDOO7vORNR4tsSm3Wpmb5xBgr+7gizDLnhe2chpoOuNOGAeNOmz9eKpUz+zmZ7Ec6Qf7ExDmbYD/erR9w0MOfjFm5lX/6tA6na5h1izWzrHBy2po1sKxuUV4DMW/tpFarl6Y5qy6MtadpLoTD5xrKFbO0Ap6p4vJ8WT4WAYu1i2NNwFbfSANelkwZ2kBLNmL4U8iPPXOuoLd7McrL/d/aG20BhkCFl/NopkWy0mKlrVNTkjgOHn44OR2+j+udQzCa1eAQmTZ7uy2+sutiAtNoZtrbis+eWSw9jhwp6TnM2gmyglSXQZo3ODg5Ra7uiZhddGkmiWnW7TbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=NHbSDNV2T2irJ2x/Z0a2n0hXx/l3aizWt9FIpy62CO4=; b=MJNEZVQdum6pFaKH7fka1ROcDkeA5CMU153O4T/Ob2W2hZSBQaAlJNgJezsNHAEFnzQn7rH66rH2KXvCYkj00n9ChEmHc8zybKGvsVutwJzEELOYl3DxM3vpvaBiRwH3dlpQOzU4HGcHMuSDuNp55fzFa1F9eCfMl9e2tDSSaOMYuC34f5PMsvWE/27O0SPmxVhCfTwiod2RSeVDtADN5IoL40fgZoMtcYkp00dA+zxJIx1fAjznPtO/DcTXLMDRBNlFYggoghuDw+EcFmX5TSnU7JuTrBKsG6mDxx+IzYoEBQmSBCKLQAE+tLOmol7ykZxJ2egTANS0nReKTPM9BQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NHbSDNV2T2irJ2x/Z0a2n0hXx/l3aizWt9FIpy62CO4=; b=lReU5af3UJSOY9xtZ1KG6lfF1p3DICVmdO+oulJFf4GGwYrWkqdtQ1oKMaR8YtuGMKdasKI6punKDVQydCNGWVfywkZvBnYjS8DYi6QDXqETwz+urCLy50/HZhIEfyJe5M2/EsAA5EW2kob6lqZKDvBLVmReYTpiExwA9vpmdTUtO07l1B8+v+VYUYLsNPJN6IQOAoAil6p+viCs4aVqne6jFQ5VXuVK9Js3XBbi4KBVJie38zJ5fy5x4P3cupelP1mjqSbiABuQ/VOcbL9v5kQ2stjWowE0kJZj+BoVt3mD1+vU5f5CbRPdTpEuqmGI12nGPeseq3xU52sxMZYsjg== Received: from CH2PR18CA0045.namprd18.prod.outlook.com (2603:10b6:610:55::25) by IA1PR12MB8407.namprd12.prod.outlook.com (2603:10b6:208:3d9::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.27; Tue, 6 Aug 2024 13:50:28 +0000 Received: from CH2PEPF0000009A.namprd02.prod.outlook.com (2603:10b6:610:55:cafe::b2) by CH2PR18CA0045.outlook.office365.com (2603:10b6:610:55::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.28 via Frontend Transport; Tue, 6 Aug 2024 13:50:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH2PEPF0000009A.mail.protection.outlook.com (10.167.244.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Tue, 6 Aug 2024 13:50:27 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:46 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:45 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 05:59:43 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Jianbo Liu , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 03/11] net/mlx5e: TC, Offload rewrite and mirror on tunnel over ovs internal port Date: Tue, 6 Aug 2024 15:57:56 +0300 Message-ID: <20240806125804.2048753-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009A:EE_|IA1PR12MB8407:EE_ X-MS-Office365-Filtering-Correlation-Id: d2c960a9-524d-4e06-18f2-08dcb61ebadb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: by0hd4S6RTcsjjjFNEJtq8YLGtNx4oMtp9h+AbcXYTzvjav/mG++GVJXeOM031kjr+TlP1YTgvxMGbVi9u/B0SSF0VNhLsj8k9u8OG0x7cvylQlj1GIwUEedOJlTuvXewj3j8QY2wfMj2CaDzyPTUJP6A1dExUmmE8bm16rZMn6MSIYUfnsAST76OObIA+cSNEv3KlI+JG+3rh88UZyHbxLfxXGHbf+YWDrQSUtsyUBHOyE+rD9+/yKTq18qaiQ3j5GDJvT+6hxxwEGW/ad7QcgbAP3AOd65iCYSz+h5yktfNb6hwQc8yZLjKKM/cgDNx5OFkzXgmENCT7qMwjyDYXVxtmm/Lf/rSZ/p9ktqiebz+CNVy/dEkzbEh1TwkLFbkGEAOIBsQ77XQR+r+Kv5tRsMYP7tqdc9KOMnrLj7EtwNL/XJhmVa9Fu5jlVt4KYldHcMz5M3U/C5Cu8Vc3Ym7oSg70EbnCMMsKXmYRN+W7tueuyfG9MoTOZN+eSQ+MgdD6VyYuD6MnxIcPNZz8LZ9zncJB4qHmix2cw+H8IFSOVNOKA0pcuKrmG67R+bd34JFPx9YicSwXX6oMvCHbrPHwgOIaBmTMLfveMzUgLVpXm8nGiVZrE7ZAs9VDrEmiSzSuUtRgbgyDB8NtyQu4T5x+Y4qDtGRMJxyOwHtPm67zGNZjl1pcHu/TTMIauJXJhe2CbHckQGzXr6r4sjfpSbSqxtu5zlpOazyL22NH6EZqQsfrixhHgpg7VmRh2Ohbi+rNyG7gIzEDIY2Mi/Tqm4GUNctpACt4hMPPlwsWatD+UBgzSzWdkR1c7fD4a730Y2ogCHU1nC0y7v2sjWtQcyecMA3GaOCkRmFOs3DfGx85O6lNWlSEjSXmuahckt57WCmPeIzzSEhvV6aroP887RKf0xcSmCTpH+w4MzfeQbfezvsRGmVGwyt3NlqjAWVtsSupeoNJNVRQ4c5ytinOGfZ4t34qcZ0oIl7DIFh/roON8zO692VlXpq7VAFIIT3pZTVPfjrntPmniJHvc6K44a3cZt8JAzRoOWcvBn6yGxE0t936o4D90WtMFM/fVTZibRstLu5qprDTMrUO8y7qZblOAMGGbxKTkj2vwCGNSWTKdmrPB2+XmYdVO6YddEe4nCX2KJbhR3GcTj04vVDFxmDImoCcoq25WPnrvRxJ2tKg21WwGPsJ+wXutDcc9bM0qeKR7pmlmrfKVmPMoOgrzICdQwhZRDLbagltfVWigAQuvlwPVRVokNDy5Khe2qDM+A0KKBNU+X0/+JQuwlroNcD2fI568Wmh/gVzb2QmCuQrqXmhInuz38nEg/mxOJyqGS2vWHpX/f/jGuHRDcrrETZ/UfwQNwn43YkHArpgey3WnTajtpa+517r6USGa6wMts11CLLyuzabND89OjMLHurZOFKmt40ub6DEpApv3NGXVKqZHRDDBM05dryLJPeHFQ X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:50:27.8400 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d2c960a9-524d-4e06-18f2-08dcb61ebadb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8407 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu To offload the encap rule when the tunnel IP is configured on an openvswitch internal port, driver need to overwrite vport metadata in reg_c0 to the value assigned to the internal port, then forward packets to root table to be processed again by the rules matching on the metadata for such internal port. When such rule is combined with header rewrite and mirror, openvswitch generates the rule like the following, because it resets mirror after packets are modified. in_port(enp8s0f0npf0sf1),.., actions:enp8s0f0npf0sf2,set(tunnel(...)),set(ipv4(...)),vxlan_sys_4789,enp8s0f0npf0sf2 The split_count was introduced before to support rewrite and mirror. Driver splits the rule into two different hardware rules in order to offload it. But it's not enough to offload the above complicated rule because of the limitations, in both driver and firmware. To resolve this issue, the destination array is split again after the destination indexed by split_count. An extra rule is added for the leftover destinations (in the above example, it is enp8s0f0npf0sf2), and is inserted to post_act table. And the extra destination is added in the original rule to forward to post_act table, so the extra mirror is done there. Signed-off-by: Jianbo Liu Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/tc_priv.h | 1 + .../net/ethernet/mellanox/mlx5/core/en_tc.c | 103 ++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/en_tc.h | 1 + .../mellanox/mlx5/core/eswitch_offloads.c | 7 ++ 4 files changed, 112 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h index 6cc23af66b5b..efb34de4cb7a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h @@ -109,6 +109,7 @@ struct mlx5e_tc_flow { struct completion init_done; struct completion del_hw_done; struct mlx5_flow_attr *attr; + struct mlx5_flow_attr *extra_split_attr; struct list_head attrs; u32 chain_mapping; }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c index 30673292e15f..a28bf05d98f1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -1739,11 +1739,102 @@ has_encap_dests(struct mlx5_flow_attr *attr) return false; } +static int +extra_split_attr_dests_needed(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr) +{ + struct mlx5_esw_flow_attr *esw_attr; + + if (flow->attr != attr || + !list_is_first(&attr->list, &flow->attrs)) + return 0; + + esw_attr = attr->esw_attr; + if (!esw_attr->split_count || + esw_attr->split_count == esw_attr->out_count - 1) + return 0; + + if (esw_attr->dest_int_port && + (esw_attr->dests[esw_attr->split_count].flags & + MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)) + return esw_attr->split_count + 1; + + return 0; +} + +static int +extra_split_attr_dests(struct mlx5e_tc_flow *flow, + struct mlx5_flow_attr *attr, int split_count) +{ + struct mlx5e_post_act *post_act = get_post_action(flow->priv); + struct mlx5e_tc_flow_parse_attr *parse_attr, *parse_attr2; + struct mlx5_esw_flow_attr *esw_attr, *esw_attr2; + struct mlx5e_post_act_handle *handle; + struct mlx5_flow_attr *attr2; + int i, j, err; + + if (IS_ERR(post_act)) + return PTR_ERR(post_act); + + attr2 = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow)); + parse_attr2 = kvzalloc(sizeof(*parse_attr), GFP_KERNEL); + if (!attr2 || !parse_attr2) { + err = -ENOMEM; + goto err_free; + } + attr2->parse_attr = parse_attr2; + + handle = mlx5e_tc_post_act_add(post_act, attr2); + if (IS_ERR(handle)) { + err = PTR_ERR(handle); + goto err_free; + } + + esw_attr = attr->esw_attr; + esw_attr2 = attr2->esw_attr; + esw_attr2->in_rep = esw_attr->in_rep; + + parse_attr = attr->parse_attr; + parse_attr2->filter_dev = parse_attr->filter_dev; + + for (i = split_count, j = 0; i < esw_attr->out_count; i++, j++) + esw_attr2->dests[j] = esw_attr->dests[i]; + + esw_attr2->out_count = j; + attr2->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; + + err = mlx5e_tc_post_act_offload(post_act, handle); + if (err) + goto err_post_act_offload; + + err = mlx5e_tc_post_act_set_handle(flow->priv->mdev, handle, + &parse_attr->mod_hdr_acts); + if (err) + goto err_post_act_set_handle; + + esw_attr->out_count = split_count; + attr->extra_split_ft = mlx5e_tc_post_act_get_ft(post_act); + flow->extra_split_attr = attr2; + + attr2->post_act_handle = handle; + + return 0; + +err_post_act_set_handle: + mlx5e_tc_post_act_unoffload(post_act, handle); +err_post_act_offload: + mlx5e_tc_post_act_del(post_act, handle); +err_free: + kvfree(parse_attr2); + kfree(attr2); + return err; +} + static int post_process_attr(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr, struct netlink_ext_ack *extack) { + int extra_split; bool vf_tun; int err = 0; @@ -1757,6 +1848,13 @@ post_process_attr(struct mlx5e_tc_flow *flow, goto err_out; } + extra_split = extra_split_attr_dests_needed(flow, attr); + if (extra_split > 0) { + err = extra_split_attr_dests(flow, attr, extra_split); + if (err) + goto err_out; + } + if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) { err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr); if (err) @@ -1971,6 +2069,11 @@ static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv, mlx5e_tc_act_stats_del_flow(get_act_stats_handle(priv), flow); free_flow_post_acts(flow); + if (flow->extra_split_attr) { + mlx5_free_flow_attr_actions(flow, flow->extra_split_attr); + kvfree(flow->extra_split_attr->parse_attr); + kfree(flow->extra_split_attr); + } mlx5_free_flow_attr_actions(flow, attr); kvfree(attr->esw_attr->rx_tun_attr); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h index b982e648ea48..e1b8cb78369f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h @@ -86,6 +86,7 @@ struct mlx5_flow_attr { u32 dest_chain; struct mlx5_flow_table *ft; struct mlx5_flow_table *dest_ft; + struct mlx5_flow_table *extra_split_ft; u8 inner_match_level; u8 outer_match_level; u8 tun_ip_version; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 768199d2255a..f24f91d213f2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -613,6 +613,13 @@ esw_setup_dests(struct mlx5_flow_destination *dest, } } + if (attr->extra_split_ft) { + flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; + dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; + dest[*i].ft = attr->extra_split_ft; + (*i)++; + } + out: return err; } From patchwork Tue Aug 6 12:57:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754910 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2055.outbound.protection.outlook.com [40.107.94.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9DB51BE875 for ; Tue, 6 Aug 2024 13:50:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.55 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952234; cv=fail; b=d//BckQZiv2q9eG2If0K2FPxmd6X357yKBLsc9Li+ubDDQGBN/9njOHhVqCDcp3OMLA/ZzS8SPkt86CML36cac4rBXfRaBLa0BMndAMxYr9UgAvlVi4egXG0FSgb0C8Q8SS+Mce+KxCJYuJQg7yoMNjbTe27vhvnsBWeGs4UAB8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952234; c=relaxed/simple; bh=damO4B68FeDBBgvNcV6B59CjpW5vBS7D/m+DIiSv7Gc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JSqE9xtDkZEo21DQ33o4YqNtlZiJBtvelJtM7p1WiCRNeR9dmK1M6MkYIz1Dj4TfitRKrwRzREpFZBXBfr5PhDIsiy3uzJ3KD3phClH0xQesBL0J/Xad2vpKqn4L5aYIceRg5+KeZX/3Sxw7fCvPIVuUziEh8qi5tpR/Q0u7Mtk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=j33B+fju; arc=fail smtp.client-ip=40.107.94.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="j33B+fju" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=r5wrn16VPFi8oNQNK0fBmLlLiMcvbxn5H5LBkVAeOV0RSPbItwA+JdJzmll+ZaGEjs7Zw+DfV0UeTEdJx0PPIDTnomwqWLuP09J1e1024rQ+aCePKjWUm4B4KJ8OAjnOOg0DmiRccLmpB4io5+kKmGj1pXfrEp11soeTsJjmbJfzEPqNYIS8jBTNavcS1HSgO6i99mhnuVS6G6KtM5uoOJdgjHR6J+5p/y2s11LlzrbrvTWK1df/VJMhsuksx0tT4onCY6XfMYH3/0xvUiw36IJLa42+VwklPjYHxaHiPZGGmotRj63EVJZLEsl9d+/nw9ItYYu0AQA7p4i9fNKSkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vSOqis10XSa2hlFQiWocg5SmOiC1mkHyTaiKGHbxKFw=; b=SJajkULcOQM5new+JTB639OUuPKx50QiHYEuwnV/qXaublPGNRWrFYj13S/nJwHV2Jbi89uXG9/ouLwgXCEwpxjYfYfYg5gsilFpeYq+U4omVVc6DZhWbMOJgtKT0KnaFH9usmg2GcQ22r1xpCQjqBx8WwYXIPKnsqjxcWSSuWraaasinN6A8T96BOCFvFdpENougJXh37bWg/2CXhB/Dx89kuKYfTIIuGwKTWI8T4QsRxmeWdnObk0UKbToi0PD2iI9N0S9t/+HTjXj60ClWPAQTQROBUVnS90Hx7sNqM3ruT9XZ8vqBBZjBO93hUMbdwcEJ33T4izPQA/yPXGsoQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vSOqis10XSa2hlFQiWocg5SmOiC1mkHyTaiKGHbxKFw=; b=j33B+fjuhSh3ukDViq3Gf5XjA0g7DOAvN4eNqoBXc/cNI6QrASg54FPQFqGOVEwGs3hTpHxZscAbONmD8UUbETPWR0fayzN4vpaidxN1fO7G7R+oRAk3cllWnhoRNRtfvyP+vVJ0i1bmC3j4diST7hxwZhyKvHgBPUXJ2s35CBQsGjrWZjljmEWeiwrCF3JTDzcJ59EIQ4RiV6VleSsrJlroULh0Rhzt6ITgfQG7MSsAhNFeKq8ohoHBkCP2GTTJZH1RCB1APWpKJfdPklukRDmaCjiB2SouXnvEJbtvgXnLBpUd4WHu4ijHeATF3MUYHfYRH3vgO89rDXLp+e6BSQ== Received: from CH0PR03CA0438.namprd03.prod.outlook.com (2603:10b6:610:10e::14) by DS0PR12MB6488.namprd12.prod.outlook.com (2603:10b6:8:c3::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.26; Tue, 6 Aug 2024 13:50:28 +0000 Received: from CH2PEPF0000009D.namprd02.prod.outlook.com (2603:10b6:610:10e:cafe::6f) by CH0PR03CA0438.outlook.office365.com (2603:10b6:610:10e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.28 via Frontend Transport; Tue, 6 Aug 2024 13:50:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH2PEPF0000009D.mail.protection.outlook.com (10.167.244.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Tue, 6 Aug 2024 13:50:28 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:49 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:49 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 05:59:46 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Jianbo Liu , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 04/11] net/mlx5e: TC, Offload rewrite and mirror to both internal and external dests Date: Tue, 6 Aug 2024 15:57:57 +0300 Message-ID: <20240806125804.2048753-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009D:EE_|DS0PR12MB6488:EE_ X-MS-Office365-Filtering-Correlation-Id: bfce4146-e70e-4500-3392-08dcb61ebb44 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: RV/jnw7YxBDuq560ddCteIzNeUTkEnQvBba+DSValMZho1YUooo7TzYAylpJWckcQEqLk+IQXW5N4hFNMSPcpdTlp/lQDAFZf4/FLyda5jlj5/yihmTVoVDE/OWwf2JoEhlSuckRMEs/qB0xeMtOl48IfGZw7hoeAJ5L5AKoXSLunV/yWDdKdxzNZK3AFzSTMTZO1lqvQP0s2oifYB4eDOJorTZCZe5glIqwH2+YqLLMrY9j42Z7q6oXJuKZt74VPMFUvWJqbJQ8mHRCfaEC7Xaq7n/qYyZWVYoEh5+e41E0lXCyLDERha0DyPTBXk//Ha4vZ1LgKt6lKHSGmcNY2j+pLyLtJJIa1O+puTRF43dbOba6GmB2odfo/ffQrEGsshmYnk/amqvhH/rbYI6fs40BsTsd9DqnoYDcOITKjB32rTETjzXN0N9d/hHbIqf5HeGxrYmcIsDrv5Mlwu9613EFkuaJsCML3DT2F6JJ0vdzjuHQlsSb0yJ+lFhzoGba5xyKj5r5jyrL9hXRLWwgZOsfsMAAywl+ifE3SCWhZtAlw2p4gJeef4XzYkDNt7ggKX3BOAls7AZnzp50D305ddJYo5qLYx4Tqm5o3+QneS+93w56ghANoxa+bL4ohAJbrngfBmyqS4krMNSbVTrfvm7Tk4ZAGC0wlHCN/gH5hc0pPBpbvYgJdHjU7QKjuL23DsZqeaRHbzFVkn7MMgB6YV9cbehOuGQdcLPeJ3hP7D5j5l95znIOiRl9f1Q13Whm1CgwnABb3ybXbGYyH3cBM1JMAf+lszHr9T0XW+yXpBwSidKa6mc+lUuLzz+9eQdbfJDmdJuLZWAYR6pJYaJZ6BirSXrZXStqXAY70XMxtd9fJgYf4CjKUcRZfmbwdRRdrB412vkB3CirOy05AS+GHENNnbzLlVlQ8mJjpvOVCGvc62maSr1cKn74iMM6K1f+y7uVAzJ98J9u6sRoKCRgAdIHWs7eJ9pQXEISDcLlF8gJDRGNLn0oE7ZAmKYuiyNOzxnsqRr1zZcP4aRgXKwTFRlxDWfYpkIZH4+z18LL4TrZHZXYgFg2UZFFj9rM4CLcy5gH4AUjGaBANSpQBiQIwJ+65h99ST5NUqEBq3tP/0ViihxjFhGRwbRRo1S4J3P+hi/NLXcXvJ6+N5KuZ3NKecZAQNojmMmINC8psSMn+lAPAEqCzdIa5JL4eZpaHkZeprcXV+cP1UJsieFPVl158imVl2oR6fySJHjUb2s9D4GXPlhw/q9Q1OunX7GnPd7JIIAUrEgCN338x9p6hKkU10GkBZVJ2fM5YSsNCVOaC7qs9/iRRkI//oWtm45nC3ElEgMJ202xilJ5dris2dOTocqqm0C6kT/6WE/oXFpe6KNYutaU2ui9aJsXejgWlZp9UAKNKvYtqMpPJH5+l4HULwx7R70Sj470zKsxzAcqoHlXIGe68WerLsIKwjIj4RgT X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:50:28.5444 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bfce4146-e70e-4500-3392-08dcb61ebb44 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6488 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu Firmware has the limitation that it cannot offload a rule with rewrite and mirror to internal and external destinations simultaneously. This patch adds a workaround to this issue. Here the destination array is split again, just like what's done in previous commit, but after the action indexed by split_count - 1. An extra rule is added for the leftover destinations. Such rule can be offloaded, even there are destinations to both internal and external destinations, because the header rewrite is left in the original FTE. Signed-off-by: Jianbo Liu Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c index a28bf05d98f1..6b3b1afe8312 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -1742,12 +1742,17 @@ has_encap_dests(struct mlx5_flow_attr *attr) static int extra_split_attr_dests_needed(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr) { + bool int_dest = false, ext_dest = false; struct mlx5_esw_flow_attr *esw_attr; + int i; if (flow->attr != attr || !list_is_first(&attr->list, &flow->attrs)) return 0; + if (flow_flag_test(flow, SLOW)) + return 0; + esw_attr = attr->esw_attr; if (!esw_attr->split_count || esw_attr->split_count == esw_attr->out_count - 1) @@ -1758,6 +1763,18 @@ extra_split_attr_dests_needed(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)) return esw_attr->split_count + 1; + for (i = esw_attr->split_count; i < esw_attr->out_count; i++) { + /* external dest with encap is considered as internal by firmware */ + if (esw_attr->dests[i].vport == MLX5_VPORT_UPLINK && + !(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) + ext_dest = true; + else + int_dest = true; + + if (ext_dest && int_dest) + return esw_attr->split_count; + } + return 0; } From patchwork Tue Aug 6 12:57:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754911 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2054.outbound.protection.outlook.com [40.107.92.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E32B91E7A5F for ; Tue, 6 Aug 2024 13:50:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.54 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952234; cv=fail; b=oRLwy9I6czKygCpsysb+vbS59/lKZ7faCreGUEdYh9BXZ+y5FxTGmcdcbi9o66h3B9tOUsIoh7i2x0suhbZ3Lu25zPJklA03b+DNgnrz3xRfOcPYFQ00HMGz4bz8Cdap+QqP5fMitqPxJZS/FWtUhYFPvk4bbzoQ/+eRc9AA1Uw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952234; c=relaxed/simple; bh=iPWqiGATDiJrnc5jka4NQyTmbRxkEhEVJn6wj733bbQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HlXSgk2jlNJSb8AVRz4Mxphc2DtT7OMTy18hy+o9SISxy6EITCs9fG9XfNU27COg/zf8D91z7yNMECNOQUQMzce9L+EWjzLYb6FMIE4UZlrsu21sPnGQlH9/UfBViXWuzQ1ryAmDPcl1ClVaer3jFD2rqpImuRkGzXTmyV8oje0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=SuoI6EPr; arc=fail smtp.client-ip=40.107.92.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="SuoI6EPr" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Ch3IcQCIHdyHqDNGqLNf48fnWvDTEbgkH2SKQRoX9gu15PqJTQ1qNlzHLbKf7XIr80GvJH2wPRqc0fua5t33GLQDcIPSjdJU92TBqQgXTtLwBDGZsilaZ2CLxDslJq/cWtWdSKO/5i3VIZjkpBq006AQPbZ6obLw/nm30Hn2DI5rfWvAag5Hr6iz1aIkS1SOuoo8Yjl6c4XRezLzK6FcRHphq3Jcxkn/NyXEuTSE9EVsk/09Alo6COvTjWZRyEZUsGvfX2M9yFd9OnMWF3PweUAACWVvdUCnsLXmIq4iuemx1LZOzS7ti0XG0omb2fUVbe2jwb50Mj0jzqdnxENKaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QrB9R4qAMr79k1w7qBpIVigR5lEYuJU82VeMTLLKn58=; b=JnWd1QMv2ZJ23YcK3m5Rf7vXFcVmClpzo1wel/zkq/ZfE0J74EUuRnRVqwGtyukl4DMiPEKhcpU9zkB/TNYOeiNBZSvuO6aBkq6NlmIQuDJu+G4wAKpCHiPMty0782KCzqGC1OmS2uo9FyTJYoHI3Dv6Brs25zBjaxnqX8/syzdhZlihgn/87g+mfPdF49TLHy0tuqgCMMZNq8xBR3bGeYAKTpMemOxVQz7Cfnnnq9z0nTahmCsSoc9tkKEvXa1zHuagxpATgg0RjmwrhLleC5Psfe9/3F/IeoElFf2BwcgxINDghMDEirBe+XmMDMjV1f0cFzgX8itjqb8ZlDn88Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QrB9R4qAMr79k1w7qBpIVigR5lEYuJU82VeMTLLKn58=; b=SuoI6EPrdJ+4eaBDNmR2OJvet+XaLG/IzCnkgX7HcIb/oZ+Qd1iN98YIygV5ZtVD2FwSLJgyIRm9DtO6YREyTL1pphOshKQzcjlIgxMwykT4CDfTBmK67frzxEj5PcPzOpHo8KIN0QLXNqiHTzMaB+jwzOd9eKk03THfV1lnSnWhMm5jZIKhgYJ0VbMcB/WAMVgQd3IA6Eyrmnii8p3gb4ARgxLLZgZOcIuNYeJZhZWC6LwoK6DXDShrRmN8I3fz1OOWK/U4unWBfzYgxZd0agdAc/pOQHSPB1HNHd/OnWgDjnq39gFIwyG2fVm+vj9sHfNGRy3onUCIY/mcPHopnA== Received: from CH2PR07CA0028.namprd07.prod.outlook.com (2603:10b6:610:20::41) by SN7PR12MB6792.namprd12.prod.outlook.com (2603:10b6:806:267::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.23; Tue, 6 Aug 2024 13:50:29 +0000 Received: from CH2PEPF000000A0.namprd02.prod.outlook.com (2603:10b6:610:20:cafe::e1) by CH2PR07CA0028.outlook.office365.com (2603:10b6:610:20::41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.28 via Frontend Transport; Tue, 6 Aug 2024 13:50:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH2PEPF000000A0.mail.protection.outlook.com (10.167.244.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Tue, 6 Aug 2024 13:50:28 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:52 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:52 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 05:59:49 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Carolina Jubran , Tariq Toukan Subject: [PATCH net-next 05/11] net/mlx5e: Be consistent with bitmap handling of link modes Date: Tue, 6 Aug 2024 15:57:58 +0300 Message-ID: <20240806125804.2048753-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF000000A0:EE_|SN7PR12MB6792:EE_ X-MS-Office365-Filtering-Correlation-Id: 64c120a9-24da-4441-b661-08dcb61ebb2b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: RMdNVcQWRrInZbrm5ia/DPzy8yEiRMmdF1BmDCwLMd0JgMwwmAwdhLUV/uCjtFicQgilToQNzNIPnSIMTscRoDXqsE5l9a6favN/3l2Fsoh3nOIcjfARXuYi1tCNSGRD/3Nhr5KKMiY3Z4aZ+70WQ2MLRplTF4umX9W+q9AOvCeCLuh/uv8gf33gtl0nm4sBhd+5W6u18GfXy/0BgGA3DA4P3C2EV4RrSjMq9h8bIRa/LsuhotYrhYbaEKiVavJivGIAKP+4gCrB3N+yns+ReEJI1CrOAzrVuwhxDxE8iyDZCdLVdzQKoQYoJ1M7hoGJHbNkRWwwHaXopKHTXFyOZvpIFIpH2FQpcQRblYMWbe3wnhEqRTwafQPnu0HfOtFL7R7Yafgw4qRboGJvlMp3vsko03BYFB2gYYCyN4fe6u7yIYveSBW/8g2r8I3bt9qhZdwPkKjT162QZkKcUltMmYJf8V37xvAuBXFANK2lEXCXIXmcvx4UUz3xJmYS0Dz4RMe0tcWOAx63wIPV2kkJloyIROqVjyQUuMvTEiYpKmr5B0yh2IO3U3++ZTUpKq8X0I8dBsfB1i/Is25BNxdtrxaVKiQSSEFPLOkSrfxU9FkDEZglLZFynBKjb6b0lD5BRcp4rPeXXSSNq6ghwX+Ewo9CiWdtxzqKZCZp2/4U8Vcrak4TYGzxAJVXkvRBJFeqvMT7PQUCP+wS9yZieIdcFrqIBYslL99EtO8HnXBq+ST3ZyMfNrPJde2I3NCK3NBp7dKCwByS6WNcbKbyfYsEwD7VCSSEa68PHT9kxFeG4BzyphDmpnS4JaRRDEWiFkcQwt0bs3Z78z+xXjl30nni/4zgJ/t+XeQp4++NswixyYcpbqOIQfbfmV+igLXJhdDNzynRjHvxPf6vm4iETHf7Y1oClToNsIoCF8/lgFsYHS41bR7AgmhL23+vpBPcxlMNW5ZQ2vhBHXUOWhl3k35XbGnImC8U1OyAD+8hNlQ5oV0lGagb/HofEzAxCODqIqrJ27qoB0hT0FEd5x6Cy2mM3a0avWvQn69dJ9Sq/cjVOlw1XDy0oIrLg24jdqjyh2IVg/kStjRtwovXJ52Is2GIpAvQmifmZT9LE5FKn4rFX7uu/VFzmZeHszBHhr0TvtW8BzAW9U6Db1M2W5/wnLL5MUtiWB4c8i5iuuGzSLzAPirsahoDnw7AjAZ5Nax9BfURV+0dY4rU4RiaZDDiEB/WA7MKrf64vguSmt05maI1G9lWvbmzh8iULlxVmkla1LzOUrgVd77GL17zrGk9JaYaFz7JLUuWHWrlcHSiqWjVev1HvUpPBJswc8PvoQaFqDyHFv00//yPaT8Wv59G1MlnIT5CrBspWraKENCYHb1RHgcOQp9D7MznU26SbmcX9Ac09phE7MheDWnRtTHA2lMDXCPSWWKLSAxCr8oINU9joNpvarGd8TkH1UOqlflGBsyD X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:50:28.3371 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64c120a9-24da-4441-b661-08dcb61ebb2b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF000000A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6792 X-Patchwork-Delegate: kuba@kernel.org From: Gal Pressman Use the bitmap operations when accessing the advertised/supported link modes and remove places that access them as arrays of unsigned longs (underlying implementation of the bitmap), this makes the code much more readable and clear. Signed-off-by: Gal Pressman Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 23 +++++++++---------- 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 36845872ae94..5fd81253d6b9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -83,17 +83,15 @@ struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER]; ({ \ struct ptys2ethtool_config *cfg; \ const unsigned int modes[] = { __VA_ARGS__ }; \ - unsigned int i, bit, idx; \ + unsigned int i; \ cfg = &ptys2##table##_ethtool_table[reg_]; \ bitmap_zero(cfg->supported, \ __ETHTOOL_LINK_MODE_MASK_NBITS); \ bitmap_zero(cfg->advertised, \ __ETHTOOL_LINK_MODE_MASK_NBITS); \ for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ - bit = modes[i] % 64; \ - idx = modes[i] / 64; \ - __set_bit(bit, &cfg->supported[idx]); \ - __set_bit(bit, &cfg->advertised[idx]); \ + bitmap_set(cfg->supported, modes[i], 1); \ + bitmap_set(cfg->advertised, modes[i], 1); \ } \ }) @@ -1299,7 +1297,8 @@ static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes) u32 i, ptys_modes = 0; for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { - if (*ptys2legacy_ethtool_table[i].advertised == 0) + if (bitmap_empty(ptys2legacy_ethtool_table[i].advertised, + __ETHTOOL_LINK_MODE_MASK_NBITS)) continue; if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised, link_modes, @@ -1313,18 +1312,18 @@ static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes) static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes) { u32 i, ptys_modes = 0; - unsigned long modes[2]; + __ETHTOOL_DECLARE_LINK_MODE_MASK(modes); for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) { - if (ptys2ext_ethtool_table[i].advertised[0] == 0 && - ptys2ext_ethtool_table[i].advertised[1] == 0) + if (bitmap_empty(ptys2ext_ethtool_table[i].advertised, + __ETHTOOL_LINK_MODE_MASK_NBITS)) continue; - memset(modes, 0, sizeof(modes)); + bitmap_zero(modes, __ETHTOOL_LINK_MODE_MASK_NBITS); bitmap_and(modes, ptys2ext_ethtool_table[i].advertised, link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS); - if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] && - modes[1] == ptys2ext_ethtool_table[i].advertised[1]) + if (bitmap_equal(modes, ptys2ext_ethtool_table[i].advertised, + __ETHTOOL_LINK_MODE_MASK_NBITS)) ptys_modes |= MLX5E_PROT_MASK(i); } return ptys_modes; From patchwork Tue Aug 6 12:57:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754912 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2081.outbound.protection.outlook.com [40.107.96.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B8431D2F40 for ; Tue, 6 Aug 2024 13:50:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.96.81 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952237; cv=fail; b=OHToW2dYxCZUOKpXm57Rmcd3g2Huz6aUoQVjMUsXoeVEnct1X6g78iS77vxiMvOz//DkxNX+/6sin5Yc1KW5esgnW7BBUfaQYBP1VvfNTlVL0GyU3hbx8+mvGr3mFSvS+COkEErdQVxeBtYuHzAGa0teSPpzusOVAD94I+5lRsY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952237; c=relaxed/simple; bh=c9h+6FJEscB/ML3LkFBXmMfhOP8kKISlhzFp0B3HRxg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ij+wkHGxWyHAkOHBfR0OBjV3WA92xWYXFDc68UZXNZX9dvCAmPzYm+e3msVB3lzeynlE9ZqFnaL0Dy8ej8W/GP+Ir5wou2wz7s0/WUL00VyIjAiWYrDJGQi/hUuDBKJeLUo+jh38HepgXgkznzlnE7ZBMl6UrrT3ASx/1S40Jjg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=p8hY7q0z; arc=fail smtp.client-ip=40.107.96.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="p8hY7q0z" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Nakbutrax0Q3WOtzTfyUa8iQrHxwsSwQBHu0of/0sWgNMm2/oRaudke7ZoWbnxuHogGly0joGLv6TudToT4+kZkQtCQLotj6gSDFbjoWKGBjzducPHAmfi6lV3W58S76NwcMv+CNzgu5dpWwaAmAt1mTaH82S8JuDsUk11zUiI6ik+obKyJ4MTZn6hRj/ZDjZnLv7lHsQkOCJO22PRH4TArdPgQ+e+r/sKQbWed7dAvgI+w2ClVF0bO/mk664A6LYmqTLhfNz2020HlNkoL0NrfjeJ1fM3rrFnDpicvtwnGbaiNiw4QtR9hAmWRvEmntKO4Ryu3GuOYwd1qc4a8zJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=kc+NfKbempEhirBrw72S6u2UdPoCV/ENErobmU0Ri88=; b=FG5ubfw+eg0WocDCDoHJYP3DgNwogZ7g1MMkxCqmV2dZ5aKgtImK96qS0WpRh4g7eiVlXuae59c5ZJnaJjIurj9EFvlkb4Ytu4iyc/sA9ySFkKm+SnDSRkNjX6MEtXah+xMNHk3gBL6uTFmOq6XRm0gc71oaMYLhaIulC3QfrAinF1a2aXGWgWnzyOXGkEFNadmiYGeLiC7IYbXbFUv63Sr6+YJxAvvyCPKEgC/XbTvROjHeexHlCy00HgQhawVQC6lgBgcGajdypnnYJEJem3Un/LY/N7gF40cUZVJzSJpmQzBc/tgAl6FplKFI9NcSDZZGSXRB8ZrRlVYbT8gSgg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kc+NfKbempEhirBrw72S6u2UdPoCV/ENErobmU0Ri88=; b=p8hY7q0zg157QCVertYZlKMT6if7ELO4EbOKuzMul0E/HHIAy7cSPDxipEvLrmW7GagYNRqJ6ddCcBDF6Qf0i6dGaZu2/fp6WGQVQn54662Npo+ka6/3uVL0/S4aZyMXNlzJq0WJxuJ4IUW0x6wNgqnKj8XYYoAvZW2YU/hH9qp9KqTBbMpRgwTKsDa7LQyWAMBWw3rURYNs1LV20GUnpkFJymgLFSkHnAAyioptKK2ou/yoPmrOxQxvThnPsZigSikWiTThV0VPvtVsd20z8fXs8FqpyA2iSrDeQitaoAku35kxJmJSIwyY5syDSQnbiGD+n/B2UaImiDDkGX79Rw== Received: from CH0PR03CA0254.namprd03.prod.outlook.com (2603:10b6:610:e5::19) by CY8PR12MB8316.namprd12.prod.outlook.com (2603:10b6:930:7a::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.26; Tue, 6 Aug 2024 13:50:29 +0000 Received: from CH2PEPF0000009E.namprd02.prod.outlook.com (2603:10b6:610:e5:cafe::92) by CH0PR03CA0254.outlook.office365.com (2603:10b6:610:e5::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.28 via Frontend Transport; Tue, 6 Aug 2024 13:50:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH2PEPF0000009E.mail.protection.outlook.com (10.167.244.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Tue, 6 Aug 2024 13:50:28 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:56 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:55 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 05:59:52 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 06/11] net/mlx5e: Use extack in set ringparams callback Date: Tue, 6 Aug 2024 15:57:59 +0300 Message-ID: <20240806125804.2048753-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009E:EE_|CY8PR12MB8316:EE_ X-MS-Office365-Filtering-Correlation-Id: 87eb0e38-ce81-4a7c-8997-08dcb61ebb46 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: hOVbdAAC7R0G8AqnVklK+8iIlUCGKWLxhPq6nAaBj0MNcq6dBTiaGZRiFN76j7ksp2o4HqlEr1HF98l4AMF4k0P3qyPVGDxPPjIcsIMh95LDefP+9JMk7GkYVqyCZyofu/0b9Z3JLe0vJs3NikswUgsW66BlmT6vyuybt4J55Rx/a4TW0osa1jy5mwlSWGCmCXKzrbKXuO5S4KBIUIo34VgPnaSifSDaY5HHg30zX+H1L+eRgL9Z6YwfnG69/hNtZt4If3xsqSpROyfz/L+PtdgvDoq7k4aLO/1aHt+HFyy1FZtZbCxL3ZtidwdWK0cdVjY6pxtDuKO2miuaImyRzrMKlT5Rkl61B2AiB+jtmJdsAwsFhH7Bc6A0+pwKSXvcuxLxdLkSZ17uMwhZfuOTOSJa1NYDfnh6Ucj6Tto1/4o90Z1mvI57/D+qrlys6Eurd55TYbTax38/S+jxKFdBXg4lnklCENEd1GixDh1sYLWZAMsPXWoh2PNL5DSzQS/My7n4ux/peCrQdwejsNwtG+Rer44WCVqRgXED82yXCsSor7BPo9zZPtG3FCiembuLbvKaCz33w7aeD/mgsANOrMfiyx2jeWd+QnZ4LBaBqRiStCenwr7+gFXldZ/jk8rPqySzhd66Lnwe/E4W01j0AIcK9+aqDGU8Q9A7JLVEnWf7Qe17v6NBEq8nXx/8aRTnah6Ui8kzf2lI/Cibs/tyTP3fQMPbSqHxr13P1OEarpGrcqnJmQX7h7gLqIXMcwvQkGbXs5E28/m8zzUgSUR7ME0DHAzzlzPpKURtH4Mg8s0uLZibHelEAw2MRSvdsbgqplV/0vpO78ybskDzysi0s/qDpNspP0zEOOssaaVZKgwntbVOnZGbx4RHGAUEP50UfF4wH5bs8pDCUptnkSYzGOXWXd3wky+F96HyGvNWjt7MhzdoQRVUH0wQa+fsReVh6li4TPvg1C4ov8/dCvlhR1YhcCZRIj6KAtjWcePYGzEEEWQduNmmHozfjWJhbQ751ztgFqj7Z21f/yMLRNIPs3mOCZfYz98KlocCUu/J6ZeigalR+YeQYx6MCOrxcEpcMbNSH8RjXZjf5vqJ5ZrUoEwkcVfadZl/tzgcTSnH7KUmTovcf5fzgjRhTN1blUi7ZDsUVMrGb/O6J36Nz3RojJJYGdJYKM27cLk+NSj00ysa9xkG/uq15VjLxPH57uscD+CMwU4otWjv444T2UptQSsy3mXXnzJ21J76+EREJ5Zy/jMGd6wo2qoDPFYdQimK7GiIYT8f7FHGeNMHCIgGvBJwIqQ4xTbY+CuraRZmkaueVH/9so1fjr2w/cAcqfMcw58+5aiWySMKrl5bU6QsEezSFpU4D/fErKQn83ymYK9kzMAwOUYeQ/Jq+NBcsJLpj3KDfnqC3B9f0LkCtZbaxfHJPsnC7ivuNpAmOhJb0DyVe+i8sfFj2B+dQXrLWtRJ X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:50:28.5597 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87eb0e38-ce81-4a7c-8997-08dcb61ebb46 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8316 X-Patchwork-Delegate: kuba@kernel.org From: Gal Pressman In case of errors in set ringparams, reflect it through extack instead of a dmesg print. While at it, make the messages more human friendly. Signed-off-by: Gal Pressman Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 3 ++- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 23 +++++++++---------- .../net/ethernet/mellanox/mlx5/core/en_rep.c | 2 +- .../mellanox/mlx5/core/ipoib/ethtool.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index 5fd82c67b6ab..01781b70434c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -1172,7 +1172,8 @@ void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, struct ethtool_ringparam *param, struct kernel_ethtool_ringparam *kernel_param); int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, - struct ethtool_ringparam *param); + struct ethtool_ringparam *param, + struct netlink_ext_ack *extack); void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, struct ethtool_channels *ch); int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 5fd81253d6b9..f162fd0355ed 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -352,7 +352,8 @@ static void mlx5e_get_ringparam(struct net_device *dev, } int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, - struct ethtool_ringparam *param) + struct ethtool_ringparam *param, + struct netlink_ext_ack *extack) { struct mlx5e_params new_params; u8 log_rq_size; @@ -360,27 +361,25 @@ int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, int err = 0; if (param->rx_jumbo_pending) { - netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n", - __func__); + NL_SET_ERR_MSG_MOD(extack, "rx-jumbo not supported"); return -EINVAL; } if (param->rx_mini_pending) { - netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n", - __func__); + NL_SET_ERR_MSG_MOD(extack, "rx-mini not supported"); return -EINVAL; } if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) { - netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n", - __func__, param->rx_pending, - 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE); + NL_SET_ERR_MSG_FMT_MOD(extack, "rx (%d) < min (%d)", + param->rx_pending, + 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE); return -EINVAL; } if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) { - netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n", - __func__, param->tx_pending, - 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE); + NL_SET_ERR_MSG_FMT_MOD(extack, "tx (%d) < min (%d)", + param->tx_pending, + 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE); return -EINVAL; } @@ -416,7 +415,7 @@ static int mlx5e_set_ringparam(struct net_device *dev, { struct mlx5e_priv *priv = netdev_priv(dev); - return mlx5e_ethtool_set_ringparam(priv, param); + return mlx5e_ethtool_set_ringparam(priv, param, extack); } void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c index 8790d57dc6db..916ba0db29f2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c @@ -360,7 +360,7 @@ mlx5e_rep_set_ringparam(struct net_device *dev, { struct mlx5e_priv *priv = netdev_priv(dev); - return mlx5e_ethtool_set_ringparam(priv, param); + return mlx5e_ethtool_set_ringparam(priv, param, extack); } static void mlx5e_rep_get_channels(struct net_device *dev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c index 26f8a11b8906..424ff39db28d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c @@ -74,7 +74,7 @@ static int mlx5i_set_ringparam(struct net_device *dev, { struct mlx5e_priv *priv = mlx5i_epriv(dev); - return mlx5e_ethtool_set_ringparam(priv, param); + return mlx5e_ethtool_set_ringparam(priv, param, extack); } static void mlx5i_get_ringparam(struct net_device *dev, From patchwork Tue Aug 6 12:58:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754909 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2072.outbound.protection.outlook.com [40.107.212.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 986FC1C233C for ; Tue, 6 Aug 2024 13:50:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.212.72 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952234; cv=fail; b=Rq/lg+Y6oYAATOn1A5PSwnFV/4IgCCOV1jClBAc5xFPNQJokJkLdLZzhY4Xndwklwxo54QDV1pQEz3yJV22b40bK74qLoCn177NhAjI8/hnAj9LL48C8t7OYttO8zVkJnkyS6wTtscrpHNacIS0WL3hrEv5S2wy27g3BaOoW9rE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722952234; c=relaxed/simple; bh=r/SHGC+K4QTaoXmZb3/cMfNzPW2f+GQx7LoRaz3i5L0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bpK66FkH7LmxLV4HhGA2hNYkTqpVqiwoB1hUrYQPrqK/iiOmujNnxUaEe4S1KWuFtsREwIFlWpneQ2O5S8hKnDu6Ko4pCFPWi7abJ1952KsnqBTfgR5P+Qulb0MnTICdnjHZEXsnVR35kTubDJDjxDGvWBLagHNyKtwoSDUIBmw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Eoinzk1a; arc=fail smtp.client-ip=40.107.212.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Eoinzk1a" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ExzQ381W8uzWKv2fS6kUSSPDZXFL1yHAETep0NGujAFlnUn1tQb50Y6KG7Sy+N/n4nF+8gX/YZ6voghwqxKJ718t19QELv3qKviwkGP5L3ubE5+NG404Rm/tKw7nFp0tgOglDJ7grxaoqxiLWUa+rsC3rW16E2p82xRyvVvhxDapqq0aTB/MTbo47XuWa6GpYGVGLR2wRerr0oGRupN4DcEOorbCvROS1FOtRfbtbH+x4QeJvavn2VGuq//uqxhn2rn8ag4kjkSwo/4bjp+GCI3t46iSeMdbeY4kdaoZN+eiNMXWqsKt/LYoEHV5YabJjPL1GQbPlR7UmPOSj3hjqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9Vy1MHCe8ERl+RZ+V65tZkmAG/WaGvcZgx+6uGOTq2U=; b=DLsh2HsdgcHd7QYfBnjRpuMlbrKoDMO1lHNng6FMgrWZnoaU2ymJrNFRsL+oyPyaOOUL4vadQvEOsPavCpwd9/n1mKYWZkiY6whS0LxReNdBXAZvRAMCmtcMsKyn1XRSUOPwtaZAFJLOmR0deIxFeuDBIvCsI7Y6z9gwZOK7RLU/5cEMJZSlayLY5QnuyjSnGfTuSGu8ynH7x2XCE0VmELwcmNUw8Qjwew7ht9XAli13M11NArYM77JcxadK/X5FTIm8VxTRxS3x/eiu56qTYvOEe1gcj82wHQ2UW3UavO1O4nhGhIeQ4aUf5s3Sn4+KbxCe9cHSoEgDurXSxXjpjw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9Vy1MHCe8ERl+RZ+V65tZkmAG/WaGvcZgx+6uGOTq2U=; b=Eoinzk1azeCnsZe7T+JmL1oLbyXyuI9MzhfE8en1pWrGanqW3JJrhXJ9IfyG8dwoP5l/Nt4fj9rNplyN8lBjIoynv8ykyjy9adX1bqa9srKF0U38YUErvdVRZ756Gt4aGP4u4gc8BCIBzOnkolY2JarDrgiadh3DPbbCA8lQsMmpAA22wq+ovQdcTeRMg5kHzZmw04DIJmTHkbTKez/pezSgbeCllINgnNkDpReMCs8IZmzakvIKIWnzeXmCdZDSjjwEeAxHgu7Lq1irjtt1rlQZ+rr8piHcNTRol8oMFNybeFbvUH5wmky/CS3JKWBa6hjUR1y5UGbP95RZwU3B1Q== Received: from CH2PR18CA0054.namprd18.prod.outlook.com (2603:10b6:610:55::34) by DS0PR12MB9057.namprd12.prod.outlook.com (2603:10b6:8:c7::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.24; Tue, 6 Aug 2024 13:50:29 +0000 Received: from CH2PEPF0000009A.namprd02.prod.outlook.com (2603:10b6:610:55:cafe::76) by CH2PR18CA0054.outlook.office365.com (2603:10b6:610:55::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.13 via Frontend Transport; Tue, 6 Aug 2024 13:50:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH2PEPF0000009A.mail.protection.outlook.com (10.167.244.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Tue, 6 Aug 2024 13:50:28 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:59 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 05:59:58 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 05:59:56 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 07/11] net/mlx5e: Use extack in get coalesce callback Date: Tue, 6 Aug 2024 15:58:00 +0300 Message-ID: <20240806125804.2048753-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009A:EE_|DS0PR12MB9057:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c6d85e1-6086-4d87-893b-08dcb61ebb6c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: isBpfHQwBsQDYWQv1tnCxkuw/3govSV20ecVB093NJ+kV+LeFRB/Sx0HOtQCAYRGbcV2Ypnv5cnvytwobYkiIsdiy9s6y2HQeYdffd72Kk9nEnqV3GcuEAF8uwC74d43BSkgkzgp/UTdB+2ohaofT1ac6g6UYNkWpodZDBgM3P2es+g2qXwa6BciQ6zz1dYtE0uFrsb2UfnkpjH0ZPKzH337NeEUTi6iVoqViGOhSqtQkA0j99HNyEM18zl0ZXSmeVCRu782pC2C5+5udsHtjkzyF5sALYGIAPYEdRyObdB4tbaQ/VIgPkKjrNfSi/dBWwYYJ1ZPgzDsQQhm7xY1hYs0RfGOr6q9ELK+QEooA1cXdFCVdBKSTP6Y3juo4LFGcMO29XwjPsxUufsn7WpZWjr/f4yb7q0oyGsq8IC29Stb1WyOEKmub9qp8BEl5U9rTr6ILuoMah2yeGDzlXGkIfUDufsjmuDVJxra7PglymRofeu17RiWyflQDUP3716e6IGxUln5Ml4+2d8YTG7iEpOVhgxKTSNX/GABGHfV+pUiceAE5JSZs0b0/GyET9c/9X42/H/h7GKmaXl2PVcxL9nxSV0O4H8Rps9/rTewG3zY+aNHxPHhoMwVIKshMWbAjO4/Bhv1SRuFU/INHE0+V5ggkNyEmYzApKitdukVFoUi4QdjB0oHEoIniHzsaK06QT89kHiwWl5YDpVZv04/NEwwA0tbXSpdnv4jUcUyWcPN/jGdSmFh43ZYzCzGqDvAjonAf8xUnAamv1i/l4qChwtOpVlnINXXWCLvwya1U7KmhXFU3SeWNRDYbCxrq+7vRSiKqULAExyD2yeTXHme0LRrH8E1hdnm/Go5+h3Bt3gLl5IB4hPwnueyyDMDQg9+BakaGxdyviEscynOT8u1BLq5oTNQM222mKQ1dSeHI5ZTxKgYpW8a35vVtgvrJmgyOmBsuqyTSaOvkZNVV+CbNwSoyqS71GWmJFQhgU47cPtadCiejt35GGKiiRmYYmKc2UfQriRqAasDY9N+Cq9Eg29/P6+TaS/xySxJ+OqkjJxKJL79Y+swRIaqJzojzaYzlyvMDWLNWreikKfYK3jPyysKcAReUl38AfkQbtLuMOwct4pX70ydgpvaIYg+XVV0VZkq5hX/S6X6WzV0Z1uOaQKJerkDFo/KMbNJkMZRl54WzaQ4tTix+ZnguHYv7qZfMcmkVJWZQe0qFEAK09GeXyiExkcskp8JN0PuRejPMDELqq3D8h6xM9t5HF73lhUAUBebi0f7KDiyX5dBQgLKTUzXga0mJOVUyA05QdZc9MCzI4xfRBShq+LcQUvRpzwmlmrSPb6bADKRbPngrpvKNY+NkTjh1NolSTVIyvlhdk8kH6U86CatAjpnogmOildEcv1q8dTQGXZJoPLlUkbnQmh7+UFrbz5C2HlXSUaXYPf1FPF5lNYAmXpRV2Uwfm6l X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:50:28.7931 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c6d85e1-6086-4d87-893b-08dcb61ebb6c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9057 X-Patchwork-Delegate: kuba@kernel.org From: Gal Pressman In case of errors in get coalesce, reflect it through extack instead of a dmesg print. Signed-off-by: Gal Pressman Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 3 ++- drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | 9 ++++++--- drivers/net/ethernet/mellanox/mlx5/core/en_rep.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c | 2 +- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index 01781b70434c..7832f6b6c8a8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -1180,7 +1180,8 @@ int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, struct ethtool_channels *ch); int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal, - struct kernel_ethtool_coalesce *kernel_coal); + struct kernel_ethtool_coalesce *kernel_coal, + struct netlink_ext_ack *extack); int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal, struct kernel_ethtool_coalesce *kernel_coal, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index f162fd0355ed..66fc1d12b5ee 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -554,12 +554,15 @@ static int mlx5e_set_channels(struct net_device *dev, int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal, - struct kernel_ethtool_coalesce *kernel_coal) + struct kernel_ethtool_coalesce *kernel_coal, + struct netlink_ext_ack *extack) { struct dim_cq_moder *rx_moder, *tx_moder; - if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) + if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) { + NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported"); return -EOPNOTSUPP; + } rx_moder = &priv->channels.params.rx_cq_moderation; coal->rx_coalesce_usecs = rx_moder->usec; @@ -583,7 +586,7 @@ static int mlx5e_get_coalesce(struct net_device *netdev, { struct mlx5e_priv *priv = netdev_priv(netdev); - return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal); + return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal, extack); } static int mlx5e_ethtool_get_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c index 916ba0db29f2..b885042eef14 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c @@ -386,7 +386,7 @@ static int mlx5e_rep_get_coalesce(struct net_device *netdev, { struct mlx5e_priv *priv = netdev_priv(netdev); - return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal); + return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal, extack); } static int mlx5e_rep_set_coalesce(struct net_device *netdev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c index 424ff39db28d..9772327d5124 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c @@ -132,7 +132,7 @@ static int mlx5i_get_coalesce(struct net_device *netdev, { struct mlx5e_priv *priv = mlx5i_epriv(netdev); - return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal); + return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal, extack); } static int mlx5i_get_ts_info(struct net_device *netdev, From patchwork Tue Aug 6 12:58:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754902 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2072.outbound.protection.outlook.com [40.107.244.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3FD71C4622 for ; Tue, 6 Aug 2024 13:39:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.72 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722951591; cv=fail; b=eHJ16wDq/+/OgSiEqCZ+odBygOivOaeT4coKVt72MPcQoJEjGtMDysIhjdacGM9v8XA/8ZlvEZuu9eDTsA6GQIu/RDCqMcCdsPZ9Pgz2ORLJCPVd9qPP7qV63gyLv9cEukfSukf+U5AyGrhWv7gzkZiI4HjOZHIIrT+Unqx/oC8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722951591; c=relaxed/simple; bh=z+q/98TlRTNP1zaPcRclkWOKlR/mc6owl8qieAY7mME=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JFNO3zOsIwsvprLlCpTRFxzrvOW9ktZTTmrAgZyz8Fy+NVDfMGtbSH2RgPXH7NRHnhf1yklmQ6CV/dgOikIT+sqXaGcsuc6dFXVuWctpBkDxOqmtpJZUFHvOtorJ1CiN5ssnr4qH+05RtC0STeQarQNOlwQtv55IMKbU0v6+eKM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=YXl0tbwG; arc=fail smtp.client-ip=40.107.244.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="YXl0tbwG" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=zVRocsovcE2c1IQEfBmo9YZKRMLOX4W85bppKoV8BcP8/l5Q58SlNEqhZUagGsRMpNBLyhnMTbJH24xS8F8Bu9qfos6IOUjWIH0nzHEM+LqDC7N4/3qQGSEAWnDceIHg7MHB/5nrS9FdNB1zLjL9bAcx4REGJIaLKzUZYK9bWrFB/IYtEfg+XPqelkhgdiS6FbA4nvLki1dmX57ZVZwYh3Djs/NX6tXUAs2pqe1LVi5FynG8kTTYHT62yPeoP4AZ/8sE5ykLK2bBRtC1ONZA2g76+PAZwd90pbJxTlxKHcKQamuVOPOK6MrIsu8/ZEO81tdaIYFmWUIUyDXOvk84NQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MOYddmxJGlCVQY3fZHuF9ufsO9BGC0FYHRXxsWXHv0g=; b=WUgZSQI1NTLrYbHfFj38uJbvL5lrhyv3ztwbam0xEOq7XT8SG94SG/qOGOG6rGNbDCnz92p1iCjeGiKORSH2jmueCY6mvGb+hQoUNAkrG9kPjJK1SX8UWF9Hao2cIwkdvsMzI9lh7BMsPWOlY/C0wc2GmSVytAJcFUcGuR7jqoUqstA3m7zp/+tGvOeBXV3Pqmd85oo2TVIcotlxs9RkTz8QRuYGKTikvu3QCwJku4/r9pFzTnuug4OWxX3wQmuYQB664ia1r9d/EwAwSXK7XT9MjiTCisn1TPJ5lzks730xGUs38AzIRUiRVUDctxGLwp38uBf+hjDU1Ag99tA4sQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MOYddmxJGlCVQY3fZHuF9ufsO9BGC0FYHRXxsWXHv0g=; b=YXl0tbwGaj513I4KfEFk8tN5iY43tqURbfYvhx38CnIsCaN2KvGhNzY40Mlfj3HF+VbGpvFCkhRM4CUgAmIepM3yw00ZJ1eYnCoo4nfC+8P2zkoZ8DCzypql/xgN4yRDskKdGjYGfNy4mrUk8s1T8p/i0AccPNdnna1bdN39508dN3LIRsSDjTby/yOLaKEHlaStflqD1sZ5v8ASLYs0yaWdip5/yDRzWXXzpEqL8wpixz6DDyicChAV3WUw3BlQvItt2NU2Jda7bqpJBqFsxTrNU6QzjnAdUDH+LksAPkgDE9CPqa51F6G+rlyAMft1R9DwkJY0wLrTTtXDrS2lkw== Received: from CY5PR15CA0209.namprd15.prod.outlook.com (2603:10b6:930:82::27) by PH7PR12MB7819.namprd12.prod.outlook.com (2603:10b6:510:27f::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.24; Tue, 6 Aug 2024 13:39:46 +0000 Received: from CY4PEPF0000EE39.namprd03.prod.outlook.com (2603:10b6:930:82:cafe::17) by CY5PR15CA0209.outlook.office365.com (2603:10b6:930:82::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.13 via Frontend Transport; Tue, 6 Aug 2024 13:39:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CY4PEPF0000EE39.mail.protection.outlook.com (10.167.242.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.19 via Frontend Transport; Tue, 6 Aug 2024 13:39:45 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 06:00:02 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 06:00:01 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 05:59:59 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 08/11] net/mlx5e: Use extack in set coalesce callback Date: Tue, 6 Aug 2024 15:58:01 +0300 Message-ID: <20240806125804.2048753-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE39:EE_|PH7PR12MB7819:EE_ X-MS-Office365-Filtering-Correlation-Id: 95c7fa7b-c317-4a37-72e4-08dcb61d3bec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: P6gPn+y8OECS+ePsXWRp6oz2lQutu4d4KFxj/IlFphCzStcRHW3/g7OPmt7DSQEQqoZM8312KllvGWHJF0/NYyYSQJR3txVgUUEVniJoe8UyxdLmOtr/zYGfRo3Q/wRJEQgMpG0NcXP6RtaXfvcolBSTgu7yhSiUf9vhyXJn2UETB/vjyoCOInl0oZud2e7r5GBlYthU0aZ6hVYvz1e62gVgjgQrKMIkXCYf384L09Qwt2VMEjpSfdLs6SBh5BfsBe2XK9B4MRYk/pnTXtHCoTESbWeKYo5wWZfRbbLmo/bwArrmOdOQsPpC8Y+tJe6CyjPRUr57or3f2nLlYVMhwpqxyMI1F2dSxkywoWUYffjC2YqHwx32TpCbtc7KtUc8tpAO7S6AolrOwSEwNgaAS75wd598nP1lngeo8vTvkwgjUaQoNVksF9ql1FHRjeiwXYmSy4lAPWA0VCklHLtQIkpupQ4Ha2/3cU6cUYH3Fro+NT3NRfwXkfD0vsU8bmZ0RwKUBbLqqFlg+sjdmrf/3D2S/rxIhlJbyWS77xzdVjmEFjctoIO2nDVy0zHpd3v4hYL3ZfRjC5cxFnaDKT7HWG5MHAjg+4DB4pnviz6lFzUjuy7P4t6l9uLaQZYWIdkuVqCYgvcCuoisTyT+giAbfqkxhSQX7sElz7QPxC0lyhVRX5YsepA6khWop70DyWPjwz7z/4SDu266YMS2H9N9lhW2+aDPrceORQCh2vuQhYaw7GACVA4BCyuPg1dfH/j8j/z882dDUVsyAejoTAekAksp6UVKfF3ReN6Q9+M/xj0dkwtxlpv0AxW44GvsmoHPl6iJMgYR0yhaVfkeZfoWpmXAa/KuWtJ1ct7j0DVAW36kdljxRwNlTOyP1aKX7aGhwHLQXdmzoq+Zrn23b98sxIC3EL1JkK6raar8swgHBndWsmIwXEmp7Vz23NMIrKK/hrapgFNaVRPEnOVk16LAEk163B465Z+f3WP+jceXoG3dqmUcJYQ0a3v6Rc7CjthbjS8+ug0SfNZQMLmYQExhbg38fPe6brY9A5OYbOQpb0MMZ4YXJocpynsM3Omc+krLOWswatm2OJrHNSN6GURGK/imOLGZ2OmEtcHQzb2Ee0aFBRLk1uei0TXqfQwv1bOeTGHrgKlBEnoQsQiCG6hol8bGo9QZdmD9EyLcXH/WBY3EmNVgEy0oilQVQeeZTfCI6iRAyAtxXbT+pXxXbrG1fJswJCGbjenFpcz1z9TbCRngq+HTfzpWL4sNqx9Wx8KvHrJsVxXiePAq9AWrMdjVE6JPeCNNvj1+cUSF4fjTAhSug6dseGz2/wNzKHimbEEv49IdM9d4zPIVsGbkdCzd6hJBqIbKQSkIKErNj7KvPCP4cMVdlrY+hKcqYRwdFEqwsTJRk2lzhnZW0Y+UCyhArvs18aSSvJsstSd4YxdXSjlRhJvz+TQ6FuiX2u810Neu X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:39:45.4488 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95c7fa7b-c317-4a37-72e4-08dcb61d3bec X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE39.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7819 X-Patchwork-Delegate: kuba@kernel.org From: Gal Pressman In case of errors in set coalesce, reflect it through extack instead of a dmesg print. While at it, make the messages more human friendly. Signed-off-by: Gal Pressman Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 20 +++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 66fc1d12b5ee..455d6ef15d07 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -708,26 +708,34 @@ int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, int err = 0; if (!MLX5_CAP_GEN(mdev, cq_moderation) || - !MLX5_CAP_GEN(mdev, cq_period_mode_modify)) + !MLX5_CAP_GEN(mdev, cq_period_mode_modify)) { + NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported"); return -EOPNOTSUPP; + } if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME || coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) { - netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n", - __func__, MLX5E_MAX_COAL_TIME); + NL_SET_ERR_MSG_FMT_MOD( + extack, + "Max coalesce time %lu usecs, tx-usecs (%u) rx-usecs (%u)", + MLX5E_MAX_COAL_TIME, coal->tx_coalesce_usecs, + coal->rx_coalesce_usecs); return -ERANGE; } if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES || coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) { - netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n", - __func__, MLX5E_MAX_COAL_FRAMES); + NL_SET_ERR_MSG_FMT_MOD( + extack, + "Max coalesce frames %lu, tx-frames (%u) rx-frames (%u)", + MLX5E_MAX_COAL_FRAMES, coal->tx_max_coalesced_frames, + coal->rx_max_coalesced_frames); return -ERANGE; } if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) { - NL_SET_ERR_MSG_MOD(extack, "cqe_mode_rx/tx is not supported on this device"); + NL_SET_ERR_MSG_MOD(extack, "cqe-mode-rx/tx is not supported on this device"); return -EOPNOTSUPP; } From patchwork Tue Aug 6 12:58:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754905 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2079.outbound.protection.outlook.com [40.107.101.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 182C51D47BA for ; Tue, 6 Aug 2024 13:39:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.101.79 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722951601; cv=fail; b=SM3cIWssY5FIrl1Ov9xzPb++nFGr7COK3SIr0njTdygvvjux7iurT77pHxf4OthTLW6AR9r7BNDDZi/ckWVTsrzpfiuK9c8LrsX149TgthWtK+qoGI0ZdiJboCUrGyXyRwPzU7NKkg5vufbEYNL9/mTtmASFhLT0F3DIPFopbyg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722951601; c=relaxed/simple; bh=3JvIEnEjs5cAcZKw4zLYA+BWxnwuIJd/JS3lpjBFBew=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=seOBVrpOdtwKRF+qs6nwDvA+9yXaD7LEP8j8RMMw9peUGCoprHs4C47D/JZAKB7/5fFi/7jhYyXI3n71Oe05vsJpbeuQqtnmnrNu8RK5gssgew9vS+3KwqW6sEGKbgxF/SyjY9HExfocUERyRr6vSw/uZz3ItxPYVxnq0oPbG08= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=mC+mozQi; arc=fail smtp.client-ip=40.107.101.79 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="mC+mozQi" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=NgIWJ1fSmGBKU6fBt/QxLJLjsCllNUHAvE0oVccdG7xyFU437C73p+ePpLNPpH0IYktKI5s6Sj1VieegKIQTg6hMkwDIpcirZYApdev6NqGsZnGkGg+Efv1WY3z6PhD6PbfUUrrXsTM9bWR7QJbEGlfXqHa4mNmxv6e62hPlH4LQ9l87Erck0QBUD/SdPAFfb6QnE0XT5psTWcqgymEVV7CZUiJHV41T73Gz62bB6NlG6JlXnFMwCP1ISsYuYCKZV3ihUA6NGzcZkBPsYnGaXZ8KNgEqkG5p3kesPmItKLpRerlD8wq9rmAU7fA5zM2/S7nzzCyJ2jatu6bxa12XFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YVWxM5t3OzYm1Y5nWo/HsbfatV6H131EU/oaxY8stFo=; b=ySETwBLiBBkKASclwzg/DFTciviasFMpCKFiI9QAvyvZf560742CjRLgJyiBXrfmgeYBhrC1y5xyHEWtjOrN2zw2AKPuPWsABva8mr3yBc6qvjhxOUxhKECUVG7an2PT7S9H81dmd78232fL3dxu0/V6ePDJbVyKa8Aq4JOrAuKEcue7kXQxX5XCiQckhii6OiJN9W813nG+auhpSnV8ggq5nQ78Hm0xqelrI65IxtKrUDIKGUqbEX+EdbVrXUWgGTxeCf+v1ULWk2r5nVALWQVKM7o+doR+Q46C8y7qT5ls1GzUWMuWZrVSnu6lCACtjZVvfK9d+JJAtrDweaNbKA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YVWxM5t3OzYm1Y5nWo/HsbfatV6H131EU/oaxY8stFo=; b=mC+mozQiB7V7/xdxxzRleJIITqx4QhVlEYgSPWOObfhsRDVf4Zon7Uuh64oUtNUf/BqzCxemP/t82OzZM5oQ1xcarX1HBAaiJZDaxetaN+voaFhyYdarR32dnV7/BIRDE5LgsdcqDkBMXstrGJEp8fVAFPANisw2z3aBhS4oqeIqy/Bow4H2M07ZwNg0KABq586GCo/+CE88CVHdWhOihy0aBqNGJLcFvQQpupTwtkz1eQMVr865O2+urHzlcPsoNi0ZnCCz1+pRBHiXlNum/JoPnMCphO2SmrNaRfshHAKFa2oqfKCq01f8+emvxdgX/Gcw+pTA8J4U015/JkJfoA== Received: from PH7P223CA0015.NAMP223.PROD.OUTLOOK.COM (2603:10b6:510:338::11) by CY8PR12MB8067.namprd12.prod.outlook.com (2603:10b6:930:74::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.21; Tue, 6 Aug 2024 13:39:50 +0000 Received: from CY4PEPF0000EE3E.namprd03.prod.outlook.com (2603:10b6:510:338:cafe::5f) by PH7P223CA0015.outlook.office365.com (2603:10b6:510:338::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.29 via Frontend Transport; Tue, 6 Aug 2024 13:39:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CY4PEPF0000EE3E.mail.protection.outlook.com (10.167.242.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.19 via Frontend Transport; Tue, 6 Aug 2024 13:39:46 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 06:00:05 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 06:00:04 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 06:00:02 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 09/11] net/mlx5e: Use extack in get module eeprom by page callback Date: Tue, 6 Aug 2024 15:58:02 +0300 Message-ID: <20240806125804.2048753-10-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3E:EE_|CY8PR12MB8067:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d1824b9-edb7-4d36-09e3-08dcb61d3c4f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: 9ZBnlZQD51+qhILo+41GIYhk29qvu8Gj53iANnOS2dFOMimhyFKdheXFWb74zoxJ5DZ7oOeAd0pTCtPaIj9FCc+pZ13qRCugDHlu/tdfz2S/UaRxIX0g29d2EEsaHi/rYWQFxMwiQVuOY1MuNbeAysTvyRLjFOzL7eUEElCHHP7SmeE3IQFYi6/zcYWQD0TQx89AYOOVXQCrBXOu8iJs5dZ3jjd95yX7QwmiRnXDzMKPgTRKwsEJyFyqiJTBmU29uFitbrCZ5458AT0Viqqk8x8UcqGRtjeKiMRHL0npjcT/mQVUNHvjOBT11sedS9pJ9vYTkfFbbcJO9RbHvobsRIFtMO0D6zCeFCb5ZEaQTpJkpUib+d4MiismVqltNoM4s13kOkGv4Ra0JIE9QvN3AV580+6raeBNo0/094RgVt9RmETjU9JyR8OXlb7PS504XKV00WbHAosuUinGEbV9OPFjS0cSTjieK8OzfPhi5rWypjPxrkjIhC41UmTEYJJjk2Z8ZadST47ttNXzhfWph4hlUFtyy4/T2qFfR97GP/niAenKZMEqKaYj9b/AehLCncVmHCziNc/t81iIvDnJnc2N6iWI6x/duy7RAigpYkccg836x/+R5RziHP3TzNqgZhz3ZGgqtqAaHZjcit51KEzkoggbx9SVba54yLAqmPwbnXkerRj0maITdiRJLNg0O2+C6BclQAXRotQvQqojPDAoT7UOY/7sQiUkmT6YmjNJJ83uhLRCzhVRRGFEu69kLCqlVio10G0jUdw9+3Sm2RVnoaxeYFdRiMvnNjKPWyrFf2KW+Gyf0A3auJCSmtnT2IIu+RrHLur/hnNoT8fuQ2E7tArjVu8r7gI1oyACmwn4XH0Dyk8THP+tljkU9D5X5YHlj0kiQzdu0G5XRylvbRWeicY3jGU3YPpHOpx+arj7+bpZZCAxlmLqssamroY2dmPc4WwxWvq5STygtwyJMLFDgm+jOxkOFtaAah1w9KZeEz5Fi+oQBU5LM9rJP5/FphzKdC1CqPi5YkCgyEuG6cXX+4roa8sc29rL9ItTqkba0mipBRHrZDPFEkSLTXUtGQW0kr+qkHiv6dQ8yIkx76EG/ODw4U3z9pWIRD56PnfdxM/3HxeSUZLW1sgDmlei4kn+aVAy9HKFEQXcHCPvnZVHgZCfTO5NAW8NqLcgVoUDc6xHA+nZbD5pRImBe5NsTqhUibb6kYUUsx1nr3BqR2QPGkrSEuG2TFx3jceGRW1jvh1FDzB+rUrvj2+g+dXSHX5SNlmORvWdzTRR+n1ZAhZuZjQf+eF/XuoppbClo+P9VS9p9RV54slHOm3nZDoDn3Ne9a5EgHKSWWyWO/Gu5dasuuo5gkmZaOuI/fR4KmZ90v1Psf/G5ougCSDI6VQnlJtOGe+xpZ0HmcWBh/Lac4F4KXtdNXCzPG8UPYbTX3dg5p82TjvKFRuBDwwJbO6l X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:39:46.0793 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d1824b9-edb7-4d36-09e3-08dcb61d3c4f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8067 X-Patchwork-Delegate: kuba@kernel.org From: Gal Pressman In case of errors in get module eeprom by page, reflect it through extack instead of a dmesg print. While at it, make the messages more human friendly. Signed-off-by: Gal Pressman Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 455d6ef15d07..71c02e77d037 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -2024,8 +2024,10 @@ static int mlx5e_get_module_eeprom_by_page(struct net_device *netdev, if (size_read == -EINVAL) return -EINVAL; if (size_read < 0) { - netdev_err(priv->netdev, "%s: mlx5_query_module_eeprom_by_page failed:0x%x\n", - __func__, size_read); + NL_SET_ERR_MSG_FMT_MOD( + extack, + "Query module eeprom by page failed, read %u bytes, err %d\n", + i, size_read); return i; } From patchwork Tue Aug 6 12:58:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754903 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2081.outbound.protection.outlook.com [40.107.100.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B2491C4622 for ; Tue, 6 Aug 2024 13:39:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.100.81 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722951595; cv=fail; b=T0cu6cIW6BFLJ+mV7qF81lbYlC7zkuf9fcVI0A8JyBUvOzbqwbIsqusnheBFdJ9L4DPZWoZsIIQRuMF4aSX92LHaRWwgm/out9BJ/Cp9IZjQT+lsZlN/1oZ8bmlfuhxvHl54FBLXZ37q4bILiMr48QisW8gJ7973CpNZSBE2v7M= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722951595; c=relaxed/simple; bh=wGr5qERaHR0SQ8Hz6FrTgZTQ63kINg9A5rPW0EFDprE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cDGxAxOFRWy4G58zdiXLGa6nRtwsL7+5Ll02yENXhi3yFC1NwqBrBRTdKJKgKFxY7CKmRMsGn1PPc8MaYTZ1dl/zO0RJp1B9kG8m4YzCmJjerdyLwcy6jRDyZ3f19iYzH2nUcFQWpBTuXSFREhSw62F/B8XseLVdEl7iWe/U5IE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=rxOwNv7c; arc=fail smtp.client-ip=40.107.100.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="rxOwNv7c" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=r2X5scwwWL5Zgvk1Br54F2iMvuo72vZQlBG7oCtw/phS/NPLt69c9iqtHrj90wPc7cBD/f0Km95X9CcklQfN+D63nIVcAmV+YbqhBW2AtIBbX4v2rGwJG1Ogs+5U+QxNTEBtVY/wIrJ+VEO6cvRZHyrjwU5a7HXjII5MmLV03FJ5n8mch3RsMxz31XtIUY/nyuOWjSF1QhAot94fbOT1qsembMqj7UT7xJfcBWFIpxAdA5XzyARofbXqwwbzHHatacVn6f5ew5R6/WKeVA7yh5qd5pHmM9vaQ/GhaGwfHaWryD7JfrylqgZWMcbBPfdBLc1J1QOdi9nsQg0Vlk2d5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XHiiWWl99fZI0fSm8Jbh8oTKzIM48DKXCCIkvG/gFUY=; b=f8HvnM4AwcpQZa9QO+9gKEnugmQLOgmCQgbR6gGQTWtbqxXjSejRrh/r47FqxQzbQk+nX+nXPv4u7/TDQatHEwNp03uUFmPS8G9Y1rXp6RrDqfKeRB2ci9vOYwuxQO29TNZCFtFbiiCp71Q307IWowGHBq9VQCH/hRfQHBty6CJbW486CwDIn1RWpJ0lr3k3VPdH/MRN4oxPWhEPrbx99/m/t6ssObqEDeHhkXMv9CHdQ6TqYeeiEbAUimwXnN7uxblwlann20HaCHeW1xkVd/uTjviomH2jHPbw+CBFwy6xTvWnzDK8z6PBlMC3foJcc3JG6fobVf73sJEzcFAgAw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XHiiWWl99fZI0fSm8Jbh8oTKzIM48DKXCCIkvG/gFUY=; b=rxOwNv7cUXx8OXOt7AqtL8bqvx8dxzVoUbBA8dRjeAMR/82e4XXHHjPFx0ERpLxi0KimtcLebwtu0LbddL6zqrvnYGyX4RFo0bJjKyhIoCKcQZU+jru4j0bVEAheF9UK9MbFM7svFlWc3sM8xr4lbIgCvOIG3zo7ppOgE6JTQITqd3nLBRZFC3YPEfHSP4h4Wigy0c0FjAiKOPlig12Dkjzpuey9qBDnC/GKU2Lmf9sv3bmMtKV9JCoRhwwnFfxS/+jsUF342i5DatxPu+M4M0SEkgvGC/dreqDQ4N7yUU/N2GSNCKP7C4rZ81uoqH/0jRRCZjK4WHqO8WoqeO2E6Q== Received: from CY5PR17CA0007.namprd17.prod.outlook.com (2603:10b6:930:17::20) by DM6PR12MB4267.namprd12.prod.outlook.com (2603:10b6:5:21e::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.29; Tue, 6 Aug 2024 13:39:47 +0000 Received: from CY4PEPF0000EE3D.namprd03.prod.outlook.com (2603:10b6:930:17:cafe::1d) by CY5PR17CA0007.outlook.office365.com (2603:10b6:930:17::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.12 via Frontend Transport; Tue, 6 Aug 2024 13:39:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CY4PEPF0000EE3D.mail.protection.outlook.com (10.167.242.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.19 via Frontend Transport; Tue, 6 Aug 2024 13:39:46 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 06:00:08 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 06:00:07 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 06:00:05 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 10/11] net/mlx5e: CT: 'update' rules instead of 'replace' Date: Tue, 6 Aug 2024 15:58:03 +0300 Message-ID: <20240806125804.2048753-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3D:EE_|DM6PR12MB4267:EE_ X-MS-Office365-Filtering-Correlation-Id: 61188a5a-12af-4fe8-9f70-08dcb61d3cd9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: GLRknfFbmpSI5dCd8AnlXDhqojoWxaqIvhsL9VMMF7OGOKCmtzBC6pbxdF2nUWL5YeC6WqpD5dCV5zUaqpjvp/1XddGR4mlN+j+Q2wfChHKYBI/d2alEY+/c3m8MlsJ5MKcYDy7vG/00lAFYB4+2jZI0kxF0toNmCzbzXACQfz4x4V5YaKQX+xyzlsNFiogApPO8Ue0eQhSw/1ujTCwioCDBwTQxojLyoaBWljBuKImcQZhzJXaDjt4bj+nOhHHkIu74GHCgglIUwZ3bH/4VgineeqrRaljWV8gMuiXsRdQmohUP7ysuGzBNyrmg3LYo+iYK8NxmF1QNnCo6RQ+Pub9YA+yJwhqg1sKJt0wqaTXNUs4o4wYv2FHAxAX/9y+u9t6dFZsE2nnMj/Y+AiJ9oIZaSLsS+A3W/CsyEcsuKormcP8Zp924G/D4PMnP3v/7+Tja2x4znMByiwkXlXIUIb7zgLhfmeKYPJcQrWqbVoAyHwJUlRroHjq5dGKNkggmtpgLQBIzYnt4EIcBdZxADmRe+buwYRfe7imtCIwSGnRCdX2jQGE8Fdygx3Nact1PmY9bx5i7ZPTrCncofhhxIUH6yN32oph+2r8wCrSKHwR57hD6FVIK8XST1o0BsSlFq3lUKa310mUaae8v+sSk/McipIChE/nVcK8bC1JtzNvQ7OfYzQqFznG0kxrx8bIAS6UpDwHY8G8jskHsWcGcPBW+OwzX4V/dLgYyaSjWbsWTk75KrXqwHgNN4UDzGBUf7FHXicZp8A2GR1du5WB9/8PEw7skHA8HungZDlX+l1MGPjBzWNkxprWKNi9RmVhtIeUq/MrQPjX50PSRpyra9SaSa1UHUdXRuK3wMarxyedtTzSJVXrvUlP8rpYIRlh3/E5zYdFW3fBR9o86MVQv31P/AUnT4LZngG1mMAJMRvF9s95uJiuR43Gl8PIDiHsMJ2XSfW/mwzuGtYAN1w+rUikDxDjgKkTR8AKC70juCQAl+lsw175Rhn5T/w/eoSon3fHixipV/WcNDFuOu2K/fgAemOGpQBpUT6tUTkVjcx4rbnKAxHHadueUl4fcMXQoHQw3FrBLpiP8B6I5t97oeCoQ3ZHbBs53GhYrnOXWngg34Uqq/VBsvP4OIk77KsRTTfBbvak1Ql50CrYErwhZFSa7WdcKdVAw+TpBvbkI1anGEBYbueJspa31D6mhaxE6BJAMmsWSy7iF8k2Io7mEbQl1AtKdowy/GWnUWygnJk32/I0SE4KnCa0I+yjjt3johhMbSdwDAJba+/4oIC/WivMVHQnzIAwxK/D3cUEd+vRulpxUueZ/unRca3nPWWTpVna082AJobl0QLj47A0fgYFiVFf3kL6Rq5vDejH+5pwdiD574e8MC07VGaIlwglPcWwZRGZ9BJgi1fQuMJb+L9xQaoL1WD1SF88zMICx0aOExq0H4TCJZsb4faEg3iJt X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:39:46.9876 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61188a5a-12af-4fe8-9f70-08dcb61d3cd9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4267 X-Patchwork-Delegate: kuba@kernel.org From: Cosmin Ratiu Offloaded rules can be updated with a new modify header action containing a changed restore cookie. This was done using the verb 'replace', while in some configurations 'update' is a better fit. This commit renames the functions used to reflect that. Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/tc_ct.c | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c index 71a168746ebe..ccee07d6ba1d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c @@ -876,10 +876,10 @@ mlx5_tc_ct_entry_add_rule(struct mlx5_tc_ct_priv *ct_priv, } static int -mlx5_tc_ct_entry_replace_rule(struct mlx5_tc_ct_priv *ct_priv, - struct flow_rule *flow_rule, - struct mlx5_ct_entry *entry, - bool nat, u8 zone_restore_id) +mlx5_tc_ct_entry_update_rule(struct mlx5_tc_ct_priv *ct_priv, + struct flow_rule *flow_rule, + struct mlx5_ct_entry *entry, + bool nat, u8 zone_restore_id) { struct mlx5_ct_zone_rule *zone_rule = &entry->zone_rules[nat]; struct mlx5_flow_attr *attr = zone_rule->attr, *old_attr; @@ -924,7 +924,7 @@ mlx5_tc_ct_entry_replace_rule(struct mlx5_tc_ct_priv *ct_priv, kfree(old_attr); kvfree(spec); - ct_dbg("Replaced ct entry rule in zone %d", entry->tuple.zone); + ct_dbg("Updated ct entry rule in zone %d", entry->tuple.zone); return 0; @@ -1141,23 +1141,23 @@ mlx5_tc_ct_entry_add_rules(struct mlx5_tc_ct_priv *ct_priv, } static int -mlx5_tc_ct_entry_replace_rules(struct mlx5_tc_ct_priv *ct_priv, - struct flow_rule *flow_rule, - struct mlx5_ct_entry *entry, - u8 zone_restore_id) +mlx5_tc_ct_entry_update_rules(struct mlx5_tc_ct_priv *ct_priv, + struct flow_rule *flow_rule, + struct mlx5_ct_entry *entry, + u8 zone_restore_id) { int err = 0; if (mlx5_tc_ct_entry_in_ct_table(entry)) { - err = mlx5_tc_ct_entry_replace_rule(ct_priv, flow_rule, entry, false, - zone_restore_id); + err = mlx5_tc_ct_entry_update_rule(ct_priv, flow_rule, entry, false, + zone_restore_id); if (err) return err; } if (mlx5_tc_ct_entry_in_ct_nat_table(entry)) { - err = mlx5_tc_ct_entry_replace_rule(ct_priv, flow_rule, entry, true, - zone_restore_id); + err = mlx5_tc_ct_entry_update_rule(ct_priv, flow_rule, entry, true, + zone_restore_id); if (err && mlx5_tc_ct_entry_in_ct_table(entry)) mlx5_tc_ct_entry_del_rule(ct_priv, entry, false); } @@ -1165,13 +1165,13 @@ mlx5_tc_ct_entry_replace_rules(struct mlx5_tc_ct_priv *ct_priv, } static int -mlx5_tc_ct_block_flow_offload_replace(struct mlx5_ct_ft *ft, struct flow_rule *flow_rule, - struct mlx5_ct_entry *entry, unsigned long cookie) +mlx5_tc_ct_block_flow_offload_update(struct mlx5_ct_ft *ft, struct flow_rule *flow_rule, + struct mlx5_ct_entry *entry, unsigned long cookie) { struct mlx5_tc_ct_priv *ct_priv = ft->ct_priv; int err; - err = mlx5_tc_ct_entry_replace_rules(ct_priv, flow_rule, entry, ft->zone_restore_id); + err = mlx5_tc_ct_entry_update_rules(ct_priv, flow_rule, entry, ft->zone_restore_id); if (!err) return 0; @@ -1216,7 +1216,7 @@ mlx5_tc_ct_block_flow_offload_add(struct mlx5_ct_ft *ft, entry->restore_cookie = meta_action->ct_metadata.cookie; spin_unlock_bh(&ct_priv->ht_lock); - err = mlx5_tc_ct_block_flow_offload_replace(ft, flow_rule, entry, cookie); + err = mlx5_tc_ct_block_flow_offload_update(ft, flow_rule, entry, cookie); mlx5_tc_ct_entry_put(entry); return err; } From patchwork Tue Aug 6 12:58:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13754904 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2076.outbound.protection.outlook.com [40.107.212.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C42461C4622 for ; Tue, 6 Aug 2024 13:39:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.212.76 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722951599; cv=fail; b=BSqYPa0SuhfpQzsAfo7akAz6ez8ad4H+gLtDDwC/E8TIznWQD7cL6Nm4qv4igpKB3qoA4dml2D15ZQSh9GHta2urcm1OC1d6B2wIPGuL0eMGvSGfA1f3yfDfKftWjvdsXzkQecZ4UKG1jRayeTKRZ0d5swDSRiWrnmIIEndr7Co= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722951599; c=relaxed/simple; bh=0U8xYOqNwFaft+c6ZXZVcDB172Dnw2o0Sh5JpJ3gZrU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rV4nKn/+aeZ7qkYi1mBSuraHtBtQ3NNFUwN3QZQzYvFa0fsWVV9ET+ohlxWB0YMpvlhrjOZxLwoE5vHMN8F/8Eg30A1EZztNOdIicftZTBP/uJ6jv5mc2B8LlQ9XhbMx9XaSyQzskjZfU5dQn+zWiS4YlZJlpqUuasNV5iFp3mA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=bqsONWQ+; arc=fail smtp.client-ip=40.107.212.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="bqsONWQ+" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=XxHjlPA+Im8/MMrK2+8r/IYrcDjPIV79uYCEHJUDU2gOv+vt78qS7tEitnL0hbi81TaMZzdvxi4XNNDhr+hMVs+AK6uyP1uudodovXWJp/fXs5ZGlKfKx8PjixRQOo9fjOQr9Igu2LhsecXfDid9CiM98/R7CSqoL3Pk4iTkKs5w7zoXN6hipts5KAXrMWhqEziM4QleYUjQZlA9VW4NmvbkktfS8DNa+fifJ3sivpCEOYPGj0NheVKHiP2Xer8E6kCqjw1yoJ53xiY6h+Z7+RiT6TtS6bETCZm02AEs860682hp574ChO/gXG60QHIoEnOURmcCq6zlC+rwIRzSdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ftQZCRzAw/XMcpxvhNLEX70wxbUeedk3pIzb1lwNJK4=; b=zGps2CO8YhWzGdKcBDevhu3IMtCuGXNBoJNiTGqcjTvJFGGgmCOl/lWvXoXoM8luuqsNGugUyaBzTfSvQMOt6AzQPGLOH36zdKsG5JbB/q3MGjDa2zHshgYziHT6csnB+sOGLKCfYy/7vqN22wY3m0ua/93rNpv49NVakQMdVV1jT5TNAIjuIbaUd1E+vuO/56Y2Y9tulIBaENBKnIS3hw1pCmhrhyBdPQVk1sBiR2uQJ5Wn3AWkMg8D+aI/6GoG7C264ZoxQshpPEuhLEm3LTeCQI5UIQHoFLZAutoVadt5BKN4yC0bLMHeqSOduoKgMZY02lZEmzY5lrcQzwgSvg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ftQZCRzAw/XMcpxvhNLEX70wxbUeedk3pIzb1lwNJK4=; b=bqsONWQ+HYuoxGBMCY+Sjgj/EVQzDv18a/lOu99ZUq2L+tfYGmWDR7tmEawtwvr5vYLeEkFjncmrTcvPY9O7GzuBXa16QLJENCMmCJUVn02mohJ4v6exgPXsje/jbCakr1940e5tbZMaXUuFA5UMufAqloRh2exN506HxaI/GEYaKdgrC6uSFDixBc1RZ8qRPhO4R2SgWhdInGPOlK+0twnKQCIimKp6vWvLdDNLBUKKzqqWgh4pr0tKNAbH+5qvhFKAYj6yaX4ziGbN7wBmALbKpwkEAxBd0OKDKTtAai7qWMAft1/mcA+eNm/eqJ8mUZkleDKT2KAo0lU+h6knhg== Received: from BYAPR06CA0018.namprd06.prod.outlook.com (2603:10b6:a03:d4::31) by SN7PR12MB6690.namprd12.prod.outlook.com (2603:10b6:806:272::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.23; Tue, 6 Aug 2024 13:39:49 +0000 Received: from CY4PEPF0000EE3F.namprd03.prod.outlook.com (2603:10b6:a03:d4:cafe::cc) by BYAPR06CA0018.outlook.office365.com (2603:10b6:a03:d4::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.29 via Frontend Transport; Tue, 6 Aug 2024 13:39:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CY4PEPF0000EE3F.mail.protection.outlook.com (10.167.242.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.19 via Frontend Transport; Tue, 6 Aug 2024 13:39:47 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 06:00:11 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 06:00:11 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 06:00:08 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 11/11] net/mlx5e: CT: Update connection tracking steering entries Date: Tue, 6 Aug 2024 15:58:04 +0300 Message-ID: <20240806125804.2048753-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240806125804.2048753-1-tariqt@nvidia.com> References: <20240806125804.2048753-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3F:EE_|SN7PR12MB6690:EE_ X-MS-Office365-Filtering-Correlation-Id: e205d781-8913-4211-defb-08dcb61d3d4f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: +xYlyfCOVOsFjkJMiXxUsm+AtZ3DPjMcTRQ2DlsyNiHQwJP2OQU6rG1Sx+YEaV2FqWGeo9rfmdmyr2v+zsDopxoEkwHjGCzmURzv8iqMIJO3ME1/g/ECBkDC40bJPKcYyMPfFzPkQHzBDyb8nFrn+Gkl38r22GHj56Ecms79k5540Y+a5UcwZBTFQw9GU/gUBtTA/dnNwtxoa9cXDZTgjfe6qwm0UCb+BiOu1wNPPlY7/2C9nc6OmFMoPw1+St73K9JHorQCaOUtDsTl/aQm2bU7USg+h2v50OEX/RN/ROv0gqwrFXkI7uJ9pK0gyzFQywAeAh0ZAKCb5wIxZwva9lSefebNfeljyWMcKECJNSd/YK76SbTy+4nMrWhmooXDUU/ldTmV8+d/1UXWXvwzt8ueHFxJjjjebePC5RG6bXpxWPbVdYBfv6cWtFpJ1Ql7cB1mH8IHr531n0vZnBgY2wxCrh18LPWS1YvJ2lJuKlGAEZyTZYTUw5IkjNsBHTz20lGOMPBZN16fLa6yTZzxnRiczj+ZaIWGXBmivBy7WzuXGnRMiCYnigBE57RZ1DQu+DxWlSX71q1zh1OsDqycZpWf9qphwxCDWmAlFJAQfGZ4vxVfk+U0j8Ar9ypGRALOdvJTPG7N8noRljrGm1oQekkqNdrFxpO4EBB90spc5rl+4hZTdIGRA6SpIMp//fNypHC1OoQagkIncrrxFJUxN6njgpW2dbqBJsX8kYmnhNfcCVAp+wmiXIXP5ZjAhWkRQ51MgPjxY49V9XqUzkCWk5ZMtto2p8VZUmwo67f8SVasbg/k9G7xfYh4stxtuDGul+6rfk+vGMryUMgSHkjBQZJ6k50WIB1HQd3bCy/eYpqloiX7exY1YNd7DjQCncW2tZIbfRioejLS5LqczkKgRLJk9m/2AGGGC/JadY0k+uVsVwihznzwIPjJunfc2+WtQu85zGqviWAnadcMrAaITrjF4Tffy7ixAim+13epPOTeU7FhXIs+kwg5jMId1VkfdIZxJ/0sMx1aAbBUbvPm5TYA+chthgornAl96o73bfgUhc2f/JzykGM5DxA/ybLFPOO6GF9HSgIrCQiGWZQFBf6KmEsmLu2mNPjk9ge5dOVLoHibs7+O1m/g1zzCUWa1LmAbmiyytbIWoU5H55X0ofytLpx2KivRC59B+ZJN3zsSM8AH849Osq8rFZTlEXpMUWisTAv5pfGB+1ekyFbhZC4fQBNpRVwC285nD6ZFRXJImFnTq5y/dmaGADY26jFa+WpfSVyIbozWTnDMLstSPxToAVHwm7HVKIqi3rXg3wZUDIVel1/O3DNRBJaxaXVbMNK3w6zhQDPYwG6m83cHtr98eCiGUwpaHxMFKZQLNmAiMB/CQzkFtAmog6WXFvwl8+fIzNE0DKQ07ml+rLxeDY0mlN3DntPsqA1r7/I3Dv3B4f6lFIw494fa0hC7n3cf X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 13:39:47.7625 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e205d781-8913-4211-defb-08dcb61d3d4f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6690 X-Patchwork-Delegate: kuba@kernel.org From: Cosmin Ratiu Previously, replacing a connection tracking steering entry was done by adding a new rule (with the same tag but possibly different mod hdr actions/labels) then removing the old rule. This approach doesn't work in hardware steering because two steering entries with the same tag cannot coexist in a hardware steering table. This commit prepares for that by adding a new ct_rule_update operation on the ct_fs_ops struct which is used instead of add+delete. Implementations for both dmfs (firmware steering) and smfs (software steering) are provided, which simply add the new rule and delete the old one. Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/tc/ct_fs.h | 2 ++ .../mellanox/mlx5/core/en/tc/ct_fs_dmfs.c | 21 +++++++++++++++ .../mellanox/mlx5/core/en/tc/ct_fs_smfs.c | 26 +++++++++++++++++++ .../ethernet/mellanox/mlx5/core/en/tc_ct.c | 12 +++------ 4 files changed, 53 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs.h b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs.h index bb6b1a979ba1..62b3f7ff5562 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs.h @@ -25,6 +25,8 @@ struct mlx5_ct_fs_ops { struct mlx5_flow_attr *attr, struct flow_rule *flow_rule); void (*ct_rule_del)(struct mlx5_ct_fs *fs, struct mlx5_ct_fs_rule *fs_rule); + int (*ct_rule_update)(struct mlx5_ct_fs *fs, struct mlx5_ct_fs_rule *fs_rule, + struct mlx5_flow_spec *spec, struct mlx5_flow_attr *attr); size_t priv_size; }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_dmfs.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_dmfs.c index ae4f55be48ce..64a82aafaaca 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_dmfs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_dmfs.c @@ -65,9 +65,30 @@ mlx5_ct_fs_dmfs_ct_rule_del(struct mlx5_ct_fs *fs, struct mlx5_ct_fs_rule *fs_ru kfree(dmfs_rule); } +static int mlx5_ct_fs_dmfs_ct_rule_update(struct mlx5_ct_fs *fs, struct mlx5_ct_fs_rule *fs_rule, + struct mlx5_flow_spec *spec, struct mlx5_flow_attr *attr) +{ + struct mlx5_ct_fs_dmfs_rule *dmfs_rule = container_of(fs_rule, + struct mlx5_ct_fs_dmfs_rule, + fs_rule); + struct mlx5e_priv *priv = netdev_priv(fs->netdev); + struct mlx5_flow_handle *rule; + + rule = mlx5_tc_rule_insert(priv, spec, attr); + if (IS_ERR(rule)) + return PTR_ERR(rule); + mlx5_tc_rule_delete(priv, dmfs_rule->rule, dmfs_rule->attr); + + dmfs_rule->rule = rule; + dmfs_rule->attr = attr; + + return 0; +} + static struct mlx5_ct_fs_ops dmfs_ops = { .ct_rule_add = mlx5_ct_fs_dmfs_ct_rule_add, .ct_rule_del = mlx5_ct_fs_dmfs_ct_rule_del, + .ct_rule_update = mlx5_ct_fs_dmfs_ct_rule_update, .init = mlx5_ct_fs_dmfs_init, .destroy = mlx5_ct_fs_dmfs_destroy, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_smfs.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_smfs.c index 8c531f4ec912..1c062a2e8996 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_smfs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_smfs.c @@ -368,9 +368,35 @@ mlx5_ct_fs_smfs_ct_rule_del(struct mlx5_ct_fs *fs, struct mlx5_ct_fs_rule *fs_ru kfree(smfs_rule); } +static int mlx5_ct_fs_smfs_ct_rule_update(struct mlx5_ct_fs *fs, struct mlx5_ct_fs_rule *fs_rule, + struct mlx5_flow_spec *spec, struct mlx5_flow_attr *attr) +{ + struct mlx5_ct_fs_smfs_rule *smfs_rule = container_of(fs_rule, + struct mlx5_ct_fs_smfs_rule, + fs_rule); + struct mlx5_ct_fs_smfs *fs_smfs = mlx5_ct_fs_priv(fs); + struct mlx5dr_action *actions[3]; /* We only need to create 3 actions, see below. */ + struct mlx5dr_rule *rule; + + actions[0] = smfs_rule->count_action; + actions[1] = attr->modify_hdr->action.dr_action; + actions[2] = fs_smfs->fwd_action; + + rule = mlx5_smfs_rule_create(smfs_rule->smfs_matcher->dr_matcher, spec, + ARRAY_SIZE(actions), actions, spec->flow_context.flow_source); + if (!rule) + return -EINVAL; + + mlx5_smfs_rule_destroy(smfs_rule->rule); + smfs_rule->rule = rule; + + return 0; +} + static struct mlx5_ct_fs_ops fs_smfs_ops = { .ct_rule_add = mlx5_ct_fs_smfs_ct_rule_add, .ct_rule_del = mlx5_ct_fs_smfs_ct_rule_del, + .ct_rule_update = mlx5_ct_fs_smfs_ct_rule_update, .init = mlx5_ct_fs_smfs_init, .destroy = mlx5_ct_fs_smfs_destroy, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c index ccee07d6ba1d..dcfccaaa8d91 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c @@ -884,7 +884,6 @@ mlx5_tc_ct_entry_update_rule(struct mlx5_tc_ct_priv *ct_priv, struct mlx5_ct_zone_rule *zone_rule = &entry->zone_rules[nat]; struct mlx5_flow_attr *attr = zone_rule->attr, *old_attr; struct mlx5e_mod_hdr_handle *mh; - struct mlx5_ct_fs_rule *rule; struct mlx5_flow_spec *spec; int err; @@ -902,22 +901,19 @@ mlx5_tc_ct_entry_update_rule(struct mlx5_tc_ct_priv *ct_priv, err = mlx5_tc_ct_entry_create_mod_hdr(ct_priv, attr, flow_rule, &mh, zone_restore_id, nat, mlx5_tc_ct_entry_in_ct_nat_table(entry)); if (err) { - ct_dbg("Failed to create ct entry mod hdr"); + ct_dbg("Failed to create ct entry mod hdr, err: %d", err); goto err_mod_hdr; } mlx5_tc_ct_set_tuple_match(ct_priv, spec, flow_rule); mlx5e_tc_match_to_reg_match(spec, ZONE_TO_REG, entry->tuple.zone, MLX5_CT_ZONE_MASK); - rule = ct_priv->fs_ops->ct_rule_add(ct_priv->fs, spec, attr, flow_rule); - if (IS_ERR(rule)) { - err = PTR_ERR(rule); - ct_dbg("Failed to add replacement ct entry rule, nat: %d", nat); + err = ct_priv->fs_ops->ct_rule_update(ct_priv->fs, zone_rule->rule, spec, attr); + if (err) { + ct_dbg("Failed to update ct entry rule, nat: %d, err: %d", nat, err); goto err_rule; } - ct_priv->fs_ops->ct_rule_del(ct_priv->fs, zone_rule->rule); - zone_rule->rule = rule; mlx5_tc_ct_entry_destroy_mod_hdr(ct_priv, old_attr, zone_rule->mh); zone_rule->mh = mh; mlx5_put_label_mapping(ct_priv, old_attr->ct_attr.ct_labels_id);