From patchwork Tue Aug 6 13:33:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 13754916 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 741881D1F52 for ; Tue, 6 Aug 2024 13:34:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722951297; cv=none; b=RP27afZhS6SdIymHKznpQ/QRH5AktlnelTlyBxaMVLmIpYEbKNXXkB0TBhrWcbvq1mN2b+2KVc5bw/Z+yLLVBjbL7zJQIdX3nJu9WeuEtqNjrds4vuQoRGbcGJ1wO8gsUkbE/2XNO7WIdu3BiaoEdszzGAe4K0tGYz1JpD4tgrM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722951297; c=relaxed/simple; bh=UdzWhsd9oz0+AmDdGddx8suhoSHnbzpjtEd4LPJVNzc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M97FxKQHaLrS9IAlG3Q7gIagZkTsOfyS1YEo0Z6jxSYobRXnRZaRaqGuLR1QujScLPIeW0xtHmBqMjNGXi9UEyd7dLsj6XDIyJSPYAhwfcQboVualVOMZQLbLXbZuBrCSDa2a1ainqIYaFpM05oSl/qjho+/F6YMmolBF31eIT4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=fail smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=S0b8PbWB; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="S0b8PbWB" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0F3DEBFBCA; Tue, 6 Aug 2024 15:34:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1722951292; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=oGGBzcnOnP0mo+bJ5KHmTIO9dRW6gvWt4+kpJJygojQ=; b=S0b8PbWBmhssF5D9k42QB4s6ZzguC5h/YbvfPLQdBtYJ4ffo8kF/5LbZYfVoGiVZ+qLA14 CaqVihMfpLlqKc5S/wIU01hVRBpoHr1eKMgL38NgPbWwM55lRaAg0C7d0LD0HyTvvbUzpa kYxC+WLEZVaqKg6aL8TXO+eXByLlhaC68f6XEmjUes6FWCDinyIlXMk6B8PXD0uQHplPXe 3QJiK+dgjoq4t2G2TvT1skNCy+Bd32bgoB4tdCvWAkBQXZOW4+DKIjBopGOOf6zl6oaQIX m9XmgT9e7cD/1ONDkxuiFvs1TEiIdN+J3hgUdBpVak1nOm6dbYFnGDm8HpOhIg== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Pengutronix Kernel Team Subject: [PATCH 3/4] arm64: dts: imx8mm-kontron: Add support for display bridges on BL i.MX8MM Date: Tue, 6 Aug 2024 15:33:01 +0200 Message-ID: <20240806133352.440922-4-frieder@fris.de> In-Reply-To: <20240806133352.440922-1-frieder@fris.de> References: <20240806133352.440922-1-frieder@fris.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 From: Frieder Schrempf The Kontron Electronics BL i.MX8MM has oboard disply bridges for DSI->HDMI and DSI->LVDS conversion. The DSI interface is muxed by a GPIO-controlled switch to one of these two bridges. By default the HDMI bridge is enabled. The LVDS bridge can be selected by loading an additional (panel-specific) overlay. Signed-off-by: Frieder Schrempf --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index aab8e24216501..2b344206dfd16 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -25,6 +25,17 @@ osc_can: clock-osc-can { clock-output-names = "osc-can"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_in_conn: endpoint { + remote-endpoint = <&bridge_out_conn>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -132,6 +143,90 @@ ethphy: ethernet-phy@0 { }; }; +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + + dsi_mux_sel_hdmi: dsi-mux-sel-hdmi-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "dsi-mux-sel"; + }; + + dsi_mux_sel_lvds: dsi-mux-sel-lvds-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "dsi-mux-sel"; + status = "disabled"; + }; + + dsi-mux-oe-hog { + gpio-hog; + gpios = <15 GPIO_ACTIVE_LOW>; + output-high; + line-name = "dsi-mux-oe"; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + hdmi: hdmi@39 { + compatible = "adi,adv7535"; + reg = <0x39>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7535>; + + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + + adi,dsi-lanes = <4>; + + a2vdd-supply = <®_vdd_1v8>; + avdd-supply = <®_vdd_1v8>; + dvdd-supply = <®_vdd_1v8>; + pvdd-supply = <®_vdd_1v8>; + v1p2-supply = <®_vdd_1v8>; + v3p3-supply = <®_vdd_3v3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in_dsi_hdmi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + }; + }; + + port@1 { + reg = <1>; + + bridge_out_conn: endpoint { + remote-endpoint = <&hdmi_in_conn>; + }; + }; + }; + }; + + lvds: bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sn65dsi84>; + status = "disabled"; + }; +}; + &i2c4 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -144,6 +239,30 @@ rx8900: rtc@32 { }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <54000000>; + /* + * Let the driver calculate an appropriate clock rate based on the pixel + * clock instead of using the fixed value from imx8mm.dtsi. + */ + /delete-property/ samsung,pll-clock-frequency; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out_bridge: endpoint { + remote-endpoint = <&bridge_in_dsi_hdmi>; + }; + }; + }; +}; + &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; @@ -207,6 +326,12 @@ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio>; + pinctrl_adv7535: adv7535grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 + >; + }; + pinctrl_can: cangrp { fsl,pins = < MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 @@ -277,6 +402,20 @@ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 >; }; + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 @@ -290,6 +429,13 @@ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 >; }; + pinctrl_sn65dsi84: sn65dsi84grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x19 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 From patchwork Tue Aug 6 13:33:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 13754917 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA1161D1F7A for ; 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arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="oj4gNLkL" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B6D48BFBCA; Tue, 6 Aug 2024 15:35:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1722951304; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=yYAWlvlFpcv953bwrA/R1Uh/nypbpFD6Q8hQPr+IE80=; b=oj4gNLkL5w7jiNzhUxrADUMvq9ZtRM22/fsBc8MoR2o4+j/DjD6U+py15/IaE3RSgC3iqe EgrGPV9fiTy+mMUU1c7WO8JJ39gWGPP54zvJXsVdl5FrpKeYV0nrxcy9mMB6Y4OIRSbiLM odXCO5g8meE0dV/zUTSoha6sUVP+GMufvSdB7br1aP1hden0Y1A42uOoMGC5X1NLu/NJQ4 4TBC6BBRBBTMW5FajZ7pArti/k4plOgf5KKquFWkYiB8jeuCCUSYINLbseDCIMxC1hnMRZ 7AfBTHc2ZcR+8jh+vP9NTnY5ysfMOa16bUE3E6VHllcV0QxaRq8fcMdvuHcUow== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Alexander Stein , Fabio Estevam , Francesco Dolcini , Gregor Herburger , Hugo Villeneuve , Joao Paulo Goncalves , Mathieu Othacehe , Parthiban Nallathambi , Pengutronix Kernel Team Subject: [PATCH 4/4] arm64: dts: imx8mm-kontron: Add DL (Display-Line) overlay with LVDS support Date: Tue, 6 Aug 2024 15:33:02 +0200 Message-ID: <20240806133352.440922-5-frieder@fris.de> In-Reply-To: <20240806133352.440922-1-frieder@fris.de> References: <20240806133352.440922-1-frieder@fris.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 From: Frieder Schrempf The Kontron Electronics DL i.MX8MM consists of the BL i.MX8MM board and a 7" LVDS panel. Provide an overlay that enables the panel. Signed-off-by: Frieder Schrempf --- Note: This currently throws the following warnings: Warning (graph_port): /fragment@3: graph port node name should be 'port' Warning (graph_endpoint): /fragment@3/__overlay__: graph endpoint node name should be 'endpoint' Warning (graph_endpoint): /fragment@3/__overlay__: graph connection to node '/fragment@7/__overlay__/ports/port@0/endpoint' is not bidirectional There is the following commit in DTC that relaxes these checks and will eventually resolve these warnings: 84b056a89d ("checks: relax graph checks for overlays") https://git.kernel.org/pub/scm/utils/dtc/dtc.git/commit/?id=84b056a89d3c5b6cf6c5eeeafd4c4b14d6333aa9 --- arch/arm64/boot/dts/freescale/Makefile | 4 + .../boot/dts/freescale/imx8mm-kontron-dl.dtso | 210 ++++++++++++++++++ 2 files changed, 214 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f04c22b7de72e..d8af069139920 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -244,6 +244,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb +imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb + imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso b/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso new file mode 100644 index 0000000000000..b2d593d700e2d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Kontron Electronics GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include "imx8mm-pinfunc.h" + +&{/} { + compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000 0>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <100>; + }; + + panel { + compatible = "jenson,bl-jt60050-01a", "panel-lvds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + backlight = <&backlight>; + data-mapping = "vesa-24"; + enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + height-mm = <86>; + width-mm = <154>; + + panel-timing { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hsync-len = <1>; + hfront-porch = <160>; + hback-porch = <160>; + vsync-len = <1>; + vfront-porch = <12>; + vback-porch = <23>; + }; + + port { + panel_out_bridge: endpoint { + remote-endpoint = <&bridge_out_panel>; + }; + }; + }; +}; + +&dsi_mux_sel_hdmi { + status = "disabled"; +}; + +&dsi_mux_sel_lvds { + status = "okay"; +}; + +&dsi_out_bridge { + remote-endpoint = <&bridge_in_dsi_lvds>; +}; + +&gpio3 { + panel-rst-hog { + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "panel-reset"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_rst>; + }; + + panel-stby-hog { + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "panel-standby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_stby>; + }; + + panel-hinv-hog { + gpio-hog; + gpios = <24 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "panel-horizontal-invert"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_hinv>; + }; + + panel-vinv-hog { + gpio-hog; + gpios = <25 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "panel-vertical-invert"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_vinv>; + }; +}; + +&hdmi { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + gt911@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio3>; + interrupts = <22 8>; + reset-gpios = <&gpio3 23 0>; + irq-gpios = <&gpio3 22 0>; + }; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in_dsi_lvds: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <1 2>; + }; + }; + + port@2 { + reg = <2>; + + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 + >; + }; + + pinctrl_panel_hinv: panelhinvgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 + >; + }; + + pinctrl_panel_rst: panelrstgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 + >; + }; + + pinctrl_panel_stby: panelstbygrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 + >; + }; + + pinctrl_panel_vinv: panelvinvgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 + >; + }; +};