From patchwork Tue Aug 6 16:31:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13755102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED12DC52D70 for ; Tue, 6 Aug 2024 16:32:35 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.772952.1183397 (Exim 4.92) (envelope-from ) id 1sbN6e-00067p-JK; Tue, 06 Aug 2024 16:32:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 772952.1183397; Tue, 06 Aug 2024 16:32:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sbN6e-00067i-F1; Tue, 06 Aug 2024 16:32:16 +0000 Received: by outflank-mailman (input) for mailman id 772952; Tue, 06 Aug 2024 16:32:15 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sbN6d-0005tQ-4i for xen-devel@lists.xenproject.org; Tue, 06 Aug 2024 16:32:15 +0000 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on20600.outbound.protection.outlook.com [2a01:111:f403:2416::600]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 6eb5f844-5411-11ef-8776-851b0ebba9a2; Tue, 06 Aug 2024 18:32:13 +0200 (CEST) Received: from SN7PR04CA0114.namprd04.prod.outlook.com (2603:10b6:806:122::29) by PH8PR12MB6940.namprd12.prod.outlook.com (2603:10b6:510:1bf::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.13; Tue, 6 Aug 2024 16:32:08 +0000 Received: from SN1PEPF0002636D.namprd02.prod.outlook.com (2603:10b6:806:122:cafe::8e) by SN7PR04CA0114.outlook.office365.com (2603:10b6:806:122::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.23 via Frontend Transport; Tue, 6 Aug 2024 16:32:08 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SN1PEPF0002636D.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7828.19 via Frontend Transport; Tue, 6 Aug 2024 16:32:07 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 6 Aug 2024 11:32:06 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Tue, 6 Aug 2024 11:32:06 -0500 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6eb5f844-5411-11ef-8776-851b0ebba9a2 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CUKCNick5EhAwmTXGGCiAUvG56sGGIbE/0jlDjrMENTfq0HpwciTNqH4BhKAEEOgA7Sud9VaTxOUEYp8U0CFxvZBwileaQUscG1IZwoHm2j31EyxyVXGgpM7KZSnasJa19V/UiaHm6kpHM6leKdMikdGpTf34DeifJlHXJ8Qvro6tJwT/Q5+t7Eb+Hm0rN5hq3YXtA20d1m83rkxPpZzuex+PliFR+NhFkSRppeu/yAU2boeVFNTqsfYNoVlGEZKLvYXwq+XCWRYIi1bECOjp1C7vOyy4do3kwne45NpVw+SaeFMDs9SI8xJO64NZlneMxsPbTh7Y1kOzbPQt+c/WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sjXHs0GS12gvovEpgz4SBPfUlhQQ5tb3kdEgFOzd9ik=; b=yQ8wsGhkCFKWxBhthWaf8NucgmpNyNUQc9xoFFbSxbehFojuy2jBmPrGi6C384fj6zymqrCa14iaWbrwb4J7rrA8nSwt90ZZGsNWfkbEyCEdirozt8rfvOHG/q2SpD5S3CRtAjirjKKHvrJwR+2x1M/htHdkqBBa3rOeinePKe6O+Eo88yPS2dkFI1iiTiOVewbaaia18u+9KPHyK9LrVivoSwmmR4VB9Y13QEc1XDg760Pj6Jx5YnMBT6I3VUzf2rlpuwlnNyLYv3IVTHYJMEIbL+KHyyGovYYenOUKEluCpwHslcdOwIP4rZi2H2Mrmqw/zeGcMG03eM3m56OSZQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sjXHs0GS12gvovEpgz4SBPfUlhQQ5tb3kdEgFOzd9ik=; b=BDGCIU9pQoq3hqv5R4kBzTxP/PuwbV2CW5IZddbjWqkIHAzZubGAOroOH+nEFKbrqhnDuoO0Q4lf6v3PpUgkWRuRZTJCfQe1xhB2WNyE/5T5k8CpNCn0cK/aUiUPh7MeaSTCof/hSPfjP2JmzzbJDLRcqHQMr6t2GllSNa8DW2g= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: , , , , , CC: Subject: [PATCH v3 1/3] docs: Introduce Fusa Requirement and define maintainers Date: Tue, 6 Aug 2024 17:31:55 +0100 Message-ID: <20240806163157.2850636-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240806163157.2850636-1-ayan.kumar.halder@amd.com> References: <20240806163157.2850636-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|PH8PR12MB6940:EE_ X-MS-Office365-Filtering-Correlation-Id: 3a9e3cb0-ac9d-4028-2bad-08dcb635507e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: GcwRm+iTfn1qljqEvZS++wUDHHxSYUueDfjwfY8UvP1pNRQ71b/WmSfe1NaXU3X3AjGOtYiwpS8A37iL2OVJ05IdXrKvJQaNDn1UqHuy5MZ1HTfx2xSiB63F4bkUPuOdFh5dfRG/2uMRWvg5yUiHyqWtjIEd5gfAHi45r4c3Oih4dkcJ5IUsyHEykcIIHUDkiCWo4g2O4Zxe7/YTDwuDks5s2oFINtSGsIFIdqCA1b9KdwB6astNru4NiFg28M1qquCC6gnTKIr6N9djKWIiRP5ydNb37OylsreA4goKZKVvE30KSgUsFnPP1g/79cMlmdB6LCly14R0VQFx6UvHW0b+kgkuN9kXTK9cwLDqyWLIkAVOoVawTzOjr9rdP3i+ibYOX0zzCL6M83itMdHM6b+y/UcPodDWtebeMGHAxNhI0/o7Hukbc7vjX/si1kAxfEpuefGp5RNHJ3FHDK56tgUVlOT2waeY9nsUJz0f2JDf08iic5jo9wdheS399+deWfhbxnaIEPc6rOF2mmytX6Y2dmQBic7LHJ5y0nKtA6C+BDV2hWBvstH/0KNzvvR8qJ+cmL+51++I5HP3KblywQ9y+kJnvqD7P8Jl6EFE0Vv5sl0VPfuZtuV87iNmQmAmPXOAAHOi2JyUcDqXSWU9D0/85WH0MJzbneuZpq2tdwyvRD5/QbXPA/wOuuxLvMrIlINWs6mB/nkzcZAvTBKowTCrX9/pQARg5Mwet2duV+w0Oz73MpP5IuN+EMycFch3GUpQQeKqJrYVraZpp0a3SXDXYc53CHaMVrU3HlWp7bHBUTLX7gKk6uPh00oFJkmqmqBJ/p7OzQgRnurNgKAPcfAsxQoILIpLKUCBYx/oaH361vz2PRVx/W5vwPM2bsL/CrzYffqtYMAIRxH68ZE+jHQj3lO3872EFZpjpyOx60v33uRyeHUpvgUjm8Be9e24NkawWiy0XpRRbcNnmxdrJ7YUnigEIt2GWESy0qgeZzBVs4TdrbC34aLiWPp8B2JZWXVV4M9AezASijeegy9j0Ef+sQVWtQyRdCMNzHGqe0MBYoSuY9CgOQQdjDGcAc8VP/giKpE/ItC/bTON/Hqo+HvrPB0GT68O43f55EJaBssEqq6aaTBBnF548sisCCaT/Qc0ZGFcRNW6Krc2/xgz3cHO+HsuWZ7KZ3hoXYy8/jC9ZacMF4xk05588nTP2g83i3m0X3b3Ny4tFitMYitkEE0XJrfX/njGbjwNSap71mzDsZ30DbCT0brUbNB2pSe8+jdUR84frfhs1HwhU7hd5lRgJ78anR85dD8q2srNDQ9Ixf5/ZA35Y+AUr6PpJBCOfwAp16hlJ2kzyBQshfDDlfSE3GKXtyPNORNzC9ikIUND1sNzx0ePYOaCzaU5gsN5LDmBeivlLuohvYA0bYL4fQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 16:32:07.8954 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a9e3cb0-ac9d-4028-2bad-08dcb635507e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6940 The FUSA folder is expected to contain requirements and other documents to enable safety certification of Xen hypervisor. Added a intro to explain how the requirements are categorized, written and their supported status. Also, added index.rst for inclusion in build docs. Added maintainers for the same. Signed-off-by: Ayan Kumar Halder Acked-by: Bertrand Marquis Acked-by: Michal Orzel Reviewed-by: Stefano Stabellini Acked-by: Artem Mygaiev --- Changes from :- v1 - 1. Added a comment from Stefano. 2. Added Ack. v2 - 1. Renamed README to intro and changed the format from MD to RST (as the majority of files are in RST format and it gets picked during building of the docs). However, the actual contents hasn't changed so I am keeping the acks. 2. Added SPDX license identifier to the intro file. MAINTAINERS | 9 +++++ docs/fusa/index.rst | 9 +++++ docs/fusa/reqs/index.rst | 9 +++++ docs/fusa/reqs/intro.rst | 86 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 113 insertions(+) create mode 100644 docs/fusa/index.rst create mode 100644 docs/fusa/reqs/index.rst create mode 100644 docs/fusa/reqs/intro.rst diff --git a/MAINTAINERS b/MAINTAINERS index 7c524a8a93..0d328e065c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -314,6 +314,15 @@ F: xen/arch/x86/include/asm/x86_*/efi*.h F: xen/common/efi/ F: xen/include/efi/ +FUSA +M: Stefano Stabellini +M: Bertrand Marquis +M: Michal Orzel +M: Ayan Kumar Halder +M: Artem Mygaiev +S: Supported +F: docs/fusa/ + GDBSX DEBUGGER M: Elena Ufimtseva S: Supported diff --git a/docs/fusa/index.rst b/docs/fusa/index.rst new file mode 100644 index 0000000000..13bf4e8e23 --- /dev/null +++ b/docs/fusa/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Functional Safety documentation +=============================== + +.. toctree:: + :maxdepth: 2 + + reqs diff --git a/docs/fusa/reqs/index.rst b/docs/fusa/reqs/index.rst new file mode 100644 index 0000000000..78c02b1d9b --- /dev/null +++ b/docs/fusa/reqs/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Requirements documentation +========================== + +.. toctree:: + :maxdepth: 2 + + intro diff --git a/docs/fusa/reqs/intro.rst b/docs/fusa/reqs/intro.rst new file mode 100644 index 0000000000..d67b18dd9f --- /dev/null +++ b/docs/fusa/reqs/intro.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +################################## +Requirements Introduction Document +################################## + +This folder contains a set of requirements describing Xen and its implementation +in a form suitable for a safety certification process. + +The status is experimental and it is maintained on a best effort basis. The +requirements may get slightly out of sync with the code. We are actively working +on a process to keep them updated, more details to follow. + +The requirements writing style is inspired from the ANSI/IEEE guide to Software +Requirements Standard 830-1984. + +The requirements are categorized as follows :- + +1. Market requirements - They define the high level functionalities of the +hypervisor without going into concepts specific to Xen. Those should allow a +system architect to understand wether Xen is providing the functionalities it +needs for its system. This is the top level of the requirements. + +2. Product requirements - They define the Xen specific concepts and interfaces +provided by Xen without going into implementation details. One or several of +those requirements are linked to each market requirement. An Architect can use +them understand how Xen fulfils a market need and design how Xen should be used +in his system. + +3. Design requirements - They describe what the software implementation is doing +from a technical point of view. One or several design requirement together +define how product requirements are fulfilled technically and are linked to +them. An implementer can use them to know how to write or understand the Xen +code. + +The requirements are linked using OpenFastTrace +(https://github.com/itsallcode/openfasttrace/blob/main/doc/user_guide.md). +OpenFastTrace parses through the requirements and generates a traceability +report. + +The following is the skeleton for a requirement. + +Title of the requirement +======================== + +`unique_tag` + +.. + + Each requirement needs to have a unique tag associated. The format is + req_type~name~revision. + + Thus, it consists of three components :- + requirement type - This denotes the category of requirement. Thus, it shall + be 'XenMkt', 'XenProd' or 'XenSwdgn' to denote market, product or design + requirement. + name - This denotes name of the requirement. In case of architecture specific + requirements, this starts with the architecture type (ie x86_64, arm64). + revision number - This gets incremented each time the requirement is modified. + + +Description: +This shall describe the requirement in a definitive tone. In other words, +the requirement begins with 'Xen shall ...'. Further, the description is +expected to be unambiguous and consistent. + +Rationale: +This describes a rationale explaining the reason of the presence of the +requirement when this can help the reader. This field can be left blank. + +Comments: +This describes the use cases for the requirement when this can help the +reader. This field can be left blank as well. + +Covers: +This denotes the unique_tag of the parent. This field is non existent for the +market requirement as it is the top level. + +Needs: +This denotes the requirement type of its children. This field is non existent +for the design requirements as there are no subsequent requirements linked to +them. + + +The requirements are expected to the technically correct and follow the above +guidelines. From patchwork Tue Aug 6 16:31:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13755100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3930C52D71 for ; Tue, 6 Aug 2024 16:32:33 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.772953.1183406 (Exim 4.92) (envelope-from ) id 1sbN6h-0006OI-Oz; Tue, 06 Aug 2024 16:32:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 772953.1183406; Tue, 06 Aug 2024 16:32:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sbN6h-0006OB-MI; Tue, 06 Aug 2024 16:32:19 +0000 Received: by outflank-mailman (input) for mailman id 772953; Tue, 06 Aug 2024 16:32:18 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sbN6f-0005tQ-Vg for xen-devel@lists.xenproject.org; Tue, 06 Aug 2024 16:32:17 +0000 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2060e.outbound.protection.outlook.com [2a01:111:f403:2418::60e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 70ca58e3-5411-11ef-8776-851b0ebba9a2; Tue, 06 Aug 2024 18:32:16 +0200 (CEST) Received: from SN7PR04CA0093.namprd04.prod.outlook.com (2603:10b6:806:122::8) by LV3PR12MB9188.namprd12.prod.outlook.com (2603:10b6:408:19b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.27; Tue, 6 Aug 2024 16:32:09 +0000 Received: from SN1PEPF0002636D.namprd02.prod.outlook.com (2603:10b6:806:122:cafe::f1) by SN7PR04CA0093.outlook.office365.com (2603:10b6:806:122::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.22 via Frontend Transport; Tue, 6 Aug 2024 16:32:09 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SN1PEPF0002636D.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7828.19 via Frontend Transport; Tue, 6 Aug 2024 16:32:09 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 6 Aug 2024 11:32:08 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Tue, 6 Aug 2024 11:32:07 -0500 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 70ca58e3-5411-11ef-8776-851b0ebba9a2 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nUiPdNjtq71VDGuDDiFw/uDIoHEWHLezKBWhbj+ZjNs/TSe5St03Jzkm56pks+ApOFJSIfPpcsIUtTPPwBlYXY4RqTdvxSpQxTEKNgM1Bb0f83GRlX5SrJ5t3WqzlRyVZ9b8+k0ucn8rDoxfM8dCrfufj/B/fkcf08D/dt9ydF8jJK+e6c1ZzxZPmsabOqpqxrbb7+K00ZLLKrH4DvkYk7MZZ4sC0Cd6Fu2pC7tJ0Oek5Af2K456uQ1cdB7IFo5A4BgVbwMp5yIhgjmcrEiuVI/Po+ER8CKYtaA/TMYqV3BAnYftYh42TsYJkzVp5ry+g8IqLqMG7RsbfMRt6PVnyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nG75xyPT6ImZGBvR/mVd+v4hrOggcpDGgSesNfGn4jU=; b=jbqmNhiUY6SqwWYXeuvnF2rrQrTXVJgfgS67FV4Ndj5HDwMFYATiuaQJ62Qt6AM7yD18bnDZeeQ8cJdtcSEy6o4+4LewoYM2I1fX/r8RhiPUxhkacIYl044Mzud5sWgaaAnyyWbXLTEgLQpckAWiGcb6EYryjYeojEPu6aSYkJw/cEuKtnWWu0SC9NTqAsV53pcQ4/FTEocQI4JO56J9CNrTGOvNogqIf/UZ2FQ7ZqR9KYuzJdxGm4hagndTv/JscF8RqPBtn6W+ceowu2HMBJQUK0IVa0PjVLKj3TUPRWVUijk07ozPsFpU9fpbTGmiLIwxamZ38ilU2x8XQ53VIw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nG75xyPT6ImZGBvR/mVd+v4hrOggcpDGgSesNfGn4jU=; b=B9RKplne18juSTA3X6bV9RMQNi7GIZIonRuHO0xdyJfH5LG+aXR0DlPImQhdllPZkqWUImJo1lX9bSaSRjGeSaiXnZaLzHqOnSDMxBdewo11v0wDUhcxvgWlYxDtdAlReUmCC6dBc9JlmFZbgPW+on5PzlIU9XLaACZ0K7QVJDk= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: , , , , , CC: Subject: [PATCH v3 2/3] docs: fusa: reqs: Added a requirements writing style guide Date: Tue, 6 Aug 2024 17:31:56 +0100 Message-ID: <20240806163157.2850636-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240806163157.2850636-1-ayan.kumar.halder@amd.com> References: <20240806163157.2850636-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|LV3PR12MB9188:EE_ X-MS-Office365-Filtering-Correlation-Id: 8501c3c9-f32c-46ad-c0c1-08dcb6355135 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: 7BhZAtE0jRUpJrZqOzjriDctfDxJk25HMrrr/0FOaPMjkb4Rj0wqAiKORAuPr3dy16zGgvtOXyuIZxf85z+sGDTAroVXqG5QxYiB9EPw1fsSbK/AFshutHl6Zo63J2mOyKaq1zOYfV2B58WZdH/C61Vc9LTzyXxjhXNO+ZkJtPyZxley94YpFVfmmtqR53CtDLSjms+iknUqqZQeVMvKKP7L+om6hf2Up8kPkcg7bfpSR1TE7PBWYz4bWVNtc3NArYBN4CTXsd/9fg+AcTelc/DFG5ZNldhdF9x8oT5fdcEcRlGo32zhEuGI5fEsK3SlL/rAav0n4XoGDA3YdXzpjsjQQsyg3WyyxT4ARV2xJyLErmUiZFY4GMfTWqfD2yqThve+Su6uV7fyCHWYw24I32MDWGuptAl0sYyDH8PVkgOvQOhYDsfTHtNVwQ2pPE7ARoPbEWOacOd5oGgb0gn9W/rFSLExoB7QgV+oe/2oNK8wBLbNwCvoVg1RTsl1uBYB9xZ0FK54nZxKCPbGUmXVD2v56AMk77MSVoNVJVVff3/6EdBWpcby26/ZEV66T4yNBgicyIAe4O9isJNIaxeuWUwDx+HJd+cDb6jqp5mKWX+ZwG7445CX1ZTC0HOXqQ/FCdRh0r78dKlzU4mYDViGfMuOpCnW2M36CPxFyOkaWaqkTyAQaIRUmezZlQahP4z42Es/uT7L/DJMueJ/DXIox5rsczDHPV3Ad76ICg679tZuHy3WNT8PGtA7L0hIRyCpnzQ00pA2/hPT21Cq66VfJ37iYs70K4Avl0cnMcprBdn/NqjWJMpv4qKVeUSha186aSDwS86PwevIpid4keUVYH2D+GFaeKd6SvLTxmb0UNvYshIjdonGSOu5HHWu6CZrsOncAOs1rluY6BB5ijvbLvRNGIWrFLemq0v27ndpLnw5VjjjF9QQrbcE5m7snJq+CYuRsPLQQ+Zb9tbaGJWyXMzfDuaBBazJJ1D8OMjXRUSy0hMZ0wAHbxkJ/9uru+abODo0LjyKtkORqKB3b3etZZOeKE/E4Z7AUdsaDEW2rOnWp0ocSNL2g8fDhKOxo/oa9v4eBT7818HmzXYBg2SAZxzpIwTGDwTbLruPNqEktOnaVs9fP2AFkNNsVm3HVd969ya9hCsZ7y37ruQKtvszYueMM2JwLF/7OhsvBLNWKDbHpFsNJcwDHDynB+YRtD7OS31cWKUo+OLxUtrlTVL+bszfdTgfvwEK5pkDMpVBodcSbBS3Ckb5QpjdmOoPRv67sfqW9DMW9oclLhbSQmFSbwgHTl5E6e/YP6hOJ3oy/YSODfpdQsZZraeUGfQufBrrkzqQR7Jmrf/e8FlREBiTXy2mi0QnQm2OD34XDSAC/zraJV/U6k+ZVMGr3K2+zZDZ//p5kjnywZaOtQOSyGI6CYTuWN9jcCMmCZtbrj2t3x69Yljy9dwpfzrXPG0CY+OX X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 16:32:09.0985 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8501c3c9-f32c-46ad-c0c1-08dcb6355135 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9188 Added a guide to help write and review requirements. The requirements are written to enable safety certification of Xen hypervisor. Signed-off-by: Ayan Kumar Halder Acked-by: Bertrand Marquis --- Changes from - v1, v2 - No changes. docs/fusa/reqs/REQUIREMENTS-STYLE | 34 +++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 docs/fusa/reqs/REQUIREMENTS-STYLE diff --git a/docs/fusa/reqs/REQUIREMENTS-STYLE b/docs/fusa/reqs/REQUIREMENTS-STYLE new file mode 100644 index 0000000000..cd2408b9f2 --- /dev/null +++ b/docs/fusa/reqs/REQUIREMENTS-STYLE @@ -0,0 +1,34 @@ +Requirements writing style for the Xen Hypervisor +================================================= + +The requirements writing style described below is the style used for writing the +requirements of the Xen hypervisor to enable functional safety certification. + +The requirements writing style is inspired from the ANSI/IEEE guide to Software +Requirements Standard. Specifically, the requirements should satisfy the +following validation checklist. +(Source - https://www.nasa.gov/reference/appendix-c-how-to-write-a-good-requirement) + +Clarity - +The requirements should be clear, unambiguous, consise and simple. Each +requirement should express a single thought. Each requirement stated should have +a single interpretation. + +Consistency - +Any requirement shouldn't contradict with any other requirement. The requirements +should be categorized correctly (the categories have been explained in the +README). The tone of each requirement should be definitive (ie "Xen shall ..." +should be present in each requirement). + +Traceability - +Any market requirement should be linked to the product requirement/s and +vice versa. Any product requirement should be linked to the design requirement/s +and vice versa. Full bi-directional traceability should be maintained between +market, product and design requirements. + +Correctness - +The requirements should be feasible and technically correct (at the time of +writing). However, it is not expected that the requirements will be kept upto +date with the code. + +The requirements follow the same license and line length as the code. From patchwork Tue Aug 6 16:31:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13755103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84D3FC52D73 for ; Tue, 6 Aug 2024 16:32:37 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.772954.1183417 (Exim 4.92) (envelope-from ) id 1sbN6l-0006fd-5f; Tue, 06 Aug 2024 16:32:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 772954.1183417; Tue, 06 Aug 2024 16:32:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sbN6l-0006fU-2P; Tue, 06 Aug 2024 16:32:23 +0000 Received: by outflank-mailman (input) for mailman id 772954; Tue, 06 Aug 2024 16:32:21 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sbN6j-0006ds-Gy for xen-devel@lists.xenproject.org; Tue, 06 Aug 2024 16:32:21 +0000 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on20623.outbound.protection.outlook.com [2a01:111:f403:2412::623]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 728445f0-5411-11ef-bc04-fd08da9f4363; Tue, 06 Aug 2024 18:32:19 +0200 (CEST) Received: from SN7PR04CA0108.namprd04.prod.outlook.com (2603:10b6:806:122::23) by IA0PR12MB8256.namprd12.prod.outlook.com (2603:10b6:208:407::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.26; Tue, 6 Aug 2024 16:32:12 +0000 Received: from SN1PEPF0002636D.namprd02.prod.outlook.com (2603:10b6:806:122:cafe::1a) by SN7PR04CA0108.outlook.office365.com (2603:10b6:806:122::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.23 via Frontend Transport; Tue, 6 Aug 2024 16:32:11 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SN1PEPF0002636D.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7828.19 via Frontend Transport; Tue, 6 Aug 2024 16:32:11 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 6 Aug 2024 11:32:10 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Tue, 6 Aug 2024 11:32:09 -0500 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 728445f0-5411-11ef-bc04-fd08da9f4363 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=etdKK395KNo7Yq06oURYqjTqkV/eX5eIJPo3+JD6QPs10VlBNEqCXnLTnJcQG7i52FHMIXH2yIygG25r3Q5rAMHr99Y0Rnl8o2vMjSYlLoFTcVhpr6XiR1yfmvrOWj8SS9CR/TTqDO622DA4EwS4QXa0jmNoPkU93h2VWRsnQsGzv+XNSZjr3+V8eVrO2WmiAtCtzcOvqu/QCFxDTPy4vK+kqXcvjCn3akrZGaOoMVchwqDMaJi9bobFrwBDQrCwraxdiAgmeJoRHr7ya7ZuTRi9jB7P2+T64y0iOSOeGWr9Cqml2Mdgga/DeYEaMTbbV7aVQYb7mv5B26NiFFmqkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Ro4RCdbeVMPWPxCUKX0Z9qQcm5SjMsD0JCUP7059ZMU=; b=xwXxu9CqW1nRXM01pvOPOHo2dtiKC3MfApNv5o8oO4WnS2hIfexmbPIkRCAUophF3+6AjHgDWgB6EU2hKkGBhdfmp+m9/wkt+AGFZ0ovQSLGLOSLHa/SfBB34Pt5CbfArnlfmYlsdrtYWfwK7hJA+OTibbqd9/2jemIquvUbYKmX2HMCLlnnBg9T/ukKX7C8FITLNUfJaaKfzJT/IeP9dy6oTsBQ7Z84RoM5HqEtcbc8XhmzEd8IBO7zqmx6v2+ljh3CEzH2FiJm4KHpDUGN6RkzqULfXW0drxVcTvSbNL8Flys85TwrUSXZhY8sBDA7mZJAB2j5U4QTEFwOgEm4yQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Ro4RCdbeVMPWPxCUKX0Z9qQcm5SjMsD0JCUP7059ZMU=; b=rTISSYUzgj5wSCl3sflUjwFBhlSXoxpUHrblcjAdCM0CeDinSKAIXlY/giWL+pTgkVVL8AhmpIyy91X987WVecVExU/Nc97Yk77VM2osFxmF172iybjeAltkPPnS0X7Pp1L1z3ntTgjzH5kInUA2MOXpEDMgQ/k+vZvlvqjN1Ic= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: , , , , , CC: Subject: [PATCH v3 3/3] docs: fusa : reqs: Added a sample of requirements [DO_NOT_MERGE] Date: Tue, 6 Aug 2024 17:31:57 +0100 Message-ID: <20240806163157.2850636-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240806163157.2850636-1-ayan.kumar.halder@amd.com> References: <20240806163157.2850636-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|IA0PR12MB8256:EE_ X-MS-Office365-Filtering-Correlation-Id: 71aa3aa4-1df0-4934-c161-08dcb63552db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: NFs7yay+imCQ6Os/a4YaIc4qLiiA08yQ+OJFYK+5j6a2o6ZogB2Fz129vtEwvgisnjyzvKUUkbJS6mtlra+eqSC7w4GvBGuuqf3Lio8qFO8edVWLhJhL1goMJp0CW23HDbz3IfwYqMC4eO5rrr4ZLnl5ApHUeyJ/0eWtl0juPgV4vx4Ffof/ZZy+paVgYSCxBc/D3o+FJEM0Yw24SdV1proSBxvaK2QouajwUHs4WjFUsYs4RgDOScbbDFAas9KZWmwjT/kA1bB8JJgmp+dsrdzzOfMjk0NKo8hrR6Elcqb4ErOVfqNK5AjTGWk/By/BNPZvBRRjLMzfz7Tdpn/E0Rbs9S5D2govzhpqBkoFrDu1eb2Qtl39GvH2M2poifA/+eqo2k9tpXrX+j13W+zCOMyqu7mBzJ1yldJDyRrBXPhvAApDpBO5RhlF8yrYDwBx0MTstd9j2nND26ju9G0HHzakgdQ10JaWoVnHPCE17TGWuPiePvniSqm6Wxr60pIANqnF3Po/xfoD7i1ScQX4ssiGjqTKTI3diJHWUCuBljaz3H08zbTHXi6/jdW9CcCtb0+EdR6QHPuuPm7os1Q2gp15aDd9NgSbtYZ9WdgoeZBQKmytox5F2+hSvH2rw0U6grvEN/wkWZ8utiIBQ6+SdCbv2K3F/hFbRZs8a2upqkpnuC19V1Hb0TyYsvO9RS7zvrb10/hY1sCrgqwizKe5RJu8eM3AD9fklCSZyXbZ7D3egTqF4cX7rqZvG0KRKxj0zEMlAtX7dVJkA738t4MBrIBUnHuaiNyme+ImziN9cZeNXJVpag4cZ4zlWsGi1lQM2JlC7R19X40nk22hbCXpA0UXXZD033/o6imeSuEhRgKTSM0MsOcE4NY+bi7l4gXgLcMy6fmvfqu1SfBsGCHWGJpInMPEiA9reggQimM5VlYXnMr1HqtLWpm5zu7zt8v+LrTBkQeKq8BxWzr7PFQWGQTinIZJtPsiVH98NeFpyFkjM/AEf9d2jXmo+U2xbfEm2xyILCagSSjfYRopBaTbhHsDOgmrvZuWVfGmXQXeh4d5L4mQVKdEnTgo6UBMWYLU+CDm8eWQWRX5EzDkNhz3RUPMmY9e1PVXjgRUPvS6j+xXMchB20YZYCijyeB2ORV83F4Ca3T9NFlvbX2c98g24Ab9g6mypYsEMAg3XMn16OTpok2iI/HQ0LDTt75KEEHNTriMikFof7ui3AltViXZUGpbAoAtmhA3xOHakUHWI6ifPLBgCTfgka5t35CgLLar7zLbTfKpB8JvBKEW1iEPKdAu3BiDq67n9R6qET03T5sXqsMc1A7c/TjlQ4yp4VVbRIZKC2eojkFUOTrpPlqj6Acy/7iwMHRrBB4o8vc+gxJg7i0NNsGDoo9j42qSsp9l X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 16:32:11.8485 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71aa3aa4-1df0-4934-c161-08dcb63552db X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8256 Added a sample of market, product and design requirements. This is to help explain how we are writing the requirements and understand the context of the first patch. We will be sending these requirements for review in the subsequent patches. Please do not merge this patch. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1, v2 - No changes. .../reqs/design-reqs/arm64/emulated-uart.rst | 240 ++++++++++++++++++ .../reqs/design-reqs/arm64/generic-timer.rst | 146 +++++++++++ docs/fusa/reqs/design-reqs/xen-version.rst | 207 +++++++++++++++ docs/fusa/reqs/market-reqs/reqs.rst | 77 ++++++ docs/fusa/reqs/product-reqs/reqs.rst | 64 +++++ 5 files changed, 734 insertions(+) create mode 100644 docs/fusa/reqs/design-reqs/arm64/emulated-uart.rst create mode 100644 docs/fusa/reqs/design-reqs/arm64/generic-timer.rst create mode 100644 docs/fusa/reqs/design-reqs/xen-version.rst create mode 100644 docs/fusa/reqs/market-reqs/reqs.rst create mode 100644 docs/fusa/reqs/product-reqs/reqs.rst diff --git a/docs/fusa/reqs/design-reqs/arm64/emulated-uart.rst b/docs/fusa/reqs/design-reqs/arm64/emulated-uart.rst new file mode 100644 index 0000000000..483db92fa8 --- /dev/null +++ b/docs/fusa/reqs/design-reqs/arm64/emulated-uart.rst @@ -0,0 +1,240 @@ +UART +==== + +The following are the requirements related to SBSA UART [1] emulated and +exposed by Xen to Arm64 domains. + +Probe the UART device tree node +------------------------------- + +`XenSwdgn~arm64_uart_probe_dt_node~1` + +Description: +Xen shall generate a device tree node for the SBSA UART (in accordance to Arm +SBSA UART device tree binding [2]) to allow domains to probe it. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Transmit data in software polling mode +-------------------------------------- + +`XenSwdgn~arm64_uart_transmit_data_poll_mode~1` + +Description: +Domain shall transmit data in polling mode (i.e. without involving interrupts). + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Transmit data in interrupt driven mode +-------------------------------------- + +`XenSwdgn~arm64_uart_transmit_data_irq_mode~1` + +Description: +Domain shall transmit data in interrupt driven mode. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Receive data in software polling mode +------------------------------------- + +`XenSwdgn~arm64_uart_receive_data_polling_mode~1` + +Description: +Domain shall receive data in polling mode (i.e. without involving interrupts). + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Receive data in interrupt driven mode +------------------------------------- + +`XenSwdgn~arm64_uart_receive_data_interrupt_driven_mode~1` + +Description: +Domain shall receive data in interrupt driven mode. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Access UART data register +------------------------- + +`XenSwdgn~arm64_uart_access_data_register~1` + +Description: +Domain shall access (read/write) UART data register. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Access UART receive status register +----------------------------------- + +`XenSwdgn~arm64_uart_access_receive_status_register~1` + +Description: +Domain shall access (read/write) UART receive status register. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Access UART flag register +------------------------- + +`XenSwdgn~arm64_uart_access_flag_register~1` + +Description: +Domain shall access (read only) UART flag register. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Access UART mask set/clear register +----------------------------------- + +`XenSwdgn~arm64_uart_access_mask_register~1` + +Description: +Domain shall access (read/write) UART mask set/clear register. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Access UART raw interrupt status register +----------------------------------------- + +`XenSwdgn~arm64_uart_access_raw_interrupt_status_register~1` + +Description: +Domain shall access (read only) UART raw interrupt status register. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Access UART masked interrupt status register +-------------------------------------------- + +`XenSwdgn~arm64_uart_access_mask_irq_status_register~1` + +Description: +Domain shall access (read only) UART masked interrupt status register. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Access UART interrupt clear register +------------------------------------ + +`XenSwdgn~arm64_uart_access_irq_clear_register~1` + +Description: +Domain shall access (write only) UART interrupt clear register. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Receive UART TX interrupt +------------------------- + +`XenSwdgn~arm64_uart_receive_tx_irq~1` + +Description: +Domain shall receive UART TX interrupt + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Receive UART RX interrupt reception +----------------------------------- + +`XenSwdgn~arm64_uart_receive_rx_irq~1` + +Description: +Domain shall receive UART RX interrupt + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +Initial State +============= + +Access UART in an initial (reset) state +--------------------------------------- + +`XenSwdgn~arm64_uart_access_reset_state~1` + +Description: +Domain shall be given the access to the UART in a state, where all registers +hold the reset value according to the specification [3] (only for registers +implemented as part of SBSA UART). + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_uart~1` + +| [1] Arm Base System Architecture, chapter B +| [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt +| [3] PrimeCell UART (PL011) diff --git a/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst b/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst new file mode 100644 index 0000000000..00228448a3 --- /dev/null +++ b/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst @@ -0,0 +1,146 @@ +Generic Timer +============= + +The following are the requirements related to ARM Generic Timer [1] interface +exposed by Xen to Arm64 domains. + +Probe the Generic Timer device tree node from a domain +------------------------------------------------------ + +`XenSwdgn~arm64_probe_generic_timer_dt~1` + +Description: +Xen shall generate a device tree node for the Generic Timer (in accordance to +ARM architected timer device tree binding [2]) to allow domains to probe it. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_timer~1` + +Read system counter frequency +----------------------------- + +`XenSwdgn~arm64_read_system_counter_freq~1` + +Description: +Domain shall read the frequency of the system counter (either via CNTFRQ_EL0 +register or "clock-frequency" device tree property if present). + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_timer~1` + +Access CNTKCTL_EL1 system register from a domain +------------------------------------------------ + +`XenSwdgn~arm64_access_cntkctl_el1_system_register~1` + +Description: +Domain shall access the counter-timer kernel control register to allow +controlling the access to the timer from userspace (EL0). + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_timer~1` + +Access virtual timer from a domain +---------------------------------- + +`XenSwdgn~arm64_access_virtual_timer~1` + +Description: +Domain shall access and make use of the virtual timer by accessing the following +system registers: +CNTVCT_EL0, +CNTV_CTL_EL0, +CNTV_CVAL_EL0, +CNTV_TVAL_EL0. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_timer~1` + +Access physical timer from a domain +----------------------------------- + +`XenSwdgn~arm64_access_physical_timer~1` + +Description: +Domain shall access and make use of the physical timer by accessing the +following system registers: +CNTPCT_EL0, +CNTP_CTL_EL0, +CNTP_CVAL_EL0, +CNTP_TVAL_EL0. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_timer~1` + +Trigger the virtual timer interrupt from a domain +------------------------------------------------- + +`XenSwdgn~arm64_trigger_virtual_timer_interrupt~1` + +Description: +Domain shall program the virtual timer to generate the interrupt when the +asserted condition is met. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_timer~1` + +Trigger the physical timer interrupt from a domain +-------------------------------------------------- + +`XenSwdgn~arm64_trigger_physical_timer_interrupt~1` + +Description: +Domain shall program the physical timer to generate the interrupt when the +asserted condition is met. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_timer~1` + +Assumption of Use on the Firmware +================================= + +Expose system timer frequency +----------------------------- + +`XenSwdgn~arm64_program_cntfrq_el0_or_dt_prop_system_timer_freq~1` + +Description: +Underlying firmware shall program CNTFRQ_EL0 with the system timer frequency. +As an alternative, "clock-frequency" dt property (in the host device tree) can +also be used to specify the system timer frequency. This helps in case of buggy +firmware when CNTFRQ_EL0 is programmed incorrectly or not programmed at all. + +Rationale: + +Comments: + +Covers: + - `XenProd~emulated_timer~1` diff --git a/docs/fusa/reqs/design-reqs/xen-version.rst b/docs/fusa/reqs/design-reqs/xen-version.rst new file mode 100644 index 0000000000..c5c58bb2df --- /dev/null +++ b/docs/fusa/reqs/design-reqs/xen-version.rst @@ -0,0 +1,207 @@ +Hypercall xen_version +===================== + +The following are the requirements related to __HYPERVISOR_xen_version hypercall +[1] exposed by Xen to Arm64 and AMD64 PVH domains. + +Access hypercall __HYPERVISOR_xen_version for getting xen version +----------------------------------------------------------------- + +`XenSwdgn~access_hyp_xen_version_read_ver~1` + +Description: +Domain shall access __HYPERVISOR_xen_version passing XENVER_version +as a command. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Validate the xen version returned by the XENVER_version command +--------------------------------------------------------------- + +`XenSwdgn~validate_version_hyp_xen_version~1` + +Description: +The xen version returned should correspond to 4.18. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Access hypercall __HYPERVISOR_xen_version for getting xen extraversion +---------------------------------------------------------------------- + +`XenSwdgn~access_hyp_xen_version_get_extraversion~1` + +Description: +Domain shall access __HYPERVISOR_xen_version passing XENVER_extraversion as a +command. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Access hypercall __HYPERVISOR_xen_version for getting compile information +------------------------------------------------------------------------- + +`XenSwdgn~access_hyp_xen_version_get_compile_info~1` + +Description: +Domain shall access __HYPERVISOR_xen_version passing XENVER_compile_info as a +command. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Access hypercall __HYPERVISOR_xen_version for getting capabilities +------------------------------------------------------------------ + +`XenSwdgn~access_hyp_xen_version_get_capabilities~1` + +Description: +Domain shall access __HYPERVISOR_xen_version passing XENVER_capabilities as a +command. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Validate the capabilities returned by XENVER_capabilities command +----------------------------------------------------------------- + +`XenSwdgn~validate_cap_return_xenver_capabilities~1` + +Description: +For Arm64, the capabilities returned should be xen-*-aarch64 string. +For AMD64 PVH, the capabilities returned should be hvm-*-x86_64 string. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Access hypercall __HYPERVISOR_xen_version for getting changeset +--------------------------------------------------------------- + +`XenSwdgn~access_hyp_xen_version_get_changeset~1` + +Description: +Domain shall access __HYPERVISOR_xen_version passing XENVER_changeset +as a command. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Access hypercall __HYPERVISOR_xen_version for getting features +-------------------------------------------------------------- + +`XenSwdgn~access_hyp_xen_version_get_features~1` + +Description: +Domain shall access __HYPERVISOR_xen_version passing XENVER_get_features as a +command. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Check supported features returned by the XENVER_get_features command when the submap index passed is 0 +------------------------------------------------------------------------------------------------------ + +`XenSwdgn~check_supported_features_xenver_get_features~1` + +Description: +For Arm64, the bit position corresponding to the supported features should be 1. +Examples of Arm64 supported features: + + * XENFEAT_ARM_SMCCC_supported + +For AMD64 PVH, the bit positions corresponding to the supported features should +be 1. +Examples of AMD64 PVH supported features: + + * XENFEAT_memory_op_vnode_supported + * XENFEAT_vcpu_time_phys_area + * XENFEAT_runstate_phys_area + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Access hypercall __HYPERVISOR_xen_version for getting guest handle +------------------------------------------------------------------ + +`XenSwdgn~access_hyp_xen_version_get_guest_handle~1` + +Description: +Domain shall access __HYPERVISOR_xen_version passing XENVER_guest_handle as a +command. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Access hypercall __HYPERVISOR_xen_version for getting xen pagesize +------------------------------------------------------------------ + +`XenSwdgn~access_hyp_xen_version_get_xen_pagesize~1` + +Description: +Domain shall access __HYPERVISOR_xen_version passing XENVER_pagesize +as a command and NULL as the guest handle. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +Validate the page size returned by XENVER_pagesize command +---------------------------------------------------------- + +`XenSwdgn~validate_page_size_xenver_pagesize_cmd~1` + +Description: +The returned page size should be 4KB. + +Rationale: + +Comments: + +Covers: + - `XenProd~version_hypercall~1` + +| [1] https://xenbits.xenproject.org/gitweb/?p=xen.git;a=blob;f=xen/include/public/version.h;hb=HEAD diff --git a/docs/fusa/reqs/market-reqs/reqs.rst b/docs/fusa/reqs/market-reqs/reqs.rst new file mode 100644 index 0000000000..a3f84cd503 --- /dev/null +++ b/docs/fusa/reqs/market-reqs/reqs.rst @@ -0,0 +1,77 @@ +Functional Requirements +======================= + +Run Arm64 VMs +------------- + +`XenMkt~run_arm64_vms~1` + +Description: +Xen shall run Arm64 VMs. + +Rationale: + +Comments: + +Needs: + - XenProd + +Run AMD-x86 VMs +--------------- + +`XenMkt~run_x86_vms~1` + +Description: +Xen shall run AMD-x86 VMs. + +Rationale: + +Comments: + +Needs: + - XenProd + +Support non paravirtualised VMs +------------------------------- + +`XenMkt~non_pv_vms_support~1` + +Description: +Xen shall support running guests which are not virtualisation aware. + +Rationale: + +Comments: + +Needs: + - XenProd + +Provide console to the VMs +-------------------------- + +`XenMkt~provide_console_vms~1` + +Description: +Xen shall provide a console to a VM. + +Rationale: + +Comments: + +Needs: + - XenProd + +Provide timer to the VMs +------------------------ + +`XenMkt~provide_timer_vms~1` + +Description: +Xen shall provide a timer to a VM. + +Rationale: + +Comments: + +Needs: + - XenProd diff --git a/docs/fusa/reqs/product-reqs/reqs.rst b/docs/fusa/reqs/product-reqs/reqs.rst new file mode 100644 index 0000000000..9954b7532a --- /dev/null +++ b/docs/fusa/reqs/product-reqs/reqs.rst @@ -0,0 +1,64 @@ +Domain Creation And Runtime +=========================== + +Emulated UART +------------- + +`XenProd~emulated_uart~1` + +Description: +Xen shall emulate Arm SBSA UART on behalf of the domains. + +Rationale: + +Comments: +The domains can use it to write/read to/from the console. + +Covers: + - `XenMkt~run_arm64_vms~1` + - `XenMkt~non_pv_vms_support~1` + - `XenMkt~provide_console_vms~1` + +Needs: + - XenSwdgn + +Emulated Timer +-------------- + +`XenProd~emulated_timer~1` + +Description: +Xen shall emulate Arm Generic Timer timer on behalf of domains. + +Rationale: + +Comments: +The domains can use it for e.g. scheduling. + +Covers: + - `XenMkt~run_arm64_vms~1` + - `XenMkt~non_pv_vms_support~1` + - `XenMkt~provide_timer_vms~1` + +Needs: + - XenSwdgn + +Version Hypercall +----------------- + +`XenProd~version_hypercall~1` + +Description: +Xen shall provide an interface to expose Xen version, type and compile +information. + +Rationale: + +Comments: + +Covers: + - `XenMkt~run_arm64_vms~1` + - `XenMkt~run_x86_vms~1` + +Needs: + - XenSwdgn