From patchwork Wed Aug 7 00:30:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris H X-Patchwork-Id: 13755568 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D30D81DDEB for ; Wed, 7 Aug 2024 00:36:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722991010; cv=none; b=dfqELMo12SpNtEeX5EqPnhLPgdDPmY5qCim3/Fi4Bs2F1nQWHiXmVQux8dq+0NtTeoekA3/NMcAcHuB/oNHaIWmJtXx0Rjn/pjPrdxZcWzBEnSAXXNpUaOG4YIQgk94902PGaHbSBKDsbsblbtcI27sXJpqfMNgvRlvo3IpEUOc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722991010; c=relaxed/simple; bh=8WR6VOKinrRYanLaA5NwZ8rozUY7FOgk66VVTRV++uw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=f5UO833J4Idv4V0xTSjVFF61B+HMLaLD8IW/tWiuRUnSnIZpHg0dw/xGEQsAsPRS4pXdQl7FIdoWGDt0Itf3c9ITGomfwWodCkxjZF8b/6ogv4FXEqOPrFh8O77zb/asQ17tX1YBnoMU2l/87c+xmUhCiFO1T5kEk4rFXXoHe+s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=k4ZdKTCj; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="k4ZdKTCj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722991009; x=1754527009; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8WR6VOKinrRYanLaA5NwZ8rozUY7FOgk66VVTRV++uw=; b=k4ZdKTCj5iWWF4lpUa6Y5jeQif9buL8jiGvJY/1mmHborHGpWL1COAAW rxCaPe/IaJuggmpDpw+nuVpbNp2+LNLTdAJJpQScFHAWDteQf1Yc90x3q lKFKs/WT+sZnxaw+ijQX8Y8O4KDWalemY5Yn0jRd4Nh+x8TH4TLtvmV9d fA8HR3u/jy4vSeIZbiUlQQui/vsBKVMi78hc3/k3FKdg9XyLLWOkcYruE da4ERChxIPZfe2xyBayImV5q9anDO9egIPHngivcUpfsDcl8e9iYWQ0/v V5qGT2GTqtLAYipzl3rS78keLL9Ct9tRtNTZUFWv7yPNhq3X45cF4gZpQ A==; X-CSE-ConnectionGUID: GNfRr3VST7a2Zj9K6rrreA== X-CSE-MsgGUID: vRjpF1yVQe+ro2QRPlpauA== X-IronPort-AV: E=McAfee;i="6700,10204,11156"; a="31669744" X-IronPort-AV: E=Sophos;i="6.09,268,1716274800"; d="scan'208";a="31669744" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2024 17:36:49 -0700 X-CSE-ConnectionGUID: YefdZEw/T4yTRd6p5xjdTQ== X-CSE-MsgGUID: xpfh385pRd+kEFufZ0BG3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,268,1716274800"; d="scan'208";a="61496999" Received: from timelab-spr09.ch.intel.com (HELO timelab-spr09.sc.intel.com) ([143.182.136.138]) by orviesa003.jf.intel.com with ESMTP; 06 Aug 2024 17:36:47 -0700 From: christopher.s.hall@intel.com To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, vinicius.gomes@intel.com, david.zage@intel.com, vinschen@redhat.com, rodrigo.cadore@l-acoustics.com, Christopher S M Hall , Michal Swiatkowski Subject: [PATCH iwl-net v1 1/5] igc: Ensure the PTM cycle is reliably triggered Date: Tue, 6 Aug 2024 17:30:28 -0700 Message-Id: <20240807003032.10300-2-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240807003032.10300-1-christopher.s.hall@intel.com> References: <20240807003032.10300-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Christopher S M Hall Writing to clear the PTM status 'valid' bit while the PTM cycle is triggered results in unreliable PTM operation. To fix this, clear the PTM 'trigger' and status after each PTM transaction. The issue can be reproduced with the following: $ sudo phc2sys -R 1000 -O 0 -i tsn0 -m Note: 1000 Hz (-R 1000) is unrealistically large, but provides a way to quickly reproduce the issue. PHC2SYS exits with: "ioctl PTP_OFFSET_PRECISE: Connection timed out" when the PTM transaction fails Fixes: a90ec8483732 ("igc: Add support for PTP getcrosststamp()") Signed-off-by: Christopher S M Hall Reviewed-by: Michal Swiatkowski Reviewed-by: Corinna Vinschen Tested-by: Corinna Vinschen (kdump hang only) --- drivers/net/ethernet/intel/igc/igc_defines.h | 1 + drivers/net/ethernet/intel/igc/igc_ptp.c | 70 ++++++++++++-------- 2 files changed, 42 insertions(+), 29 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h index 511384f3ec5c..ec191d26c650 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -583,6 +583,7 @@ #define IGC_PTM_STAT_T4M1_OVFL BIT(3) /* T4 minus T1 overflow */ #define IGC_PTM_STAT_ADJUST_1ST BIT(4) /* 1588 timer adjusted during 1st PTM cycle */ #define IGC_PTM_STAT_ADJUST_CYC BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */ +#define IGC_PTM_STAT_ALL GENMASK(5, 0) /* Used to clear all status */ /* PCIe PTM Cycle Control */ #define IGC_PTM_CYCLE_CTRL_CYC_TIME(msec) ((msec) & 0x3ff) /* PTM Cycle Time (msec) */ diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index 946edbad4302..00cc80d8d164 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -974,11 +974,38 @@ static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat) } } +static void igc_ptm_trigger(struct igc_hw *hw) +{ + u32 ctrl; + + /* To "manually" start the PTM cycle we need to set the + * trigger (TRIG) bit + */ + ctrl = rd32(IGC_PTM_CTRL); + ctrl |= IGC_PTM_CTRL_TRIG; + wr32(IGC_PTM_CTRL, ctrl); + /* Perform flush after write to CTRL register otherwise + * transaction may not start + */ + wrfl(); +} + +static void igc_ptm_reset(struct igc_hw *hw) +{ + u32 ctrl; + + ctrl = rd32(IGC_PTM_CTRL); + ctrl &= ~IGC_PTM_CTRL_TRIG; + wr32(IGC_PTM_CTRL, ctrl); + /* Write to clear all status */ + wr32(IGC_PTM_STAT, IGC_PTM_STAT_ALL); +} + static int igc_phc_get_syncdevicetime(ktime_t *device, struct system_counterval_t *system, void *ctx) { - u32 stat, t2_curr_h, t2_curr_l, ctrl; + u32 stat, t2_curr_h, t2_curr_l; struct igc_adapter *adapter = ctx; struct igc_hw *hw = &adapter->hw; int err, count = 100; @@ -994,25 +1021,13 @@ static int igc_phc_get_syncdevicetime(ktime_t *device, * are transitory. Repeating the process returns valid * data eventually. */ - - /* To "manually" start the PTM cycle we need to clear and - * then set again the TRIG bit. - */ - ctrl = rd32(IGC_PTM_CTRL); - ctrl &= ~IGC_PTM_CTRL_TRIG; - wr32(IGC_PTM_CTRL, ctrl); - ctrl |= IGC_PTM_CTRL_TRIG; - wr32(IGC_PTM_CTRL, ctrl); - - /* The cycle only starts "for real" when software notifies - * that it has read the registers, this is done by setting - * VALID bit. - */ - wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID); + igc_ptm_trigger(hw); err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat, stat, IGC_PTM_STAT_SLEEP, IGC_PTM_STAT_TIMEOUT); + igc_ptm_reset(hw); + if (err < 0) { netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n"); return err; @@ -1021,15 +1036,7 @@ static int igc_phc_get_syncdevicetime(ktime_t *device, if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID) break; - if (stat & ~IGC_PTM_STAT_VALID) { - /* An error occurred, log it. */ - igc_ptm_log_error(adapter, stat); - /* The STAT register is write-1-to-clear (W1C), - * so write the previous error status to clear it. - */ - wr32(IGC_PTM_STAT, stat); - continue; - } + igc_ptm_log_error(adapter, stat); } while (--count); if (!count) { @@ -1255,7 +1262,7 @@ void igc_ptp_stop(struct igc_adapter *adapter) void igc_ptp_reset(struct igc_adapter *adapter) { struct igc_hw *hw = &adapter->hw; - u32 cycle_ctrl, ctrl; + u32 cycle_ctrl, ctrl, stat; unsigned long flags; u32 timadj; @@ -1290,14 +1297,19 @@ void igc_ptp_reset(struct igc_adapter *adapter) ctrl = IGC_PTM_CTRL_EN | IGC_PTM_CTRL_START_NOW | IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) | - IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) | - IGC_PTM_CTRL_TRIG; + IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT); wr32(IGC_PTM_CTRL, ctrl); /* Force the first cycle to run. */ - wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID); + igc_ptm_trigger(hw); + + if (readx_poll_timeout_atomic(rd32, IGC_PTM_STAT, stat, + stat, IGC_PTM_STAT_SLEEP, + IGC_PTM_STAT_TIMEOUT)) + netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n"); + igc_ptm_reset(hw); break; default: /* No work to do. */ From patchwork Wed Aug 7 00:30:29 2024 Content-Type: text/plain; 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06 Aug 2024 17:36:52 -0700 From: christopher.s.hall@intel.com To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, vinicius.gomes@intel.com, david.zage@intel.com, vinschen@redhat.com, rodrigo.cadore@l-acoustics.com, Christopher S M Hall Subject: [PATCH iwl-net v1 2/5] igc: Lengthen the hardware retry time to prevent timeouts Date: Tue, 6 Aug 2024 17:30:29 -0700 Message-Id: <20240807003032.10300-3-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240807003032.10300-1-christopher.s.hall@intel.com> References: <20240807003032.10300-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Christopher S M Hall Lengthen the hardware retry timer to four microseconds. The i225/i226 hardware retries if it receives an inappropriate response from the upstream device. If the device retries too quickly, the root port does not respond. The issue can be reproduced with the following: $ sudo phc2sys -R 1000 -O 0 -i tsn0 -m Note: 1000 Hz (-R 1000) is unrealistically large, but provides a way to quickly reproduce the issue. PHC2SYS exits with: "ioctl PTP_OFFSET_PRECISE: Connection timed out" when the PTM transaction fails Fixes: 6b8aa753a9f9 ("igc: Decrease PTM short interval from 10 us to 1 us") Signed-off-by: Christopher S M Hall Reviewed-by: Corinna Vinschen --- drivers/net/ethernet/intel/igc/igc_defines.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h index ec191d26c650..253327c23903 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -564,7 +564,7 @@ #define IGC_PTM_CTRL_SHRT_CYC(usec) (((usec) & 0x3f) << 2) #define IGC_PTM_CTRL_PTM_TO(usec) (((usec) & 0xff) << 8) -#define IGC_PTM_SHORT_CYC_DEFAULT 1 /* Default short cycle interval */ +#define IGC_PTM_SHORT_CYC_DEFAULT 4 /* Default short cycle interval */ #define IGC_PTM_CYC_TIME_DEFAULT 5 /* Default PTM cycle time */ #define IGC_PTM_TIMEOUT_DEFAULT 255 /* Default timeout for PTM errors */ From patchwork Wed Aug 7 00:30:30 2024 Content-Type: text/plain; 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06 Aug 2024 17:36:54 -0700 From: christopher.s.hall@intel.com To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, vinicius.gomes@intel.com, david.zage@intel.com, vinschen@redhat.com, rodrigo.cadore@l-acoustics.com, Christopher S M Hall Subject: [PATCH iwl-net v1 3/5] igc: Move ktime snapshot into PTM retry loop Date: Tue, 6 Aug 2024 17:30:30 -0700 Message-Id: <20240807003032.10300-4-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240807003032.10300-1-christopher.s.hall@intel.com> References: <20240807003032.10300-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Christopher S M Hall Move ktime_get_snapshot() into the loop. If a retry does occur, a more recent snapshot will result in a more accurate cross-timestamp. Fixes: a90ec8483732 ("igc: Add support for PTP getcrosststamp()") Signed-off-by: Christopher S M Hall Reviewed-by: Corinna Vinschen --- drivers/net/ethernet/intel/igc/igc_ptp.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index 00cc80d8d164..fb885fcaa97c 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -1011,16 +1011,16 @@ static int igc_phc_get_syncdevicetime(ktime_t *device, int err, count = 100; ktime_t t1, t2_curr; - /* Get a snapshot of system clocks to use as historic value. */ - ktime_get_snapshot(&adapter->snapshot); - + /* Doing this in a loop because in the event of a + * badly timed (ha!) system clock adjustment, we may + * get PTM errors from the PCI root, but these errors + * are transitory. Repeating the process returns valid + * data eventually. + */ do { - /* Doing this in a loop because in the event of a - * badly timed (ha!) system clock adjustment, we may - * get PTM errors from the PCI root, but these errors - * are transitory. Repeating the process returns valid - * data eventually. - */ + /* Get a snapshot of system clocks to use as historic value. */ + ktime_get_snapshot(&adapter->snapshot); + igc_ptm_trigger(hw); err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat, From patchwork Wed Aug 7 00:30:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris H X-Patchwork-Id: 13755571 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 674F01DFFC for ; Wed, 7 Aug 2024 00:36:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722991018; cv=none; b=EzO/zXHGUnTBTuyn+2Wh9kbmFzj0dYmSi172H60iOjfqg6EkQPheCRX7ZcKyeh+5wNPkIzwFCm5Hr2y9rFKtazdfm03tjbGCJXL3HKu1AsJ4ryvWGecg+QjSAPIQEwEic6TbwHPSGS704dYW3/LPr5PPTWcoAAx0P7ed/Va3sLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722991018; c=relaxed/simple; bh=FWYbx309e0mOibK/0qkpc0jS+BP2N0k4amoXf/TFnH8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AcYXwsK07Q+YbWbxMRFpx88BJVjoHCsSQXgE3rfBS3NHlRf+yj24Ds50hGqYcjpsB/XZuZ0mwT1t5HSPEfQ0ECSQx76HfebZGhmbJ3ab9T3ckqkhvnIgGvk+rcB87OCVkhz9314Vn2d8QMzeo3l0WKWvPuAhA9jVDmXMrSVH/xY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B71kjI7p; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B71kjI7p" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722991018; x=1754527018; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FWYbx309e0mOibK/0qkpc0jS+BP2N0k4amoXf/TFnH8=; b=B71kjI7pgxp6yDL3k3hBTND8DB7+kGthkVum0A275FsIAUKsfr6Pb/DV SauYcB5ikQwSZ9aNEY2xt8QDywCkrIFKMgbC6Ip4DkEnROKy2VqAbbUEf YLpiRHflqLo6rLEnEL1awJRZBXSCWIAOqs2otw2gpFxdiKJJ/RTITtdUG TEdWdVAsJnwyWvP6/mPpWUCc0YsHMJ0pFlJeqXFOl/FTGQpgsBlM9Un+0 1vB2EvTZNTZAovKOEA/5stlGIZNNMKf1v9HFUtP3URClqMzjq/uArMmy1 vkN3pk9lUbf72Kjgbam6c4M3seED6tSajXaBolf4Tsu28wvDSoErQkWOg w==; X-CSE-ConnectionGUID: Q9JeiU9ATS2US5XUeWTblw== X-CSE-MsgGUID: k+4eRi5UR0u8QranV8+m3A== X-IronPort-AV: E=McAfee;i="6700,10204,11156"; a="31669758" X-IronPort-AV: E=Sophos;i="6.09,268,1716274800"; d="scan'208";a="31669758" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2024 17:36:57 -0700 X-CSE-ConnectionGUID: Zc8pSRbkQyWw8Xd5UfY+bQ== X-CSE-MsgGUID: qPZar2KpSm6T7COtEGBoHg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,268,1716274800"; d="scan'208";a="61497020" Received: from timelab-spr09.ch.intel.com (HELO timelab-spr09.sc.intel.com) ([143.182.136.138]) by orviesa003.jf.intel.com with ESMTP; 06 Aug 2024 17:36:56 -0700 From: christopher.s.hall@intel.com To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, vinicius.gomes@intel.com, david.zage@intel.com, vinschen@redhat.com, rodrigo.cadore@l-acoustics.com, Christopher S M Hall Subject: [PATCH iwl-net v1 4/5] igc: Reduce retry count to a more reasonable number Date: Tue, 6 Aug 2024 17:30:31 -0700 Message-Id: <20240807003032.10300-5-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240807003032.10300-1-christopher.s.hall@intel.com> References: <20240807003032.10300-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Christopher S M Hall Setting the retry count to 8x is more than sufficient. 100x is unreasonable and would indicate broken hardware/firmware. Fixes: a90ec8483732 ("igc: Add support for PTP getcrosststamp()") Signed-off-by: Christopher S M Hall --- drivers/net/ethernet/intel/igc/igc_ptp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index fb885fcaa97c..f770e39650ef 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -1008,8 +1008,8 @@ static int igc_phc_get_syncdevicetime(ktime_t *device, u32 stat, t2_curr_h, t2_curr_l; struct igc_adapter *adapter = ctx; struct igc_hw *hw = &adapter->hw; - int err, count = 100; ktime_t t1, t2_curr; + int err, count = 8; /* Doing this in a loop because in the event of a * badly timed (ha!) system clock adjustment, we may From patchwork Wed Aug 7 00:30:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris H X-Patchwork-Id: 13755572 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C9522770E for ; Wed, 7 Aug 2024 00:36:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722991019; cv=none; b=TXLhYF8GKkKLOTi7MAHb7XOUS7zsE604qJbbHZGzTndPMEgFl/GTihW7BU5Oa7o8IgT/yit4uvEkThtwqfALl7C0ywHEymBPYQ+/ucX+ndb97gMrFw2h+9ijEVMs0QPbwiDIRw2uXcuYdkr2+zy7XsbPv+lhv/r59F/OhB6qzzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722991019; c=relaxed/simple; bh=Rdr9qX500IejMlvTst8ST2srghzPY596qYKAm+Pca6Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hLxEi4hePs5kdj5TKL/yOviT+K7FPRLqiRSM3UR6mK3aapy6d6lGQMRHdfwVFeThZ6IEr5R/iF3b1MquyuJoRAmgkVZSv2W1MDxU1aPvbz8AM4/yKaGgyxnZytkcZUbZt/YRU6FitpPdy7FqhiTaIgFIPppWGeXzVLwkEdwlTyw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=E9cTdrhW; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="E9cTdrhW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722991018; x=1754527018; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Rdr9qX500IejMlvTst8ST2srghzPY596qYKAm+Pca6Q=; b=E9cTdrhWKKEGbU7ifc8TI3AxleWXA7PsJy1RsWmP+GDVGu/oKCXQJqXr CDTWbqCoCtryatlj80aB+4ZPTF6jhF7xS8pSvdeimfJrJAON9ElOcUsfn 0e8u4/dwdIRfSAk9XJj1oNXc3E8GizI/n/r1iajsZKrSDbqk8YZtqDKaR gdARzYr4fDrKypnlIOwy7MAHHeX5BIr04Y7GKFqNncG1cCCKz8UaqPKTQ Gdd+Qnfu93fJ8EVR1RuHaaYA565LZof3twSPvYjKeMFWqSUOeadUgdb48 3ORXQOcEQ/CxuZ5NRJo/nR2yS7NU18GY9ynr4IT6qdf4nm8PaYgmfDlL0 w==; X-CSE-ConnectionGUID: 40m+/cQVSCebPnX8CBTySg== X-CSE-MsgGUID: 0rPddeEKSlqS0WuQmI6JVQ== X-IronPort-AV: E=McAfee;i="6700,10204,11156"; a="31669762" X-IronPort-AV: E=Sophos;i="6.09,268,1716274800"; d="scan'208";a="31669762" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2024 17:36:58 -0700 X-CSE-ConnectionGUID: cSuwcZ+2RVGto+yMtdbE9g== X-CSE-MsgGUID: kvCrhZO1SAyCv7/j1r5Agw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,268,1716274800"; d="scan'208";a="61497023" Received: from timelab-spr09.ch.intel.com (HELO timelab-spr09.sc.intel.com) ([143.182.136.138]) by orviesa003.jf.intel.com with ESMTP; 06 Aug 2024 17:36:57 -0700 From: christopher.s.hall@intel.com To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, vinicius.gomes@intel.com, david.zage@intel.com, vinschen@redhat.com, rodrigo.cadore@l-acoustics.com, Christopher S M Hall Subject: [PATCH iwl-net v1 5/5] igc: Add lock preventing multiple simultaneous PTM transactions Date: Tue, 6 Aug 2024 17:30:32 -0700 Message-Id: <20240807003032.10300-6-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240807003032.10300-1-christopher.s.hall@intel.com> References: <20240807003032.10300-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Christopher S M Hall Add a mutex around the PTM transaction to prevent multiple transactors Multiple processes try to initiate a PTM transaction, one or all may fail. This can be reproduced by running two instances of the following: $ sudo phc2sys -O 0 -i tsn0 -m PHC2SYS exits with: "ioctl PTP_OFFSET_PRECISE: Connection timed out" when the PTM transaction fails Note: Normally two instance of PHC2SYS will not run, but one process should not break another. Fixes: a90ec8483732 ("igc: Add support for PTP getcrosststamp()") Signed-off-by: Christopher S M Hall --- drivers/net/ethernet/intel/igc/igc.h | 1 + drivers/net/ethernet/intel/igc/igc_ptp.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h index c38b4d0f00ce..fbac02c79178 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -315,6 +315,7 @@ struct igc_adapter { struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ ktime_t ptp_reset_start; /* Reset time in clock mono */ struct system_time_snapshot snapshot; + struct mutex ptm_lock; /* Only allow one PTM transaction at a time */ char fw_version[32]; diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index f770e39650ef..c70a6393c210 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -1068,9 +1068,16 @@ static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp, { struct igc_adapter *adapter = container_of(ptp, struct igc_adapter, ptp_caps); + int ret; - return get_device_system_crosststamp(igc_phc_get_syncdevicetime, - adapter, &adapter->snapshot, cts); + /* This blocks until any in progress PTM transactions complete */ + mutex_lock(&adapter->ptm_lock); + + ret = get_device_system_crosststamp(igc_phc_get_syncdevicetime, + adapter, &adapter->snapshot, cts); + mutex_unlock(&adapter->ptm_lock); + + return ret; } static int igc_ptp_getcyclesx64(struct ptp_clock_info *ptp, @@ -1302,6 +1309,7 @@ void igc_ptp_reset(struct igc_adapter *adapter) wr32(IGC_PTM_CTRL, ctrl); /* Force the first cycle to run. */ + mutex_init(&adapter->ptm_lock); igc_ptm_trigger(hw); if (readx_poll_timeout_atomic(rd32, IGC_PTM_STAT, stat,