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Wed, 7 Aug 2024 18:32:37 GMT Received: from hu-molvera-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 7 Aug 2024 11:32:36 -0700 From: Melody Olvera To: Souradeep Chowdhury , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Trilok Soni , Satya Durga Srinivasu Prabhala , Elson Serrao CC: , , , , , Melody Olvera Subject: [PATCH v1 1/3] dt-bindings: soc: qcom: eud: Update compatible strings for eud Date: Wed, 7 Aug 2024 11:32:02 -0700 Message-ID: <20240807183205.803847-2-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240807183205.803847-1-quic_molvera@quicinc.com> References: <20240807183205.803847-1-quic_molvera@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: RTQ5svxgQnS2Ahwco3fwoLPPel1JGzn8 X-Proofpoint-GUID: RTQ5svxgQnS2Ahwco3fwoLPPel1JGzn8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-07_11,2024-08-07_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 suspectscore=0 phishscore=0 impostorscore=0 mlxscore=0 clxscore=1015 mlxlogscore=736 spamscore=0 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408070129 The EUD can more accurately be divided into two types; a secure type which requires that certain registers be updated via scm call and a nonsecure type which must access registers nonsecurely. Thus, change the compatible strings to reflect secure and nonsecure eud usage. Signed-off-by: Melody Olvera --- Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index f2c5ec7e6437..476f92768610 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -17,8 +17,8 @@ properties: compatible: items: - enum: - - qcom,sc7280-eud - - const: qcom,eud + - qcom,secure-eud + - qcom,eud reg: items: @@ -55,7 +55,7 @@ additionalProperties: false examples: - | eud@88e0000 { - compatible = "qcom,sc7280-eud", "qcom,eud"; + compatible = "qcom,eud"; reg = <0x88e0000 0x2000>, <0x88e2000 0x1000>; From patchwork Wed Aug 7 18:32:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 13756629 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B45F714375D; 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Wed, 07 Aug 2024 18:32:40 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 477IWd5l020502 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 7 Aug 2024 18:32:39 GMT Received: from hu-molvera-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 7 Aug 2024 11:32:38 -0700 From: Melody Olvera To: Souradeep Chowdhury , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Trilok Soni , Satya Durga Srinivasu Prabhala , Elson Serrao CC: , , , , , Melody Olvera Subject: [PATCH v1 2/3] usb: misc: qcom_eud: Access mode manager through secure calls Date: Wed, 7 Aug 2024 11:32:03 -0700 Message-ID: <20240807183205.803847-3-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240807183205.803847-1-quic_molvera@quicinc.com> References: <20240807183205.803847-1-quic_molvera@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Dln-m1TTaEhHfBiIpKsLtVKcYWX1fTXm X-Proofpoint-GUID: Dln-m1TTaEhHfBiIpKsLtVKcYWX1fTXm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-07_11,2024-08-07_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 phishscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408070129 On many SoCs, the EUD mode manager needs to be accessed through calls to the secure monitor, so add a compatible string and a config to assess how the mode manager must be accessed and change behavior accordingly. Signed-off-by: Melody Olvera --- drivers/usb/misc/qcom_eud.c | 53 ++++++++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 6 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 19906301a4eb..77ef089a3ebf 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -35,18 +36,31 @@ struct eud_chip { struct usb_role_switch *role_sw; void __iomem *base; void __iomem *mode_mgr; + phys_addr_t mode_mgr_phys; unsigned int int_status; int irq; bool enabled; bool usb_attached; }; +struct eud_cfg { + bool secure_eud_en; +}; + static int enable_eud(struct eud_chip *priv) { + int ret; + writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + if (priv->mode_mgr_phys && !priv->mode_mgr) { + ret = qcom_scm_io_writel(priv->mode_mgr_phys + EUD_REG_EUD_EN2, 1); + if (ret) + return ret; + } else { + writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + } return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } @@ -54,7 +68,10 @@ static int enable_eud(struct eud_chip *priv) static void disable_eud(struct eud_chip *priv) { writel(0, priv->base + EUD_REG_CSR_EUD_EN); - writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); + if (priv->mode_mgr_phys && !priv->mode_mgr) + qcom_scm_io_writel(priv->mode_mgr_phys + EUD_REG_EUD_EN2, 0); + else + writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); } static ssize_t enable_show(struct device *dev, @@ -178,6 +195,8 @@ static void eud_role_switch_release(void *data) static int eud_probe(struct platform_device *pdev) { struct eud_chip *chip; + struct resource *res; + const struct eud_cfg *cfg; int ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); @@ -200,9 +219,22 @@ static int eud_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); - chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(chip->mode_mgr)) - return PTR_ERR(chip->mode_mgr); + cfg = of_device_get_match_data(&pdev->dev); + if (!cfg) + return -EINVAL; + + if (cfg->secure_eud_en) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return -ENODEV; + chip->mode_mgr_phys = res->start; + chip->mode_mgr = NULL; + } else { + chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->mode_mgr)) + return PTR_ERR(chip->mode_mgr); + chip->mode_mgr_phys = 0; + } chip->irq = platform_get_irq(pdev, 0); if (chip->irq < 0) @@ -231,8 +263,17 @@ static void eud_remove(struct platform_device *pdev) disable_irq_wake(chip->irq); } +static const struct eud_cfg nonsecure_eud = { + .secure_eud_en = false, +}; + +static const struct eud_cfg secure_eud = { + .secure_eud_en = true, +}; + static const struct of_device_id eud_dt_match[] = { - { .compatible = "qcom,eud" }, + { .compatible = "qcom,eud", .data = &nonsecure_eud }, + { .compatible = "qcom,secure-eud", .data = &secure_eud }, { } }; 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Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3d8410683402..f4b120043036 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4018,7 +4018,7 @@ system-cache-controller@9200000 { }; eud: eud@88e0000 { - compatible = "qcom,sc7280-eud", "qcom,eud"; + compatible = "qcom,eud"; reg = <0 0x88e0000 0 0x2000>, <0 0x88e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;