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Tue, 5 Mar 2019 10:19:25 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba Subject: [PATCH v5 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Date: Tue, 5 Mar 2019 11:19:06 +0100 Message-Id: <1551781151-5562-4-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551781151-5562-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIKsWRmVeSWpSXmKPExsWy7djPc7p6vnUxBq9maVlsnLGe1eL6l+es FvOPnGO16H/8mtni/PkN7BZnm96wW9xqkLG4vGsOm8Xn3iOMFjPO72OyWHvkLrvF7cYVbBaH 37SzOvB6bFrVyeZx8N0eJo++LasYPT5vkgtgieKySUnNySxLLdK3S+DKeDrxCHvBQb6KCyun sTYwbuXpYuTkkBAwkfj18wRrFyMXh5DACkaJL+8us0A4Xxglfs1azQ7hfGaUmPz9IgtMy53J X6ESyxklZq29ygTXsuLvFKAMBwebgJ7EjlWFIA0iAtUSd67vZwapYRZ4yygx8+YXFpAaYQF/ iU1PikBMFgFViTVvw0DKeQU8Ja5MncUIsUtO4ua5TmYQm1PAS2L/wvVgYyQE5rFLzLlxnB2i yEXix6xtULawxKvjW6BsGYn/O+czQdjFEmc7VrFB2DUS7Sd3QNVYSxw+fpEV5AZmAU2J9bv0 IcKOEs1HP4OFJQT4JG68FQQJMwOZk7ZNZ4YI80p0tAlBVGtIbOm5ALVITGL5mmlQwz0ktp/t hQbuXEaJ46e3sExglJ+FsGwBI+MqRvHU0uLc9NRio7zUcr3ixNzi0rx0veT83E2MwIRy+t/x LzsYd/1JOsQowMGoxMObYVYbI8SaWFZcmXuIUYKDWUmE9494XYwQb0piZVVqUX58UWlOavEh RmkOFiVx3mqGB9FCAumJJanZqakFqUUwWSYOTqkGRtv/sub3zx4xMrsn+3DxQs8XqT07b1/j n3z/TPmX8zd5debwn/nwTtt/7y1Zk7C4RSuWK606t3tdv+DEZ8kV3AY/33068uy9RklByuQl ez4l2cR8nCkRdNBk+1Glljq5RYl2cUcjO1z2Hl7ytFNNboPIEoGNN091GZY3eaRyumioe01m dDhtskqJpTgj0VCLuag4EQBC3pYiJAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsVy+t/xu7q6vnUxBr9/mllsnLGe1eL6l+es FvOPnGO16H/8mtni/PkN7BZnm96wW9xqkLG4vGsOm8Xn3iOMFjPO72OyWHvkLrvF7cYVbBaH 37SzOvB6bFrVyeZx8N0eJo++LasYPT5vkgtgidKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx 1DM0No+1MjJV0rezSUnNySxLLdK3S9DLeDrxCHvBQb6KCyunsTYwbuXpYuTkkBAwkbgz+St7 FyMXh5DAUkaJk207WSESYhKT9m1nh7CFJf5c62IDsYUEPjFKbJwh1cXIwcEmoCexY1UhSFhE oF6i/80lNpA5zALfGSUOPZnACJIQFvCVOLz2JSNIPYuAqsSat2EgYV4BT4krU2cxQoyXk7h5 rpMZxOYU8JLYv3A9M8QqT4mpXxeyTGDkW8DIsIpRJLW0ODc9t9hIrzgxt7g0L10vOT93EyMw wLcd+7llB2PXu+BDjAIcjEo8vBlmtTFCrIllxZW5hxglOJiVRHj/iNfFCPGmJFZWpRblxxeV 5qQWH2I0BbppIrOUaHI+MPrySuINTQ3NLSwNzY3Njc0slMR5zxtURgkJpCeWpGanphakFsH0 MXFwSjUwSsgd3KEouetSudTzeeayTGdiPzMueps5+cviyZE/N53/HPZfeNeBkOS/Hns4TT+5 855gi9aaPm3h3wgnm2trJ2U8OOp74thT93XLjQp77A5vFn2/7vHXxSs3+rWdL1kv+uCGdkPI HtULM4yKDZsW6Eavnrq1/eL307XctmyLD/07LKf3I8/12DclluKMREMt5qLiRADa8HxGhgIA AA== X-CMS-MailID: 20190305101926eucas1p158d6241bd6851b3d98ed9aae6cba502c X-Msg-Generator: CA X-RootMTR: 20190305101926eucas1p158d6241bd6851b3d98ed9aae6cba502c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190305101926eucas1p158d6241bd6851b3d98ed9aae6cba502c References: <1551781151-5562-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 6da5875..6f5db70 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1331,6 +1331,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), +}; + static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), @@ -1473,7 +1484,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),