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Thu, 8 Aug 2024 14:04:04 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 8 Aug 2024 07:03:59 -0700 From: Luo Jie Date: Thu, 8 Aug 2024 22:03:12 +0800 Subject: [PATCH 1/4] dt-bindings: clock: qcom: Add common PLL clock controller for IPQ SoC MIME-Version: 1.0 Message-ID: <20240808-qcom_ipq_cmnpll-v1-1-b0631dcbf785@quicinc.com> References: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> In-Reply-To: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723125835; l=3457; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=bqymaGN7lV2NoCv9XT3InR9+WQfCR0oVo66v/yxIWRI=; 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It receives input clock from the on-chip Wi-Fi, and produces output clocks at fixed rates. These output rates are predetermined, and are unrelated to the input clock rate. The output clocks are supplied to the Ethernet hardware such as PPE (packet process engine) and the externally connected switch or PHY device. The common PLL driver is initially being supported for IPQ9574 SoC. Signed-off-by: Luo Jie --- .../bindings/clock/qcom,ipq-cmn-pll.yaml | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq-cmn-pll.yaml new file mode 100644 index 000000000000..c45b3a201751 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq-cmn-pll.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq-cmn-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Common PLL Clock Controller on IPQ SoC + +maintainers: + - Bjorn Andersson + - Luo Jie + +description: + The common PLL clock controller expects a reference input clock. + This reference clock is from the on-board Wi-Fi. The CMN PLL + supplies a number of fixed rate output clocks to the Ethernet + devices including PPE (packet process engine) and the connected + switch or PHY device. + +properties: + compatible: + enum: + - qcom,ipq9574-cmn-pll + + reg: + maxItems: 1 + + clocks: + items: + - description: The reference clock, the supported clock rates include + 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ. + - description: The AHB clock + - description: The SYS clock + description: + The reference clock is the source clock of CMN PLL, which is from the + Wi-Fi. The AHB and SYS clocks must be enabled to access common PLL + clock registers. + + clock-names: + items: + - const: ref + - const: ahb + - const: sys + + clock-output-names: + items: + - const: ppe-353mhz + - const: eth0-50mhz + - const: eth1-50mhz + - const: eth2-50mhz + - const: eth-25mhz + description: + The output clocks are given to Ethernet blocks that includes PPE and + the connected switch or PHY device. + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + + clock-controller@9b000 { + compatible = "qcom,ipq9574-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + clock-output-names = "ppe-353mhz", + "eth0-50mhz", + "eth1-50mhz", + "eth2-50mhz", + "eth-25mhz"; + #clock-cells = <1>; + }; +... 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Thu, 8 Aug 2024 14:04:08 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 8 Aug 2024 07:04:04 -0700 From: Luo Jie Date: Thu, 8 Aug 2024 22:03:13 +0800 Subject: [PATCH 2/4] clk: qcom: Add common PLL clock controller driver for IPQ SoC MIME-Version: 1.0 Message-ID: <20240808-qcom_ipq_cmnpll-v1-2-b0631dcbf785@quicinc.com> References: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> In-Reply-To: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723125835; l=9424; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=zx5SghnMnnNJKI++0+Ng96Jv8/fUXJm6EqOTHdQBdTA=; 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The driver is initially supported for IPQ9574 SoC. The common PLL clock controller expects a reference input clock from the on-board Wi-Fi block acting as clock source. The input reference clock needs to be configured to one of the supported clock rates. The controller supplies a number of fixed-rate output clocks. For the IPQ9574, there is one output clock of 353 MHZ to PPE (Packet Process Engine) hardware block, three 50 MHZ output clocks and an additional 25 MHZ output clock supplied to the connected Ethernet devices. Signed-off-by: Luo Jie --- drivers/clk/qcom/Kconfig | 10 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-ipq-cmn-pll.c | 233 +++++++++++++++++++++++++++++++++++++ 3 files changed, 244 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index cf6ad908327f..8e36cde64134 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -190,6 +190,16 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. +config IPQ_CMN_PLL + tristate "IPQ Common PLL Clock Controller" + depends on IPQ_GCC_9574 + help + Support for common PLL clock controller on IPQ platform. The + common PLL feeds the reference clocks to the Ethernet devices + based on IPQ SoC. + Say Y or M if you want to support common PLL clock on the IPQ + based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 8a6f0dabd02f..35f656146de7 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o +obj-$(CONFIG_IPQ_CMN_PLL) += clk-ipq-cmn-pll.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o diff --git a/drivers/clk/qcom/clk-ipq-cmn-pll.c b/drivers/clk/qcom/clk-ipq-cmn-pll.c new file mode 100644 index 000000000000..c10c6a7e82e6 --- /dev/null +++ b/drivers/clk/qcom/clk-ipq-cmn-pll.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* + * Common PLL block expects the reference clock from on-board Wi-Fi block, + * and supplies the fixed rate clocks as output to the Ethernet hardware + * blocks. The Ethernet related blocks include PPE (packet process engine) + * and the external connected PHY (or switch) chip receiving clocks from + * the common PLL. + * + * On the IPQ9574 SoC, There are three clocks with 50 MHZ, one clock with + * 25 MHZ which are output from the common PLL to Ethernet PHY (or switch), + * and one clock with 353 MHZ to PPE. + * + * +---------+ + * | GCC | + * +--+---+--+ + * AHB CLK| |SYS CLK + * V V + * +-------+---+------+ + * | +-------------> eth0-50mhz + * REF CLK | IPQ9574 | + * -------->+ +-------------> eth1-50mhz + * | CMN PLL block | + * | +-------------> eth2-50mhz + * | | + * +---------+--------+-------------> eth-25mhz + * | + * V + * ppe-353mhz + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define CMN_PLL_REFCLK_SRC_SELECTION 0x28 +#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) + +#define CMN_PLL_REFCLK_CONFIG 0x784 +#define CMN_PLL_REFCLK_EXTERNAL BIT(9) +#define CMN_PLL_REFCLK_DIV GENMASK(8, 4) +#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) + +#define CMN_PLL_POWER_ON_AND_RESET 0x780 +#define CMN_ANA_EN_SW_RSTN BIT(6) + +/** + * struct cmn_pll_fixed_clk - Common PLL output clocks information + * @nrates: Number of elements in rates + * @rates: Array of clock rates supplied by common PLL + */ +struct cmn_pll_fixed_clk { + int nrates; + const unsigned long *rates; +}; + +/* + * The clock rates are for the output clock ppe-353mhz, eth0-50mhz + * eth1-50mhz, eth2-50mhz and eth-25mhz. + */ +static const unsigned long ipq9574_rates[] = { + 353000000UL, 50000000UL, 50000000UL, 50000000UL, 25000000UL, +}; + +static const struct cmn_pll_fixed_clk ipq9574_fixed_clk = { + .nrates = ARRAY_SIZE(ipq9574_rates), + .rates = ipq9574_rates, +}; + +static int ipq_cmn_pll_config(struct device *dev, unsigned long parent_rate) +{ + void __iomem *base; + u32 val; + + base = devm_of_iomap(dev, dev->of_node, 0, NULL); + if (IS_ERR(base)) + return PTR_ERR(base); + + val = readl(base + CMN_PLL_REFCLK_CONFIG); + val &= ~(CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_INDEX); + + /* + * Configure the reference input clock selection as per the given rate. + * The output clock rates are always of fixed value. + */ + switch (parent_rate) { + case 25000000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3); + break; + case 31250000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4); + break; + case 40000000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6); + break; + case 48000000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7); + break; + case 50000000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8); + break; + case 96000000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7); + val &= ~CMN_PLL_REFCLK_DIV; + val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2); + break; + default: + return -EINVAL; + } + + writel(val, base + CMN_PLL_REFCLK_CONFIG); + + /* Update the source clock rate selection. Only 96 MHZ uses 0. */ + val = readl(base + CMN_PLL_REFCLK_SRC_SELECTION); + val &= ~CMN_PLL_REFCLK_SRC_DIV; + if (parent_rate != 96000000) + val |= FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 1); + + writel(val, base + CMN_PLL_REFCLK_SRC_SELECTION); + + /* + * Reset the common PLL block by asserting/de-asserting for 100 ms + * each, to ensure the updated configurations take effect. + */ + val = readl(base + CMN_PLL_POWER_ON_AND_RESET); + val &= ~CMN_ANA_EN_SW_RSTN; + writel(val, base); + msleep(100); + + val |= CMN_ANA_EN_SW_RSTN; + writel(val, base + CMN_PLL_POWER_ON_AND_RESET); + msleep(100); + + return 0; +} + +static int ipq_cmn_pll_clk_register(struct device *dev, const char *parent) +{ + const struct cmn_pll_fixed_clk *fixed_clk; + struct clk_hw_onecell_data *data; + const char *clk_name; + struct clk_hw *hw; + int index; + + fixed_clk = of_device_get_match_data(dev); + if (!fixed_clk) + return -ENODEV; + + data = devm_kzalloc(dev, struct_size(data, hws, fixed_clk->nrates), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + /* + * Register the fixed rate output clocks with the correct clock names, + * the number of clocks and clock names are guaranteed by DTS. + */ + for (index = 0; index < fixed_clk->nrates; index++) { + if (of_property_read_string_index(dev->of_node, + "clock-output-names", + index, &clk_name)) + return -ENODEV; + + hw = devm_clk_hw_register_fixed_rate(dev, clk_name, parent, 0, + fixed_clk->rates[index]); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + data->hws[index] = hw; + } + data->num = fixed_clk->nrates; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); +} + +static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk *clk; + int ret; + + /* + * To access the common PLL registers, the GCC AHB & SYSY clocks + * for common PLL block need to be enabled. + */ + clk = devm_clk_get_enabled(dev, "ahb"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Enable AHB clock failed\n"); + + clk = devm_clk_get_enabled(dev, "sys"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Enable SYS clock failed\n"); + + clk = devm_clk_get(dev, "ref"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Get reference clock failed\n"); + + /* Configure common PLL to apply the reference clock. */ + ret = ipq_cmn_pll_config(dev, clk_get_rate(clk)); + if (ret) + return dev_err_probe(dev, ret, "Configure common PLL failed\n"); + + return ipq_cmn_pll_clk_register(dev, __clk_get_name(clk)); +} + +static const struct of_device_id ipq_cmn_pll_clk_ids[] = { + { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_fixed_clk }, + { } +}; + +static struct platform_driver ipq_cmn_pll_clk_driver = { + .probe = ipq_cmn_pll_clk_probe, + .driver = { + .name = "ipq_cmn_pll", + .of_match_table = ipq_cmn_pll_clk_ids, + }, +}; + +module_platform_driver(ipq_cmn_pll_clk_driver); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. 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Signed-off-by: Luo Jie --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 01dd286ba7ef..1bc7bd86e589 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1300,6 +1300,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y +CONFIG_IPQ_CMN_PLL=m CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y From patchwork Thu Aug 8 14:03:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 13757527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D64BFC52D6F for ; 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Thu, 08 Aug 2024 14:04:19 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 478E4Iic021443 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 Aug 2024 14:04:18 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 8 Aug 2024 07:04:13 -0700 From: Luo Jie Date: Thu, 8 Aug 2024 22:03:15 +0800 Subject: [PATCH 4/4] arm64: dts: qcom: Add common PLL node for IPQ9574 SoC MIME-Version: 1.0 Message-ID: <20240808-qcom_ipq_cmnpll-v1-4-b0631dcbf785@quicinc.com> References: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> In-Reply-To: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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It in-turn supplies fixed rate output clocks to the hardware blocks that provide ethernet functions, such as PPE (Packet Process Engine) and connected switch or PHY. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 6 +++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 22 +++++++++++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..26bc2de7f99a 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -3,7 +3,7 @@ * IPQ9574 RDP board common device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -167,3 +167,7 @@ &usb3 { &xo_board_clk { clock-frequency = <24000000>; }; + +&cmn_pll_ref_clk { + clock-frequency = <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 48dfafea46a7..ad7789dc686e 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -3,7 +3,7 @@ * IPQ9574 SoC device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -28,6 +28,11 @@ xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + cmn_pll_ref_clk: cmn-pll-ref-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; }; cpus { @@ -226,6 +231,21 @@ rpm_msg_ram: sram@60000 { reg = <0x00060000 0x6000>; }; + clock-controller@9b000 { + compatible = "qcom,ipq9574-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + clock-output-names = "ppe-353mhz", + "eth0-50mhz", + "eth1-50mhz", + "eth2-50mhz", + "eth-25mhz"; + #clock-cells = <1>; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>;