From patchwork Thu Aug 8 16:31:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Detlev Casanova X-Patchwork-Id: 13757936 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 873B51917D4; Thu, 8 Aug 2024 16:34:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.14 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723134844; cv=pass; b=k5M9DkYgba3mE3RsJBOXWyCOSuGFD0uM0WbjW/L+6Px9eO0tdT+WX6QsQL+rBFfRA4CRT3UJ4n5U/LuAg0EUpxNGiyXEv3T9fKP97Lx5iyv0xTbZlsZ49rezqknu8DvaNOFPVenHLTjPuvDmIEYgsEwM66m2d6d946EvoMGASkE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723134844; c=relaxed/simple; bh=TmXhq8Z9zdF+EcftMWkcPqg6cC8NKV7O84Q2Ne4BGxQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u5YTFVuz9pvLtOWMUafnqs+5GPhzqQE9zYYqmDIx4E32KAGvNGSAWCzp4CqP1bB7y+9+91xYOipkPXB9strMHMiF8w6P94AO6+pllKOvrO2l7Nuw0ZEnVqKovEmEFcgmkNO4A86BZZkPmYK1jMFulqHc3cXnsZL01Vnpc9tiEnk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=detlev.casanova@collabora.com header.b=Snv7pVN5; arc=pass smtp.client-ip=136.143.188.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=detlev.casanova@collabora.com header.b="Snv7pVN5" ARC-Seal: i=1; a=rsa-sha256; t=1723134818; cv=none; d=zohomail.com; s=zohoarc; b=WEU/cEHl7no+OufB895Wcx4cmnUUFZXcE9N7ppbGThVX6q2ExlZamXmtNjFBNktLoixBaPNOfAUq4nkJGvLlJFjUEspeY9b7VEStwnTDtHOoMZPlwBnaR85gHrNiMoEh8gYOQo7JyXtc2sRHHlV3sw2VQqehJ69XRwhaQfUOH5E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1723134818; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=RyCepvyWzhp8Bg9hhu049ivfAGgOO+ujHi0U3uQVpzQ=; b=ZVy7caFIR1AptdRp/7y5Vuw18m08/jEmdj7hXpezUdFMQi7Ks1mMQ/DuZKDEuDWzbNXupklQC1Y7FNA0cLvI2BPH67C0cVCVozeAEV12qNKRQ6BIgX/LkfFFeCXs6NhISHHsmwLj+LQuVvneFnElmJ5Rrk59SrsUOuP160qdW0Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=detlev.casanova@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1723134818; s=zohomail; d=collabora.com; i=detlev.casanova@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=RyCepvyWzhp8Bg9hhu049ivfAGgOO+ujHi0U3uQVpzQ=; b=Snv7pVN5ww1a7qVUz0RvQepSkMx5/QlMLoO8X/c6BNNWIadNyjQjLCqg21DUllBo N1c1lAcZEhmgMi1uxO9Eza7WkO/NEFH2MbqAw9IDjSUuJoR6p8AD1d0jWZjRpMe6yu2 zNB9KQQutdVrXXoGS7y6Uk/DbxXdaiFjwb5hnifo= Received: by mx.zohomail.com with SMTPS id 1723134816403244.22942005210552; Thu, 8 Aug 2024 09:33:36 -0700 (PDT) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson , Detlev Casanova , Finley Xiao , Jagan Teki , Arnd Bergmann , Elaine Zhang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 1/2] dt-bindings: power: Add support for RK3576 SoC Date: Thu, 8 Aug 2024 12:31:04 -0400 Message-ID: <20240808163451.80750-2-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240808163451.80750-1-detlev.casanova@collabora.com> References: <20240808163451.80750-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External From: Finley Xiao Define power domain IDs as described in the TRM and add compatible for rockchip,rk3576-power-controller Signed-off-by: Finley Xiao [reword, add yaml] Signed-off-by: Detlev Casanova Acked-by: Conor Dooley --- .../power/rockchip,power-controller.yaml | 1 + .../dt-bindings/power/rockchip,rk3576-power.h | 30 +++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 include/dt-bindings/power/rockchip,rk3576-power.h diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml index 0d5e999a58f1b..650dc0aae6f51 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -41,6 +41,7 @@ properties: - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller - rockchip,rk3568-power-controller + - rockchip,rk3576-power-controller - rockchip,rk3588-power-controller - rockchip,rv1126-power-controller diff --git a/include/dt-bindings/power/rockchip,rk3576-power.h b/include/dt-bindings/power/rockchip,rk3576-power.h new file mode 100644 index 0000000000000..324a056aa8512 --- /dev/null +++ b/include/dt-bindings/power/rockchip,rk3576-power.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +#ifndef __DT_BINDINGS_POWER_RK3576_POWER_H__ +#define __DT_BINDINGS_POWER_RK3576_POWER_H__ + +/* VD_NPU */ +#define RK3576_PD_NPU 0 +#define RK3576_PD_NPUTOP 1 +#define RK3576_PD_NPU0 2 +#define RK3576_PD_NPU1 3 + +/* VD_GPU */ +#define RK3576_PD_GPU 4 + +/* VD_LOGIC */ +#define RK3576_PD_NVM 5 +#define RK3576_PD_SDGMAC 6 +#define RK3576_PD_USB 7 +#define RK3576_PD_PHP 8 +#define RK3576_PD_SUBPHP 9 +#define RK3576_PD_AUDIO 10 +#define RK3576_PD_VEPU0 11 +#define RK3576_PD_VEPU1 12 +#define RK3576_PD_VPU 13 +#define RK3576_PD_VDEC 14 +#define RK3576_PD_VI 15 +#define RK3576_PD_VO0 16 +#define RK3576_PD_VO1 17 +#define RK3576_PD_VOP 18 + +#endif From patchwork Thu Aug 8 16:31:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Detlev Casanova X-Patchwork-Id: 13757935 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77466191494; Thu, 8 Aug 2024 16:34:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.14 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723134843; cv=pass; b=Khr/WsCUboeUH6rlGOXOe6kZXP0WC7JplmfkAm4f4mcTXJwO2HblwxuwRAfSZ304udTMqWsy12MK7oOb18Ac6WYuymd/kBQkJOyBOchoSUyqOVxPuK/sT/dGVZ4nSgzOVlT80VddGIWbJV66OJ6YjWsJjsYnsdUYU4VlJaRbNOw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723134843; c=relaxed/simple; bh=aej6SKxAAwpzLuI/YEKkMKLyJohYyL4+daLLnEyQNRo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eY77BNv54VDXM9N4ghh1yfaZNGxSpoxGgRulTlUTrivXS0JeAYlzNiPGL9CRa5NngMbti+Zd8k6sn1gYXcZFkTz/kZj2eECkC4hb6xD+VKUKoAnHiwOh/Ue50bT10QVkN1LSUQktjkWaLeyfe6xg1VMznaHDI2c4RRDzajJgv2g= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=detlev.casanova@collabora.com header.b=YHrEEmGp; arc=pass smtp.client-ip=136.143.188.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=detlev.casanova@collabora.com header.b="YHrEEmGp" ARC-Seal: i=1; a=rsa-sha256; t=1723134818; cv=none; d=zohomail.com; s=zohoarc; b=IhludwVswXvzqENagkqHgAiY97vVJPp5Y5IfcB5ddWt4na0KSwrkmOjTrUkcDVGXzba0OA+pqMveYmKaWMpk+9KmSZtqiiueMUomyyAEj1Vc72nNmfRqIjbVzk0kN7QZdj5XmqpYvsw3vWlX6oooX6ABHNPm6BmoBk6Pfb0Yvhc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1723134818; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=9bVG/WfF+0n0gxa9bF395FNuCg9vCC0x9bJ3iZgPyeM=; b=lRqlqbij991DF3SLESfFSqoP5yer3G6JSb9VUQ54qqN5nwHYf7XzUnUPhs1Y8tUoVEUzOSniTdtLpHuyZ9DIb36KP7qHwaJKePpQMmjWPYQ+jS5yRVdMdjThSIEyHAD2YMq4sOQXGXBgDhDhcGaiYKsZ5kRhaR5okSCn8+BYoLc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=detlev.casanova@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1723134818; s=zohomail; d=collabora.com; i=detlev.casanova@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=9bVG/WfF+0n0gxa9bF395FNuCg9vCC0x9bJ3iZgPyeM=; b=YHrEEmGpH3GoDn1Gjke0jvzivZepYnHTcIS8m5WWnCWMYCGpNBxQU5Zla6KatreX Y6uXJ9FBpssKFbUhpAwCPaZowSDKq2U7V2ubanq3RA6g/1pasFk0qFTlIN73ez7Yj+K hMCZmeNypVFZye1sJSEv9oY84WGFc9rvURH+eCMU= Received: by mx.zohomail.com with SMTPS id 1723134818122271.87033045863643; Thu, 8 Aug 2024 09:33:38 -0700 (PDT) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson , Detlev Casanova , Finley Xiao , Jagan Teki , Arnd Bergmann , Elaine Zhang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 2/2] pmdomain: rockchip: Add support for rk3576 SoC Date: Thu, 8 Aug 2024 12:31:05 -0400 Message-ID: <20240808163451.80750-3-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240808163451.80750-1-detlev.casanova@collabora.com> References: <20240808163451.80750-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External From: Finley Xiao Add configuration for RK3576 SoC and list the power domains. Signed-off-by: Finley Xiao [rebase, reword, squash] Signed-off-by: Detlev Casanova --- drivers/pmdomain/rockchip/pm-domains.c | 73 ++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 3 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c index 9b76b62869d0d..863f1ad6b9e11 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -33,6 +33,7 @@ #include #include #include +#include #include struct rockchip_domain_info { @@ -50,6 +51,7 @@ struct rockchip_domain_info { u32 pwr_offset; u32 mem_offset; u32 req_offset; + u32 delay_us; }; struct rockchip_pmu_info { @@ -144,9 +146,27 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ +#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, g_mask, delay, wakeup) \ { \ - .name = _name, \ + .name = _name, \ + .pwr_offset = p_offset, \ + .pwr_w_mask = (pwr) << 16, \ + .pwr_mask = (pwr), \ + .status_mask = (status), \ + .mem_status_mask = (r_status), \ + .repair_status_mask = (r_status), \ + .req_offset = r_offset, \ + .req_w_mask = (req) << 16, \ + .req_mask = (req), \ + .idle_mask = (idle), \ + .ack_mask = (ack), \ + .delay_us = delay, \ + .active_wakeup = wakeup, \ +} + +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ +{ \ + .name = _name, \ .req_mask = (req), \ .req_w_mask = (req) << 16, \ .ack_mask = (ack), \ @@ -175,6 +195,9 @@ struct rockchip_pmu { #define DOMAIN_RK3568(name, pwr, req, wakeup) \ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) +#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, delay, wakeup) \ + DOMAIN_M_O_R_G(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, g_mask, delay, wakeup) + /* * Dynamic Memory Controller may need to coordinate with us -- see * rockchip_pmu_block(). @@ -552,7 +575,10 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) /* if powering up, leave idle mode */ rockchip_pmu_set_idle_request(pd, false); - rockchip_pmu_restore_qos(pd); + if (pd->info->delay_us) + udelay(pd->info->delay_us); + else + rockchip_pmu_restore_qos(pd); } clk_bulk_disable(pd->num_clks, pd->clks); @@ -1106,6 +1132,28 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = { [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false), }; +static const struct rockchip_domain_info rk3576_pm_domains[] = { + [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, 0, false), + [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), 0, false), + [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), 0x6, 0, false), + [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), BIT(0), 0, false), + [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), BIT(15), 0, false), + [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, 0, 0, false), + [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, 15, false), + [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, 0, false), + [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, 0, false), + [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, 0, true), + [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), 0, false), + [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, 0, false), + [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), 0, false), + [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), 0, false), + [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), 0, false), + [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, 15, false), + [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, 0, false), + [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, 0, false), + [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), 0, false), +}; + static const struct rockchip_domain_info rk3588_pm_domains[] = { [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false), [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false), @@ -1284,6 +1332,21 @@ static const struct rockchip_pmu_info rk3568_pmu = { .domain_info = rk3568_pm_domains, }; +static const struct rockchip_pmu_info rk3576_pmu = { + .pwr_offset = 0x210, + .status_offset = 0x230, + .chain_status_offset = 0x248, + .mem_status_offset = 0x250, + .mem_pwr_offset = 0x300, + .req_offset = 0x110, + .idle_offset = 0x128, + .ack_offset = 0x120, + .repair_status_offset = 0x570, + + .num_domains = ARRAY_SIZE(rk3576_pm_domains), + .domain_info = rk3576_pm_domains, +}; + static const struct rockchip_pmu_info rk3588_pmu = { .pwr_offset = 0x14c, .status_offset = 0x180, @@ -1359,6 +1422,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .compatible = "rockchip,rk3568-power-controller", .data = (void *)&rk3568_pmu, }, + { + .compatible = "rockchip,rk3576-power-controller", + .data = (void *)&rk3576_pmu, + }, { .compatible = "rockchip,rk3588-power-controller", .data = (void *)&rk3588_pmu,