From patchwork Fri Aug 9 13:13:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Maslanka X-Patchwork-Id: 13758787 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B985E14D6EB for ; Fri, 9 Aug 2024 13:13:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723209232; cv=none; b=fqqnZ8zEQbi2IpTiGENiSsU17nYeU/7NB9SohF8/zfmpGSo02w2d1FmPGutd573K8MhmFqXAmcPzAAFEUKfUoydn8FTmcpa4mpxAD57/6/cYRhzVfBO4NXdjUNJgzlrRgt2ref6dchxO4WqlYsZuOkstXBBLItUa98g9m//J6Ag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723209232; c=relaxed/simple; bh=98Z/diLKNDBsST+GyskNA46yYAnNS1EgmuzelcgBkGU=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=mJV2/YHjTjleVVc5TLaPNsV9u5O3BS+hT4hvGDiOw+/XORLJjAgKVTKsR0g7Sd0J3ydGc9iNjUd57Jzi56ON/SgSwRDKGnIE1q0OY1Otv/QpTlhfr8JdbgQ6k0qCJ9JOIsN3oapnWT55wh1HsqbYhSEyDLzHmw/x2AxynhH5n+Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--mmaslanka.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=3U2gxwvz; arc=none smtp.client-ip=209.85.128.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--mmaslanka.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="3U2gxwvz" Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-6698f11853aso40853437b3.0 for ; Fri, 09 Aug 2024 06:13:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1723209230; x=1723814030; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=qfk55jXbMJ+9XW8lw7BFbqVnIJpApyghmdPVYouiRvE=; b=3U2gxwvzxhp+p7WyFOS7vl6kVG5g4BRxj2cYPKMnIpBXD/LQQpa0cSp7phIHciDUoB UxohIqI9llqldjkQ2yj9wpLVY6oUdNi2v5MUrNQMrC5EfLkTqCknGJwHLn5aUOLHsG2H Rv30gBFILfWQ76TFu16ZV0qOlHKFwHS5hU59LmaRj74L3AXGceHanyh0qB76prJ++TIE 9D2C8tLn6Zn5e3TPO+OL8S/gzvqPMI3YA5nt+8AYYb1AQz/2FrsnHCosI6I/eH0t1pjk 0tSEETmvOSliVL1J9R83pT3qiOx1a3hBIq34L6z2Tas9l3HwPScBe5tDPj2s27rhpEKV J/zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723209230; x=1723814030; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qfk55jXbMJ+9XW8lw7BFbqVnIJpApyghmdPVYouiRvE=; b=ds9eGXDSz1UvJECIkSq3U2Ns8RBz25Yer9b1E2ucHQ52MTX2lPQ/0Pzczim9Kyk/Pk et+Rda+rl+k3K9pYC79mDEyd7no1NYEtX4DHFJfVtT19Iy7CwdnMNYnY7CukzCvq5MW5 Yr9TpL8D+gGMGZe+mxIV+XlP4urak+9ekOK4Sr0K634x/j358DMFszEadxNs+7fo1fMo w0FoyoPOEiQdIKUY3696N67mTHfkReEfJsEb+pLAIdFiWBOT5tztE0VdPif/6AOG32ME Nxi2LMwPYVFtXci7AM8zyHhkWkwDAH+RSuoS1SJ4yHVEbKW0oBy79LLEpsvISqYOApNw 0ljg== X-Forwarded-Encrypted: i=1; AJvYcCV96fokG7toLhRVYtE0qHIlMqJ6GE8/hY3DjepCFlfERY8lZBYjb0IByyaLt2ahI6ZR9t7kXHKYTEca3OmZP/0CEXSev8FzZusre13gqqJL1LXnGA== X-Gm-Message-State: AOJu0YycTxPW7Irz9G+3mS98AN8ZywCmcOMUpRP4OQG1dxg6dEvyOSQ/ LIpQaVjN6iwY5h2RF3XBNkKorY/V0X9zLaef23QkvBaJWjTzrWPWK5cJtlqVvh66ENfzsyt/Tk9 A8Tw+UOKX1EedKg== X-Google-Smtp-Source: AGHT+IH4kJBCxiOiei21ZZPcfcqwWZSWG5cinBXlbnJTFOwf/ORgOJMo9yMLleQC22aHWj0qjIMdzl6ROAG0znA= X-Received: from mmaslanka2.c.googlers.com ([fda3:e722:ac3:cc00:31:98fb:c0a8:b8d]) (user=mmaslanka job=sendgmr) by 2002:a05:690c:711:b0:691:2f66:4b1c with SMTP id 00721157ae682-69ec8c8e4camr110527b3.6.1723209229629; Fri, 09 Aug 2024 06:13:49 -0700 (PDT) Date: Fri, 9 Aug 2024 13:13:32 +0000 In-Reply-To: <28567169-4588-002d-85b8-906d22f12f05@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <28567169-4588-002d-85b8-906d22f12f05@linux.intel.com> X-Mailer: git-send-email 2.46.0.76.ge559c4bf1a-goog Message-ID: <20240809131343.1173369-1-mmaslanka@google.com> Subject: [PATCH v4 1/2] clocksource: acpi_pm: Add external callback for suspend/resume From: Marek Maslanka To: LKML Cc: Marek Maslanka , Daniel Lezcano , Thomas Gleixner , Rajneesh Bhardwaj , David E Box , Hans de Goede , " =?utf-8?q?Ilpo_J=C3=A4rvinen?= " , platform-driver-x86@vger.kernel.org Provides the capability to register an external callback for the ACPI PM timer, which is called during the suspend and resume processes. Signed-off-by: Marek Maslanka --- Changes in v4: - No changes as this was introduced as a separated patch after the v3 review. - Link to v3: https://lore.kernel.org/lkml/20240730120546.1042515-1-mmaslanka@google.com/ --- --- drivers/clocksource/acpi_pm.c | 27 +++++++++++++++++++++++++++ drivers/clocksource/acpi_pm.h | 16 ++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 drivers/clocksource/acpi_pm.h diff --git a/drivers/clocksource/acpi_pm.c b/drivers/clocksource/acpi_pm.c index 82338773602ca..c629f5462bc0f 100644 --- a/drivers/clocksource/acpi_pm.c +++ b/drivers/clocksource/acpi_pm.c @@ -25,6 +25,12 @@ #include #include +#include "acpi_pm.h" + +static void *suspend_resume_cb_data; + +static void (*suspend_resume_callback)(void *data, bool suspend); + /* * The I/O port the PMTMR resides at. * The location is detected during setup_arch(), @@ -58,6 +64,25 @@ u32 acpi_pm_read_verified(void) return v2; } +void acpi_pm_register_suspend_resume_callback(void (*cb)(void *data, bool suspend), + void *data) +{ + suspend_resume_callback = cb; + suspend_resume_cb_data = data; +} + +static void acpi_pm_suspend(struct clocksource *cs) +{ + if (suspend_resume_callback) + suspend_resume_callback(suspend_resume_cb_data, true); +} + +static void acpi_pm_resume(struct clocksource *cs) +{ + if (suspend_resume_callback) + suspend_resume_callback(suspend_resume_cb_data, false); +} + static u64 acpi_pm_read(struct clocksource *cs) { return (u64)read_pmtmr(); @@ -69,6 +94,8 @@ static struct clocksource clocksource_acpi_pm = { .read = acpi_pm_read, .mask = (u64)ACPI_PM_MASK, .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .suspend = acpi_pm_suspend, + .resume = acpi_pm_resume, }; diff --git a/drivers/clocksource/acpi_pm.h b/drivers/clocksource/acpi_pm.h new file mode 100644 index 0000000000000..c932899f04282 --- /dev/null +++ b/drivers/clocksource/acpi_pm.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ACPI_PM_H__ +#define __ACPI_PM_H__ + +#include + +/** + * Register callback for suspend and resume event + * + * @cb Callback triggered on suspend and resume + * @data Data passed with the callback + */ +void acpi_pm_register_suspend_resume_callback(void (*cb)(void *data, bool suspend), + void *data); + +#endif From patchwork Fri Aug 9 13:13:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Maslanka X-Patchwork-Id: 13758788 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80EEB18E04E for ; Fri, 9 Aug 2024 13:13:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723209238; cv=none; b=L8VLCbeeY2RZEU0urSlWXT443ijsacxzENFKVzLt64J/cbB3LaCh6BIjsOs4KroFyjGsTEjVeGRr9H9pGYJhcDOXMHKHxfCRGMv4YSqV8rKQ4Sn3EtApaE2oqCdkO5AC85prz1S1qTPotaZmGcHPi6tkjQYCXUyksHHKhT3XLA8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723209238; c=relaxed/simple; bh=z1ryOnyNdiWyCiOOsK0lRasJ82np/w5l9XEXaAZssw4=; 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AJvYcCUSycOpiHnNmI7CxEfKHCiZY5UWJChcKNA4anUMC691nSFR7gJXqcboD+/mcKoYXrYs23OG3fCcXsYvQuQlk9u1b5bh@vger.kernel.org X-Gm-Message-State: AOJu0YzGmv/cZULFrgFUAwvJMt9Z2aMsTRcPRNVy7yHAunJFhWSRIJlF U2c/1jq+iS60zdG1loB1x2B6+gq15Im/jDJuJLBwE4gS8lXtqahApQRUT3gUcQLLQI8BWTuIIMi v8tsmElyLou51pA== X-Google-Smtp-Source: AGHT+IHjs6fU9ID4XekBygu4qpGC/paqaxDgn1Rv4wwNJ+wwvsZBJcgiJbkad/eSq9rbZyy9KYLGzBwmWXPh+8k= X-Received: from mmaslanka2.c.googlers.com ([fda3:e722:ac3:cc00:31:98fb:c0a8:b8d]) (user=mmaslanka job=sendgmr) by 2002:a25:2bc8:0:b0:e0b:ab63:b9c7 with SMTP id 3f1490d57ef6-e0eb9a4606amr3324276.7.1723209235532; Fri, 09 Aug 2024 06:13:55 -0700 (PDT) Date: Fri, 9 Aug 2024 13:13:33 +0000 In-Reply-To: <20240809131343.1173369-1-mmaslanka@google.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <28567169-4588-002d-85b8-906d22f12f05@linux.intel.com> <20240809131343.1173369-1-mmaslanka@google.com> X-Mailer: git-send-email 2.46.0.76.ge559c4bf1a-goog Message-ID: <20240809131343.1173369-2-mmaslanka@google.com> Subject: [PATCH v4 2/2] platform/x86:intel/pmc: Enable the ACPI PM Timer to be turned off when suspended From: Marek Maslanka To: LKML Cc: Marek Maslanka , Daniel Lezcano , Thomas Gleixner , Rajneesh Bhardwaj , David E Box , Hans de Goede , " =?utf-8?q?Ilpo_J=C3=A4rvinen?= " , platform-driver-x86@vger.kernel.org Allow to disable ACPI PM Timer on suspend and enable on resume. A disabled timer helps optimise power consumption when the system is suspended. On resume the timer is only reactivated if it was activated prior to suspend, so unless the ACPI PM timer is enabled in the BIOS, this won't change anything. The ACPI PM timer is used by Intel's iTCO/wdat_wdt watchdog to drive the watchdog, so it doesn't need to run during suspend. Signed-off-by: Marek Maslanka --- Changes in v4: - Enable/disable ACPI PM Timer with the clocksource resume/suspend process instead of during pmc_core resume/suspend. Use added callback in acpi_pm to do this. - Do not rely on current set clocksource to check if ACPI PM Timer can be disabled. - Link to v3: https://lore.kernel.org/lkml/20240730120546.1042515-1-mmaslanka@google.com/ --- --- drivers/platform/x86/intel/pmc/adl.c | 2 ++ drivers/platform/x86/intel/pmc/cnp.c | 2 ++ drivers/platform/x86/intel/pmc/core.c | 49 +++++++++++++++++++++++++++ drivers/platform/x86/intel/pmc/core.h | 8 +++++ drivers/platform/x86/intel/pmc/icl.c | 2 ++ drivers/platform/x86/intel/pmc/mtl.c | 2 ++ drivers/platform/x86/intel/pmc/spt.c | 2 ++ drivers/platform/x86/intel/pmc/tgl.c | 2 ++ 8 files changed, 69 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/adl.c b/drivers/platform/x86/intel/pmc/adl.c index e7878558fd909..9d9c07f44ff61 100644 --- a/drivers/platform/x86/intel/pmc/adl.c +++ b/drivers/platform/x86/intel/pmc/adl.c @@ -295,6 +295,8 @@ const struct pmc_reg_map adl_reg_map = { .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES, .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, + .acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET, + .acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE, .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, .lpm_num_modes = ADL_LPM_NUM_MODES, .lpm_num_maps = ADL_LPM_NUM_MAPS, diff --git a/drivers/platform/x86/intel/pmc/cnp.c b/drivers/platform/x86/intel/pmc/cnp.c index dd72974bf71e2..513c02670c5aa 100644 --- a/drivers/platform/x86/intel/pmc/cnp.c +++ b/drivers/platform/x86/intel/pmc/cnp.c @@ -200,6 +200,8 @@ const struct pmc_reg_map cnp_reg_map = { .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES, .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, + .acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET, + .acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE, .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED, .etr3_offset = ETR3_OFFSET, }; diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index 10c96c1a850af..f6a29530347bb 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -29,6 +29,7 @@ #include "core.h" #include "../pmt/telemetry.h" +#include "../../../../clocksource/acpi_pm.h" /* Maximum number of modes supported by platfoms that has low power mode capability */ const char *pmc_lpm_modes[] = { @@ -1171,6 +1172,42 @@ static bool pmc_core_is_pson_residency_enabled(struct pmc_dev *pmcdev) return val == 1; } +/** + * Enable or disable ACPI PM Timer + * + * This function is intended to be a callback for ACPI PM suspend/resume event. + * The ACPI PM Timer is enabled on resume only if it was enabled during suspend. + */ +static void pmc_core_acpi_pm_timer_suspend_resume(void *data, bool suspend) +{ + struct pmc_dev *pmcdev = data; + struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_reg_map *map = pmc->map; + bool enabled; + u32 reg; + + if (!map->acpi_pm_tmr_ctl_offset) + return; + + mutex_lock(&pmcdev->lock); + + if (!suspend && !pmcdev->enable_acpi_pm_timer_on_resume) { + mutex_unlock(&pmcdev->lock); + return; + } + + reg = pmc_core_reg_read(pmc, map->acpi_pm_tmr_ctl_offset); + enabled = !(reg & map->acpi_pm_tmr_disable_bit); + if (suspend) + reg |= map->acpi_pm_tmr_disable_bit; + else + reg &= ~map->acpi_pm_tmr_disable_bit; + pmc_core_reg_write(pmc, map->acpi_pm_tmr_ctl_offset, reg); + + pmcdev->enable_acpi_pm_timer_on_resume = suspend && enabled; + + mutex_unlock(&pmcdev->lock); +} static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev) { @@ -1362,6 +1399,7 @@ static int pmc_core_probe(struct platform_device *pdev) struct pmc_dev *pmcdev; const struct x86_cpu_id *cpu_id; int (*core_init)(struct pmc_dev *pmcdev); + const struct pmc_reg_map *map; struct pmc *primary_pmc; int ret; @@ -1420,6 +1458,11 @@ static int pmc_core_probe(struct platform_device *pdev) pm_report_max_hw_sleep(FIELD_MAX(SLP_S0_RES_COUNTER_MASK) * pmc_core_adjust_slp_s0_step(primary_pmc, 1)); + map = primary_pmc->map; + if (map->acpi_pm_tmr_ctl_offset) + acpi_pm_register_suspend_resume_callback(pmc_core_acpi_pm_timer_suspend_resume, + pmcdev); + device_initialized = true; dev_info(&pdev->dev, " initialized\n"); @@ -1429,6 +1472,12 @@ static int pmc_core_probe(struct platform_device *pdev) static void pmc_core_remove(struct platform_device *pdev) { struct pmc_dev *pmcdev = platform_get_drvdata(pdev); + const struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_reg_map *map = pmc->map; + + if (map->acpi_pm_tmr_ctl_offset) + acpi_pm_register_suspend_resume_callback(NULL, NULL); + pmc_core_dbgfs_unregister(pmcdev); pmc_core_clean_structure(pdev); } diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index 83504c49a0e31..fe1a94f693b63 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -67,6 +67,8 @@ struct telem_endpoint; #define SPT_PMC_LTR_SCC 0x3A0 #define SPT_PMC_LTR_ISH 0x3A4 +#define SPT_PMC_ACPI_PM_TMR_CTL_OFFSET 0x18FC + /* Sunrise Point: PGD PFET Enable Ack Status Registers */ enum ppfear_regs { SPT_PMC_XRAM_PPFEAR0A = 0x590, @@ -147,6 +149,8 @@ enum ppfear_regs { #define SPT_PMC_VRIC1_SLPS0LVEN BIT(13) #define SPT_PMC_VRIC1_XTALSDQDIS BIT(22) +#define SPT_PMC_BIT_ACPI_PM_TMR_DISABLE BIT(1) + /* Cannonlake Power Management Controller register offsets */ #define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4 #define CNP_PMC_PM_CFG_OFFSET 0x1818 @@ -344,6 +348,8 @@ struct pmc_reg_map { const u8 *lpm_reg_index; const u32 pson_residency_offset; const u32 pson_residency_counter_step; + const u32 acpi_pm_tmr_ctl_offset; + const u32 acpi_pm_tmr_disable_bit; }; /** @@ -417,6 +423,8 @@ struct pmc_dev { u32 die_c6_offset; struct telem_endpoint *punit_ep; struct pmc_info *regmap_list; + + bool enable_acpi_pm_timer_on_resume; }; enum pmc_index { diff --git a/drivers/platform/x86/intel/pmc/icl.c b/drivers/platform/x86/intel/pmc/icl.c index 71b0fd6cb7d84..cbbd440544688 100644 --- a/drivers/platform/x86/intel/pmc/icl.c +++ b/drivers/platform/x86/intel/pmc/icl.c @@ -46,6 +46,8 @@ const struct pmc_reg_map icl_reg_map = { .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES, .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, + .acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET, + .acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE, .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED, .etr3_offset = ETR3_OFFSET, }; diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c index c7d15d864039d..91f2fa728f5c8 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -462,6 +462,8 @@ const struct pmc_reg_map mtl_socm_reg_map = { .ppfear_buckets = MTL_SOCM_PPFEAR_NUM_ENTRIES, .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, + .acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET, + .acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE, .lpm_num_maps = ADL_LPM_NUM_MAPS, .ltr_ignore_max = MTL_SOCM_NUM_IP_IGN_ALLOWED, .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, diff --git a/drivers/platform/x86/intel/pmc/spt.c b/drivers/platform/x86/intel/pmc/spt.c index ab993a69e33ee..2cd2b3c68e468 100644 --- a/drivers/platform/x86/intel/pmc/spt.c +++ b/drivers/platform/x86/intel/pmc/spt.c @@ -130,6 +130,8 @@ const struct pmc_reg_map spt_reg_map = { .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES, .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT, + .acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET, + .acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE, .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED, .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET, }; diff --git a/drivers/platform/x86/intel/pmc/tgl.c b/drivers/platform/x86/intel/pmc/tgl.c index e0580de180773..371b4e30f1426 100644 --- a/drivers/platform/x86/intel/pmc/tgl.c +++ b/drivers/platform/x86/intel/pmc/tgl.c @@ -197,6 +197,8 @@ const struct pmc_reg_map tgl_reg_map = { .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES, .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, + .acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET, + .acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE, .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED, .lpm_num_maps = TGL_LPM_NUM_MAPS, .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,