From patchwork Mon Aug 12 13:48:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Veerasooran X-Patchwork-Id: 13760622 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9005B17B43F; Mon, 12 Aug 2024 13:49:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723470558; cv=none; b=RZDDDGeJgLy9nIAtWZiY8ewEbjznSVYpNcnKNLGI5rwrASMT8Ewmtx0Pk1teGu1Bxrp2Rm+D0qhzno0ZjDjZT4+LYfAUtyCNCPFbLqQJr4jaBkmlo7b7f3hq6bIf4ks/46CrwKdRlILFWo4O4KX5IuxFuplwVcl57tfyo20AbO4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723470558; c=relaxed/simple; bh=qJvFk7/dLkH9pUjzhXC38WRDHiuSnNUM7hFPIYxK5sg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uubY62PVmM3fEMruPMgLj5y33HN2raZ9sp1GgpWF/4Wu7SBlLgTtQeWUID/cmNGLMZ+ysvZTSyUjjz8KBJ1hAOPyY5dXFUtWOBGYenvu2L6aRCFMdb21lxN3nyrB4ma8LMdepRA0Zk3L4Ux12GDcCMVFqamEoQw8edJFAuqoKEs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=KjRs5GXy; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="KjRs5GXy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1723470556; x=1755006556; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qJvFk7/dLkH9pUjzhXC38WRDHiuSnNUM7hFPIYxK5sg=; b=KjRs5GXys/E53BcuScEJJ8eOgGdCESxr3xP/N1oNlJmlkiu94fDVkxjL qkrO3HZt8EzqOPNMSiwkHM9FbF4FXCYC/dD/CkNIehNTbeFGTRtcipZes JZHGJW9pVd3dMMc16fcOjmVAxg4aYaREibMFNCJQgJEbjwmfXweZd33SH xQ+kF32wIgXuYaLnT5GgRork8gSIY0N22d0BJNsjxuCCgAzspiEKnOt3a pdiHP/Apbn9/rxRKewdCbN0z91VotfyIQVED3bIa8E4bodpRuo9b0AA4W KmbO7OLTnRgY8Zw6Ne5VcjZUEq0A+Z/etCZugCKTgNst1sRoA42cMVC5e Q==; X-CSE-ConnectionGUID: kPkSNNkqRiKssk122yqRMw== X-CSE-MsgGUID: vJZ6G1iQRXW0TzG2O+F7QA== X-IronPort-AV: E=Sophos;i="6.09,283,1716274800"; d="scan'208";a="31049488" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 12 Aug 2024 06:49:15 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 12 Aug 2024 06:48:48 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 12 Aug 2024 06:48:44 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , , , , Parthiban Veerasooran Subject: [PATCH net-next 1/7] net: phy: microchip_t1s: restructure cfg read/write functions arguments Date: Mon, 12 Aug 2024 19:18:10 +0530 Message-ID: <20240812134816.380688-2-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> References: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This patch restructures lan865x_write_cfg_params() and lan865x_read_cfg_params() functions arguments to more generic which will be useful for the next patch which updates the improved initial configuration for LAN8650/1 Rev.B0 published in the Configuration Note. Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 41 ++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c index 534ca7d1b061..373a8b8da5ee 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -112,7 +112,7 @@ static int lan865x_revb0_indirect_read(struct phy_device *phydev, u16 addr) /* This is pulled straight from AN1760 from 'calculation of offset 1' & * 'calculation of offset 2' */ -static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[2]) +static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[]) { const u16 fixup_regs[2] = {0x0004, 0x0008}; int ret; @@ -130,13 +130,15 @@ static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[2] return 0; } -static int lan865x_read_cfg_params(struct phy_device *phydev, u16 cfg_params[]) +static int lan865x_read_cfg_params(struct phy_device *phydev, + const u16 cfg_regs[], u16 cfg_params[], + u8 count) { int ret; - for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) { + for (int i = 0; i < count; i++) { ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, - lan865x_revb0_fixup_cfg_regs[i]); + cfg_regs[i]); if (ret < 0) return ret; cfg_params[i] = (u16)ret; @@ -145,13 +147,14 @@ static int lan865x_read_cfg_params(struct phy_device *phydev, u16 cfg_params[]) return 0; } -static int lan865x_write_cfg_params(struct phy_device *phydev, u16 cfg_params[]) +static int lan865x_write_cfg_params(struct phy_device *phydev, + const u16 cfg_regs[], u16 cfg_params[], + u8 count) { int ret; - for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) { - ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, - lan865x_revb0_fixup_cfg_regs[i], + for (int i = 0; i < count; i++) { + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, cfg_regs[i], cfg_params[i]); if (ret) return ret; @@ -160,18 +163,14 @@ static int lan865x_write_cfg_params(struct phy_device *phydev, u16 cfg_params[]) return 0; } -static int lan865x_setup_cfgparam(struct phy_device *phydev) +static int lan865x_setup_cfgparam(struct phy_device *phydev, s8 offsets[]) { + u16 cfg_results[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)]; u16 cfg_params[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)]; - u16 cfg_results[5]; - s8 offsets[2]; int ret; - ret = lan865x_generate_cfg_offsets(phydev, offsets); - if (ret) - return ret; - - ret = lan865x_read_cfg_params(phydev, cfg_params); + ret = lan865x_read_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + cfg_params, ARRAY_SIZE(cfg_params)); if (ret) return ret; @@ -190,16 +189,22 @@ static int lan865x_setup_cfgparam(struct phy_device *phydev) FIELD_PREP(GENMASK(15, 8), 17 + offsets[0]) | (22 + offsets[0]); - return lan865x_write_cfg_params(phydev, cfg_results); + return lan865x_write_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + cfg_results, ARRAY_SIZE(cfg_results)); } static int lan865x_revb0_config_init(struct phy_device *phydev) { + s8 offsets[2]; int ret; /* Reference to AN1760 * https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8650-1-Configuration-60001760.pdf */ + ret = lan865x_generate_cfg_offsets(phydev, offsets); + if (ret) + return ret; + for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_registers); i++) { ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, lan865x_revb0_fixup_registers[i], @@ -210,7 +215,7 @@ static int lan865x_revb0_config_init(struct phy_device *phydev) /* Function to calculate and write the configuration parameters in the * 0x0084, 0x008A, 0x00AD, 0x00AE and 0x00AF registers (from AN1760) */ - return lan865x_setup_cfgparam(phydev); + return lan865x_setup_cfgparam(phydev, offsets); } static int lan867x_revb1_config_init(struct phy_device *phydev) From patchwork Mon Aug 12 13:48:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Veerasooran X-Patchwork-Id: 13760625 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1152D17C7C3; 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X-CSE-ConnectionGUID: yI+1XPNJS2+OYumvWzLkww== X-CSE-MsgGUID: kSgf8UN+Rriw6bpyTas3KA== X-IronPort-AV: E=Sophos;i="6.09,283,1716274800"; d="scan'208";a="31049504" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 12 Aug 2024 06:49:16 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 12 Aug 2024 06:48:53 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 12 Aug 2024 06:48:49 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , , , , Parthiban Veerasooran Subject: [PATCH net-next 2/7] net: phy: microchip_t1s: update new initial settings for LAN865X Rev.B0 Date: Mon, 12 Aug 2024 19:18:11 +0530 Message-ID: <20240812134816.380688-3-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> References: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This patch configures the new/improved initial settings from the latest configuration application note released for LAN8650/1 Rev.B0 Revision F (DS60001760G - June 2024). Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 109 +++++++++++++++++++++++--------- 1 file changed, 78 insertions(+), 31 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c index 373a8b8da5ee..51ff97ffad0e 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -59,29 +59,45 @@ static const u16 lan867x_revb1_fixup_masks[12] = { 0x0600, 0x7F00, 0x2000, 0xFFFF, }; -/* LAN865x Rev.B0 configuration parameters from AN1760 */ -static const u32 lan865x_revb0_fixup_registers[28] = { - 0x0091, 0x0081, 0x0043, 0x0044, - 0x0045, 0x0053, 0x0054, 0x0055, - 0x0040, 0x0050, 0x00D0, 0x00E9, - 0x00F5, 0x00F4, 0x00F8, 0x00F9, +/* LAN865x Rev.B0 configuration parameters from AN1760 + * As per the Configuration Application Note AN1760 published in the below link, + * https://www.microchip.com/en-us/application-notes/an1760 + * Revision F (DS60001760G - June 2024) + */ +static const u32 lan865x_revb0_fixup_registers[17] = { + 0x00D0, 0x00E0, 0x00E9, 0x00F5, + 0x00F4, 0x00F8, 0x00F9, 0x0081, + 0x0091, 0x0043, 0x0044, 0x0045, + 0x0053, 0x0054, 0x0055, 0x0040, + 0x0050, +}; + +static const u16 lan865x_revb0_fixup_values[17] = { + 0x3F31, 0xC000, 0x9E50, 0x1CF8, + 0xC020, 0xB900, 0x4E53, 0x0080, + 0x9660, 0x00FF, 0xFFFF, 0x0000, + 0x00FF, 0xFFFF, 0x0000, 0x0002, + 0x0002, +}; + +static const u16 lan865x_revb0_fixup_cfg_regs[2] = { + 0x0084, 0x008A, +}; + +static const u32 lan865x_revb0_sqi_fixup_regs[12] = { 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, 0x00B8, 0x00B9, 0x00BA, 0x00BB, }; -static const u16 lan865x_revb0_fixup_values[28] = { - 0x9660, 0x00C0, 0x00FF, 0xFFFF, - 0x0000, 0x00FF, 0xFFFF, 0x0000, - 0x0002, 0x0002, 0x5F21, 0x9E50, - 0x1CF8, 0xC020, 0x9B00, 0x4E53, +static const u16 lan865x_revb0_sqi_fixup_values[12] = { 0x0103, 0x0910, 0x1D26, 0x002A, 0x0103, 0x070D, 0x1720, 0x0027, 0x0509, 0x0E13, 0x1C25, 0x002B, }; -static const u16 lan865x_revb0_fixup_cfg_regs[5] = { - 0x0084, 0x008A, 0x00AD, 0x00AE, 0x00AF +static const u16 lan865x_revb0_sqi_fixup_cfg_regs[3] = { + 0x00AD, 0x00AE, 0x00AF, }; /* Pulled from AN1760 describing 'indirect read' @@ -121,6 +137,8 @@ static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[]) ret = lan865x_revb0_indirect_read(phydev, fixup_regs[i]); if (ret < 0) return ret; + + ret &= 0x1F; if (ret & BIT(4)) offsets[i] = ret | 0xE0; else @@ -174,25 +192,38 @@ static int lan865x_setup_cfgparam(struct phy_device *phydev, s8 offsets[]) if (ret) return ret; - cfg_results[0] = (cfg_params[0] & 0x000F) | - FIELD_PREP(GENMASK(15, 10), 9 + offsets[0]) | - FIELD_PREP(GENMASK(15, 4), 14 + offsets[0]); - cfg_results[1] = (cfg_params[1] & 0x03FF) | - FIELD_PREP(GENMASK(15, 10), 40 + offsets[1]); - cfg_results[2] = (cfg_params[2] & 0xC0C0) | - FIELD_PREP(GENMASK(15, 8), 5 + offsets[0]) | - (9 + offsets[0]); - cfg_results[3] = (cfg_params[3] & 0xC0C0) | - FIELD_PREP(GENMASK(15, 8), 9 + offsets[0]) | - (14 + offsets[0]); - cfg_results[4] = (cfg_params[4] & 0xC0C0) | - FIELD_PREP(GENMASK(15, 8), 17 + offsets[0]) | - (22 + offsets[0]); + cfg_results[0] = FIELD_PREP(GENMASK(15, 10), (9 + offsets[0]) & 0x3F) | + FIELD_PREP(GENMASK(15, 4), (14 + offsets[0]) & 0x3F) | + 0x03; + cfg_results[1] = FIELD_PREP(GENMASK(15, 10), (40 + offsets[1]) & 0x3F); return lan865x_write_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, cfg_results, ARRAY_SIZE(cfg_results)); } +static int lan865x_setup_sqi_cfgparam(struct phy_device *phydev, s8 offsets[]) +{ + u16 cfg_results[ARRAY_SIZE(lan865x_revb0_sqi_fixup_cfg_regs)]; + u16 cfg_params[ARRAY_SIZE(lan865x_revb0_sqi_fixup_cfg_regs)]; + int ret; + + ret = lan865x_read_cfg_params(phydev, lan865x_revb0_sqi_fixup_cfg_regs, + cfg_params, ARRAY_SIZE(cfg_params)); + if (ret) + return ret; + + cfg_results[0] = FIELD_PREP(GENMASK(15, 8), (5 + offsets[0]) & 0x3F) | + ((9 + offsets[0]) & 0x3F); + cfg_results[1] = FIELD_PREP(GENMASK(15, 8), (9 + offsets[0]) & 0x3F) | + ((14 + offsets[0]) & 0x3F); + cfg_results[2] = FIELD_PREP(GENMASK(15, 8), (17 + offsets[0]) & 0x3F) | + ((22 + offsets[0]) & 0x3F); + + return lan865x_write_cfg_params(phydev, + lan865x_revb0_sqi_fixup_cfg_regs, + cfg_results, ARRAY_SIZE(cfg_results)); +} + static int lan865x_revb0_config_init(struct phy_device *phydev) { s8 offsets[2]; @@ -211,11 +242,27 @@ static int lan865x_revb0_config_init(struct phy_device *phydev) lan865x_revb0_fixup_values[i]); if (ret) return ret; + + if (i == 2) { + ret = lan865x_setup_cfgparam(phydev, offsets); + if (ret) + return ret; + } } - /* Function to calculate and write the configuration parameters in the - * 0x0084, 0x008A, 0x00AD, 0x00AE and 0x00AF registers (from AN1760) - */ - return lan865x_setup_cfgparam(phydev, offsets); + + ret = lan865x_setup_sqi_cfgparam(phydev, offsets); + if (ret) + return ret; + + for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_sqi_fixup_regs); i++) { + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan865x_revb0_sqi_fixup_regs[i], + lan865x_revb0_sqi_fixup_values[i]); + if (ret) + return ret; + } + + return 0; } static int lan867x_revb1_config_init(struct phy_device *phydev) From patchwork Mon Aug 12 13:48:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Veerasooran X-Patchwork-Id: 13760623 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E06A753370; 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X-CSE-ConnectionGUID: kPkSNNkqRiKssk122yqRMw== X-CSE-MsgGUID: +cN3otFkQYe3CpLDrgoVsQ== X-IronPort-AV: E=Sophos;i="6.09,283,1716274800"; d="scan'208";a="31049500" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 12 Aug 2024 06:49:16 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 12 Aug 2024 06:48:58 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 12 Aug 2024 06:48:54 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , , , , Parthiban Veerasooran Subject: [PATCH net-next 3/7] net: phy: microchip_t1s: add support for Microchip's LAN865X Rev.B1 Date: Mon, 12 Aug 2024 19:18:12 +0530 Message-ID: <20240812134816.380688-4-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> References: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This patch adds support for LAN8650/1 Rev.B1. As per the latest configuration note AN1760 released (Revision F (DS60001760G - June 2024)) for Rev.B0 is also applicable for Rev.B1. Refer hardware revisions list in the latest AN1760. https://www.microchip.com/en-us/application-notes/an1760 Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/Kconfig | 4 +-- drivers/net/phy/microchip_t1s.c | 62 ++++++++++++++++----------------- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 7fddc8306d82..68db15d52355 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -282,8 +282,8 @@ config MICREL_PHY config MICROCHIP_T1S_PHY tristate "Microchip 10BASE-T1S Ethernet PHYs" help - Currently supports the LAN8670/1/2 Rev.B1 and LAN8650/1 Rev.B0 Internal - PHYs. + Currently supports the LAN8670/1/2 Rev.B1 and LAN8650/1 Rev.B0/B1 + Internal PHYs. config MICROCHIP_PHY tristate "Microchip PHYs" diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c index 51ff97ffad0e..187540ae95c0 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -4,7 +4,7 @@ * * Support: Microchip Phys: * lan8670/1/2 Rev.B1 - * lan8650/1 Rev.B0 Internal PHYs + * lan8650/1 Rev.B0/B1 Internal PHYs */ #include @@ -12,7 +12,8 @@ #include #define PHY_ID_LAN867X_REVB1 0x0007C162 -#define PHY_ID_LAN865X_REVB0 0x0007C1B3 +/* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation */ +#define PHY_ID_LAN865X_REVB 0x0007C1B3 #define LAN867X_REG_STS2 0x0019 @@ -59,12 +60,12 @@ static const u16 lan867x_revb1_fixup_masks[12] = { 0x0600, 0x7F00, 0x2000, 0xFFFF, }; -/* LAN865x Rev.B0 configuration parameters from AN1760 +/* LAN865x Rev.B0/B1 configuration parameters from AN1760 * As per the Configuration Application Note AN1760 published in the below link, * https://www.microchip.com/en-us/application-notes/an1760 * Revision F (DS60001760G - June 2024) */ -static const u32 lan865x_revb0_fixup_registers[17] = { +static const u32 lan865x_revb_fixup_registers[17] = { 0x00D0, 0x00E0, 0x00E9, 0x00F5, 0x00F4, 0x00F8, 0x00F9, 0x0081, 0x0091, 0x0043, 0x0044, 0x0045, @@ -72,7 +73,7 @@ static const u32 lan865x_revb0_fixup_registers[17] = { 0x0050, }; -static const u16 lan865x_revb0_fixup_values[17] = { +static const u16 lan865x_revb_fixup_values[17] = { 0x3F31, 0xC000, 0x9E50, 0x1CF8, 0xC020, 0xB900, 0x4E53, 0x0080, 0x9660, 0x00FF, 0xFFFF, 0x0000, @@ -80,23 +81,23 @@ static const u16 lan865x_revb0_fixup_values[17] = { 0x0002, }; -static const u16 lan865x_revb0_fixup_cfg_regs[2] = { +static const u16 lan865x_revb_fixup_cfg_regs[2] = { 0x0084, 0x008A, }; -static const u32 lan865x_revb0_sqi_fixup_regs[12] = { +static const u32 lan865x_revb_sqi_fixup_regs[12] = { 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, 0x00B8, 0x00B9, 0x00BA, 0x00BB, }; -static const u16 lan865x_revb0_sqi_fixup_values[12] = { +static const u16 lan865x_revb_sqi_fixup_values[12] = { 0x0103, 0x0910, 0x1D26, 0x002A, 0x0103, 0x070D, 0x1720, 0x0027, 0x0509, 0x0E13, 0x1C25, 0x002B, }; -static const u16 lan865x_revb0_sqi_fixup_cfg_regs[3] = { +static const u16 lan865x_revb_sqi_fixup_cfg_regs[3] = { 0x00AD, 0x00AE, 0x00AF, }; @@ -108,7 +109,7 @@ static const u16 lan865x_revb0_sqi_fixup_cfg_regs[3] = { * * 0x4 refers to memory map selector 4, which maps to MDIO_MMD_VEND2 */ -static int lan865x_revb0_indirect_read(struct phy_device *phydev, u16 addr) +static int lan865x_revb_indirect_read(struct phy_device *phydev, u16 addr) { int ret; @@ -134,7 +135,7 @@ static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[]) int ret; for (int i = 0; i < ARRAY_SIZE(fixup_regs); i++) { - ret = lan865x_revb0_indirect_read(phydev, fixup_regs[i]); + ret = lan865x_revb_indirect_read(phydev, fixup_regs[i]); if (ret < 0) return ret; @@ -183,11 +184,11 @@ static int lan865x_write_cfg_params(struct phy_device *phydev, static int lan865x_setup_cfgparam(struct phy_device *phydev, s8 offsets[]) { - u16 cfg_results[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)]; - u16 cfg_params[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)]; + u16 cfg_results[ARRAY_SIZE(lan865x_revb_fixup_cfg_regs)]; + u16 cfg_params[ARRAY_SIZE(lan865x_revb_fixup_cfg_regs)]; int ret; - ret = lan865x_read_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + ret = lan865x_read_cfg_params(phydev, lan865x_revb_fixup_cfg_regs, cfg_params, ARRAY_SIZE(cfg_params)); if (ret) return ret; @@ -197,17 +198,17 @@ static int lan865x_setup_cfgparam(struct phy_device *phydev, s8 offsets[]) 0x03; cfg_results[1] = FIELD_PREP(GENMASK(15, 10), (40 + offsets[1]) & 0x3F); - return lan865x_write_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + return lan865x_write_cfg_params(phydev, lan865x_revb_fixup_cfg_regs, cfg_results, ARRAY_SIZE(cfg_results)); } static int lan865x_setup_sqi_cfgparam(struct phy_device *phydev, s8 offsets[]) { - u16 cfg_results[ARRAY_SIZE(lan865x_revb0_sqi_fixup_cfg_regs)]; - u16 cfg_params[ARRAY_SIZE(lan865x_revb0_sqi_fixup_cfg_regs)]; + u16 cfg_results[ARRAY_SIZE(lan865x_revb_sqi_fixup_cfg_regs)]; + u16 cfg_params[ARRAY_SIZE(lan865x_revb_sqi_fixup_cfg_regs)]; int ret; - ret = lan865x_read_cfg_params(phydev, lan865x_revb0_sqi_fixup_cfg_regs, + ret = lan865x_read_cfg_params(phydev, lan865x_revb_sqi_fixup_cfg_regs, cfg_params, ARRAY_SIZE(cfg_params)); if (ret) return ret; @@ -219,12 +220,11 @@ static int lan865x_setup_sqi_cfgparam(struct phy_device *phydev, s8 offsets[]) cfg_results[2] = FIELD_PREP(GENMASK(15, 8), (17 + offsets[0]) & 0x3F) | ((22 + offsets[0]) & 0x3F); - return lan865x_write_cfg_params(phydev, - lan865x_revb0_sqi_fixup_cfg_regs, + return lan865x_write_cfg_params(phydev, lan865x_revb_sqi_fixup_cfg_regs, cfg_results, ARRAY_SIZE(cfg_results)); } -static int lan865x_revb0_config_init(struct phy_device *phydev) +static int lan865x_revb_config_init(struct phy_device *phydev) { s8 offsets[2]; int ret; @@ -236,10 +236,10 @@ static int lan865x_revb0_config_init(struct phy_device *phydev) if (ret) return ret; - for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_registers); i++) { + for (int i = 0; i < ARRAY_SIZE(lan865x_revb_fixup_registers); i++) { ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, - lan865x_revb0_fixup_registers[i], - lan865x_revb0_fixup_values[i]); + lan865x_revb_fixup_registers[i], + lan865x_revb_fixup_values[i]); if (ret) return ret; @@ -254,10 +254,10 @@ static int lan865x_revb0_config_init(struct phy_device *phydev) if (ret) return ret; - for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_sqi_fixup_regs); i++) { + for (int i = 0; i < ARRAY_SIZE(lan865x_revb_sqi_fixup_regs); i++) { ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, - lan865x_revb0_sqi_fixup_regs[i], - lan865x_revb0_sqi_fixup_values[i]); + lan865x_revb_sqi_fixup_regs[i], + lan865x_revb_sqi_fixup_values[i]); if (ret) return ret; } @@ -332,10 +332,10 @@ static struct phy_driver microchip_t1s_driver[] = { .get_plca_status = genphy_c45_plca_get_status, }, { - PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0), - .name = "LAN865X Rev.B0 Internal Phy", + PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB), + .name = "LAN865X Rev.B0/B1 Internal Phy", .features = PHY_BASIC_T1S_P2MP_FEATURES, - .config_init = lan865x_revb0_config_init, + .config_init = lan865x_revb_config_init, .read_status = lan86xx_read_status, .get_plca_cfg = genphy_c45_plca_get_cfg, .set_plca_cfg = genphy_c45_plca_set_cfg, @@ -347,7 +347,7 @@ module_phy_driver(microchip_t1s_driver); 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Mon, 12 Aug 2024 06:49:03 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 12 Aug 2024 06:48:59 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , , , , Parthiban Veerasooran Subject: [PATCH net-next 4/7] net: phy: microchip_t1s: move LAN867X reset handling to a new function Date: Mon, 12 Aug 2024 19:18:13 +0530 Message-ID: <20240812134816.380688-5-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> References: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This patch moves LAN867X reset handling code to a new function called lan867x_check_reset_complete() which will be useful for the next patch which also uses the same code to handle the reset functionality. Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c index 187540ae95c0..d0af02a25d01 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -265,7 +265,7 @@ static int lan865x_revb_config_init(struct phy_device *phydev) return 0; } -static int lan867x_revb1_config_init(struct phy_device *phydev) +static int lan867x_check_reset_complete(struct phy_device *phydev) { int err; @@ -287,6 +287,17 @@ static int lan867x_revb1_config_init(struct phy_device *phydev) } } + return 0; +} + +static int lan867x_revb1_config_init(struct phy_device *phydev) +{ + int err; + + err = lan867x_check_reset_complete(phydev); + if (err) + return err; + /* Reference to AN1699 * https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf * AN1699 says Read, Modify, Write, but the Write is not required if the From patchwork Mon Aug 12 13:48:14 2024 Content-Type: text/plain; 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Mon, 12 Aug 2024 06:49:03 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , , , , Parthiban Veerasooran Subject: [PATCH net-next 5/7] net: phy: microchip_t1s: add support for Microchip's LAN867X Rev.C1 Date: Mon, 12 Aug 2024 19:18:14 +0530 Message-ID: <20240812134816.380688-6-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> References: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This patch adds support for LAN8670/1/2 Rev.C1 as per the latest configuration note AN1699 released (Revision E (DS60001699F - June 2024)) https://www.microchip.com/en-us/application-notes/an1699 Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/Kconfig | 2 +- drivers/net/phy/microchip_t1s.c | 68 ++++++++++++++++++++++++++++++++- 2 files changed, 67 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 68db15d52355..63b45544c191 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -282,7 +282,7 @@ config MICREL_PHY config MICROCHIP_T1S_PHY tristate "Microchip 10BASE-T1S Ethernet PHYs" help - Currently supports the LAN8670/1/2 Rev.B1 and LAN8650/1 Rev.B0/B1 + Currently supports the LAN8670/1/2 Rev.B1/C1 and LAN8650/1 Rev.B0/B1 Internal PHYs. config MICROCHIP_PHY diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c index d0af02a25d01..62f5ce548c6a 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -3,7 +3,7 @@ * Driver for Microchip 10BASE-T1S PHYs * * Support: Microchip Phys: - * lan8670/1/2 Rev.B1 + * lan8670/1/2 Rev.B1/C1 * lan8650/1 Rev.B0/B1 Internal PHYs */ @@ -12,6 +12,7 @@ #include #define PHY_ID_LAN867X_REVB1 0x0007C162 +#define PHY_ID_LAN867X_REVC1 0x0007C164 /* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation */ #define PHY_ID_LAN865X_REVB 0x0007C1B3 @@ -243,7 +244,7 @@ static int lan865x_revb_config_init(struct phy_device *phydev) if (ret) return ret; - if (i == 2) { + if (i == 1) { ret = lan865x_setup_cfgparam(phydev, offsets); if (ret) return ret; @@ -290,6 +291,58 @@ static int lan867x_check_reset_complete(struct phy_device *phydev) return 0; } +static int lan867x_revc1_config_init(struct phy_device *phydev) +{ + s8 offsets[2]; + int ret; + + ret = lan867x_check_reset_complete(phydev); + if (ret) + return ret; + + ret = lan865x_generate_cfg_offsets(phydev, offsets); + if (ret) + return ret; + + /* LAN867x Rev.C1 configuration settings are equal to the first 9 + * configuration settings and all the sqi fixup settings from LAN865x + * Rev.B0/B1. So the same fixup registers and values from LAN865x + * Rev.B0/B1 are used for LAN867x Rev.C1 to avoid duplication. + * Refer the below links for the comparision. + * https://www.microchip.com/en-us/application-notes/an1760 + * Revision F (DS60001760G - June 2024) + * https://www.microchip.com/en-us/application-notes/an1699 + * Revision E (DS60001699F - June 2024) + */ + for (int i = 0; i < 9; i++) { + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan865x_revb_fixup_registers[i], + lan865x_revb_fixup_values[i]); + if (ret) + return ret; + + if (i == 1) { + ret = lan865x_setup_cfgparam(phydev, offsets); + if (ret) + return ret; + } + } + + ret = lan865x_setup_sqi_cfgparam(phydev, offsets); + if (ret) + return ret; + + for (int i = 0; i < ARRAY_SIZE(lan865x_revb_sqi_fixup_regs); i++) { + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan865x_revb_sqi_fixup_regs[i], + lan865x_revb_sqi_fixup_values[i]); + if (ret) + return ret; + } + + return 0; +} + static int lan867x_revb1_config_init(struct phy_device *phydev) { int err; @@ -342,6 +395,16 @@ static struct phy_driver microchip_t1s_driver[] = { .set_plca_cfg = genphy_c45_plca_set_cfg, .get_plca_status = genphy_c45_plca_get_status, }, + { + PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1), + .name = "LAN867X Rev.C1", + .features = PHY_BASIC_T1S_P2MP_FEATURES, + .config_init = lan867x_revc1_config_init, + .read_status = lan86xx_read_status, + .get_plca_cfg = genphy_c45_plca_get_cfg, + .set_plca_cfg = genphy_c45_plca_set_cfg, + .get_plca_status = genphy_c45_plca_get_status, + }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB), .name = "LAN865X Rev.B0/B1 Internal Phy", @@ -358,6 +421,7 @@ module_phy_driver(microchip_t1s_driver); static struct mdio_device_id __maybe_unused tbl[] = { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) }, + { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1) }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB) }, { } }; From patchwork Mon Aug 12 13:48:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Veerasooran X-Patchwork-Id: 13760627 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AB5517D340; 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X-CSE-ConnectionGUID: yI+1XPNJS2+OYumvWzLkww== X-CSE-MsgGUID: Xq2ba6JoSMyo37qJDjg+Cw== X-IronPort-AV: E=Sophos;i="6.09,283,1716274800"; d="scan'208";a="31049519" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 12 Aug 2024 06:49:18 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 12 Aug 2024 06:49:12 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 12 Aug 2024 06:49:08 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , , , , Parthiban Veerasooran Subject: [PATCH net-next 6/7] net: phy: microchip_t1s: add support for Microchip's LAN867X Rev.C2 Date: Mon, 12 Aug 2024 19:18:15 +0530 Message-ID: <20240812134816.380688-7-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> References: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This patch adds support for LAN8670/1/2 Rev.C2 as per the latest configuration note AN1699 released (Revision E (DS60001699F - June 2024)) for Rev.C1 is also applicable for Rev.C2. Refer hardware revisions list in the latest AN1699 Revision E (DS60001699F - June 2024). https://www.microchip.com/en-us/application-notes/an1699 Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/Kconfig | 4 ++-- drivers/net/phy/microchip_t1s.c | 22 +++++++++++++++++----- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 63b45544c191..cf6ddb7072d7 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -282,8 +282,8 @@ config MICREL_PHY config MICROCHIP_T1S_PHY tristate "Microchip 10BASE-T1S Ethernet PHYs" help - Currently supports the LAN8670/1/2 Rev.B1/C1 and LAN8650/1 Rev.B0/B1 - Internal PHYs. + Currently supports the LAN8670/1/2 Rev.B1/C1/C2 and + LAN8650/1 Rev.B0/B1 Internal PHYs. config MICROCHIP_PHY tristate "Microchip PHYs" diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c index 62f5ce548c6a..bd0c768df0af 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -3,7 +3,7 @@ * Driver for Microchip 10BASE-T1S PHYs * * Support: Microchip Phys: - * lan8670/1/2 Rev.B1/C1 + * lan8670/1/2 Rev.B1/C1/C2 * lan8650/1 Rev.B0/B1 Internal PHYs */ @@ -13,6 +13,7 @@ #define PHY_ID_LAN867X_REVB1 0x0007C162 #define PHY_ID_LAN867X_REVC1 0x0007C164 +#define PHY_ID_LAN867X_REVC2 0x0007C165 /* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation */ #define PHY_ID_LAN865X_REVB 0x0007C1B3 @@ -291,7 +292,7 @@ static int lan867x_check_reset_complete(struct phy_device *phydev) return 0; } -static int lan867x_revc1_config_init(struct phy_device *phydev) +static int lan867x_revc_config_init(struct phy_device *phydev) { s8 offsets[2]; int ret; @@ -304,10 +305,10 @@ static int lan867x_revc1_config_init(struct phy_device *phydev) if (ret) return ret; - /* LAN867x Rev.C1 configuration settings are equal to the first 9 + /* LAN867x Rev.C1/C2 configuration settings are equal to the first 9 * configuration settings and all the sqi fixup settings from LAN865x * Rev.B0/B1. So the same fixup registers and values from LAN865x - * Rev.B0/B1 are used for LAN867x Rev.C1 to avoid duplication. + * Rev.B0/B1 are used for LAN867x Rev.C1/C2 to avoid duplication. * Refer the below links for the comparision. * https://www.microchip.com/en-us/application-notes/an1760 * Revision F (DS60001760G - June 2024) @@ -399,7 +400,17 @@ static struct phy_driver microchip_t1s_driver[] = { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1), .name = "LAN867X Rev.C1", .features = PHY_BASIC_T1S_P2MP_FEATURES, - .config_init = lan867x_revc1_config_init, + .config_init = lan867x_revc_config_init, + .read_status = lan86xx_read_status, + .get_plca_cfg = genphy_c45_plca_get_cfg, + .set_plca_cfg = genphy_c45_plca_set_cfg, + .get_plca_status = genphy_c45_plca_get_status, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC2), + .name = "LAN867X Rev.C2", + .features = PHY_BASIC_T1S_P2MP_FEATURES, + .config_init = lan867x_revc_config_init, .read_status = lan86xx_read_status, .get_plca_cfg = genphy_c45_plca_get_cfg, .set_plca_cfg = genphy_c45_plca_set_cfg, @@ -422,6 +433,7 @@ module_phy_driver(microchip_t1s_driver); static struct mdio_device_id __maybe_unused tbl[] = { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1) }, + { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC2) }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB) }, { } }; From patchwork Mon Aug 12 13:48:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Veerasooran X-Patchwork-Id: 13760628 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3090617C7CE; Mon, 12 Aug 2024 13:49:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723470575; cv=none; b=cmJZV30WkvcA1SnXV3dFg35JVaPvuKm2O6alyfvSw8IwRWVaAy0XaLDT2OJDf/FxqlD1M9gzz3TTMaxaBtOwqLyunGQdT+HRqg1uuNHDS5KJoKbKZmNTPedh78E+0iJnk71OObmMrSOID0laMEtKmAKr7EewbhVR50YGB8fehQU= ARC-Message-Signature: i=1; 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Mon, 12 Aug 2024 06:49:17 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 12 Aug 2024 06:49:13 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , , , , Parthiban Veerasooran Subject: [PATCH net-next 7/7] net: phy: microchip_t1s: configure collision detection based on PLCA mode Date: Mon, 12 Aug 2024 19:18:16 +0530 Message-ID: <20240812134816.380688-8-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> References: <20240812134816.380688-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org As per LAN8650/1 Rev.B0/B1 AN1760 (Revision F (DS60001760G - June 2024)) and LAN8670/1/2 Rev.C1/C2 AN1699 (Revision E (DS60001699F - June 2024)), under normal operation, the device should be operated in PLCA mode. Disabling collision detection is recommended to allow the device to operate in noisy environments or when reflections and other inherent transmission line distortion cause poor signal quality. Collision detection must be re-enabled if the device is configured to operate in CSMA/CD mode. Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 42 ++++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c index bd0c768df0af..a0565508d7d2 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -26,6 +26,12 @@ #define LAN865X_REG_CFGPARAM_CTRL 0x00DA #define LAN865X_REG_STS2 0x0019 +/* Collision Detector Control 0 Register */ +#define LAN86XX_REG_COL_DET_CTRL0 0x0087 +#define COL_DET_CTRL0_ENABLE_BIT_MASK BIT(15) +#define COL_DET_ENABLE BIT(15) +#define COL_DET_DISABLE 0x0000 + #define LAN865X_CFGPARAM_READ_ENABLE BIT(1) /* The arrays below are pulled from the following table from AN1699 @@ -370,6 +376,36 @@ static int lan867x_revb1_config_init(struct phy_device *phydev) return 0; } +/* As per LAN8650/1 Rev.B0/B1 AN1760 (Revision F (DS60001760G - June 2024)) and + * LAN8670/1/2 Rev.C1/C2 AN1699 (Revision E (DS60001699F - June 2024)), under + * normal operation, the device should be operated in PLCA mode. Disabling + * collision detection is recommended to allow the device to operate in noisy + * environments or when reflections and other inherent transmission line + * distortion cause poor signal quality. Collision detection must be re-enabled + * if the device is configured to operate in CSMA/CD mode. + * + * AN1760: https://www.microchip.com/en-us/application-notes/an1760 + * AN1699: https://www.microchip.com/en-us/application-notes/an1699 + */ +static int lan86xx_plca_set_cfg(struct phy_device *phydev, + const struct phy_plca_cfg *plca_cfg) +{ + int ret; + + ret = genphy_c45_plca_set_cfg(phydev, plca_cfg); + if (ret) + return ret; + + if (plca_cfg->enabled) + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, + LAN86XX_REG_COL_DET_CTRL0, + COL_DET_CTRL0_ENABLE_BIT_MASK, + COL_DET_DISABLE); + + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_COL_DET_CTRL0, + COL_DET_CTRL0_ENABLE_BIT_MASK, COL_DET_ENABLE); +} + static int lan86xx_read_status(struct phy_device *phydev) { /* The phy has some limitations, namely: @@ -403,7 +439,7 @@ static struct phy_driver microchip_t1s_driver[] = { .config_init = lan867x_revc_config_init, .read_status = lan86xx_read_status, .get_plca_cfg = genphy_c45_plca_get_cfg, - .set_plca_cfg = genphy_c45_plca_set_cfg, + .set_plca_cfg = lan86xx_plca_set_cfg, .get_plca_status = genphy_c45_plca_get_status, }, { @@ -413,7 +449,7 @@ static struct phy_driver microchip_t1s_driver[] = { .config_init = lan867x_revc_config_init, .read_status = lan86xx_read_status, .get_plca_cfg = genphy_c45_plca_get_cfg, - .set_plca_cfg = genphy_c45_plca_set_cfg, + .set_plca_cfg = lan86xx_plca_set_cfg, .get_plca_status = genphy_c45_plca_get_status, }, { @@ -423,7 +459,7 @@ static struct phy_driver microchip_t1s_driver[] = { .config_init = lan865x_revb_config_init, .read_status = lan86xx_read_status, .get_plca_cfg = genphy_c45_plca_get_cfg, - .set_plca_cfg = genphy_c45_plca_set_cfg, + .set_plca_cfg = lan86xx_plca_set_cfg, .get_plca_status = genphy_c45_plca_get_status, }, };