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Thu, 15 Aug 2024 08:57:29 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 40xkmhenmp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:29 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vSVu029647; Thu, 15 Aug 2024 08:57:28 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vSEm029640 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:28 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id 8F6CB411DA; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 01/16] dt-bindings: dma: qcom,bam: Add bam pipe lock Date: Thu, 15 Aug 2024 14:27:10 +0530 Message-Id: <20240815085725.2740390-2-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dPzDTXje2zgTCvSf6rea3MW84dL_nyi4 X-Proofpoint-ORIG-GUID: dPzDTXje2zgTCvSf6rea3MW84dL_nyi4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 spamscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 BAM having pipe locking mechanism. The Lock and Un-Lock bit should be set on CMD descriptor only. Upon encountering a descriptor with Lock bit set, the BAM will lock all other pipes not related to the current pipe group, and keep handling the current pipe only until it sees the Un-Lock set. Signed-off-by: Md Sadre Alam --- Change in [v2] * Added initial support for dt-binding Change in [v1] * This patch was not included in [v1] Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 3ad0d9b1fbc5..91cc2942aa62 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -77,6 +77,12 @@ properties: Indicates that the bam is powered up by a remote processor but must be initialized by the local processor. + qcom,bam_pipe_lock: + type: boolean + description: + Indicates that the bam pipe needs locking or not based on client driver + sending the LOCK or UNLOK bit set on command descriptor. + reg: maxItems: 1 @@ -92,6 +98,8 @@ anyOf: - qcom,powered-remotely - required: - qcom,controlled-remotely + - required: + - qcom,bam_pipe_lock - required: - clocks - clock-names From patchwork Thu Aug 15 08:57:11 2024 Content-Type: text/plain; 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Thu, 15 Aug 2024 08:57:29 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vSF4029646; Thu, 15 Aug 2024 08:57:28 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vSe4029644 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:28 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id 932D3411EE; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 02/16] dmaengine: qcom: bam_dma: add bam_pipe_lock dt property Date: Thu, 15 Aug 2024 14:27:11 +0530 Message-Id: <20240815085725.2740390-3-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CkHHe18vFuWjsd4YAquZKZTbAof_vVln X-Proofpoint-ORIG-GUID: CkHHe18vFuWjsd4YAquZKZTbAof_vVln X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 bulkscore=0 clxscore=1011 phishscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 bam having locking and unlocking mechanism of bam pipes. Upon encountering a descriptor with Lock bit set, the BAM will lock all other pipes not related to the current pipe group, and keep handling the current pipe only until it sees the Un-Lock set , then it will release all locked pipes. The actual locking is done on the new descriptor fetching for publishing, i.e. locked pipe will not fetch new descriptors even if it got event/events adding more descriptors for this pipe. Adding the bam_pipe_lock flag in bam driver to handle Lock and Un-Lock bit set on command descriptor. Signed-off-by: Md Sadre Alam --- Change in [v2] * Added bam_pipe_lock dt property Change in [v1] * This patch was not included in [v1] drivers/dma/qcom/bam_dma.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 5e7d332731e0..1ac7e250bdaa 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -389,6 +389,7 @@ struct bam_device { u32 ee; bool controlled_remotely; bool powered_remotely; + bool bam_pipe_lock; u32 active_channels; const struct reg_offset_data *layout; @@ -1272,6 +1273,9 @@ static int bam_dma_probe(struct platform_device *pdev) bdev->powered_remotely = of_property_read_bool(pdev->dev.of_node, "qcom,powered-remotely"); + bdev->bam_pipe_lock = of_property_read_bool(pdev->dev.of_node, + "qcom,bam_pipe_lock"); + if (bdev->controlled_remotely || bdev->powered_remotely) bdev->bamclk = devm_clk_get_optional(bdev->dev, "bam_clk"); else From patchwork Thu Aug 15 08:57:12 2024 Content-Type: text/plain; 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Thu, 15 Aug 2024 08:57:29 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vSWL029645; Thu, 15 Aug 2024 08:57:28 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vSOU029643 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:28 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id 96F6041254; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 03/16] dmaengine: qcom: bam_dma: add LOCK & UNLOCK flag support Date: Thu, 15 Aug 2024 14:27:12 +0530 Message-Id: <20240815085725.2740390-4-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BCo9da2oaL2nPsP4y9QAtOnGpzMarqE- X-Proofpoint-ORIG-GUID: BCo9da2oaL2nPsP4y9QAtOnGpzMarqE- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 impostorscore=0 mlxlogscore=916 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Add lock and unlock flag support on command descriptor. Once lock set in requester pipe, then the bam controller will lock all others pipe and process the request only from requester pipe. Unlocking only can be performed from the same pipe. If DMA_PREP_LOCK flag passed in command descriptor then requester of this transaction wanted to lock the BAM controller for this transaction so BAM driver should set LOCK bit for the HW descriptor. If DMA_PREP_UNLOCK flag passed in command descriptor then requester of this transaction wanted to unlock the BAM controller.so BAM driver should set UNLOCK bit for the HW descriptor. Signed-off-by: Md Sadre Alam --- Change in [v2] * Added LOCK and UNLOCK flag in bam driver Change in [v1] * This patch was not included in [v1] drivers/dma/qcom/bam_dma.c | 10 +++++++++- include/linux/dmaengine.h | 6 ++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 1ac7e250bdaa..ab3b5319aa68 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -58,6 +58,8 @@ struct bam_desc_hw { #define DESC_FLAG_EOB BIT(13) #define DESC_FLAG_NWD BIT(12) #define DESC_FLAG_CMD BIT(11) +#define DESC_FLAG_LOCK BIT(10) +#define DESC_FLAG_UNLOCK BIT(9) struct bam_async_desc { struct virt_dma_desc vd; @@ -692,9 +694,15 @@ static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan, unsigned int curr_offset = 0; do { - if (flags & DMA_PREP_CMD) + if (flags & DMA_PREP_CMD) { desc->flags |= cpu_to_le16(DESC_FLAG_CMD); + if (bdev->bam_pipe_lock && flags & DMA_PREP_LOCK) + desc->flags |= cpu_to_le16(DESC_FLAG_LOCK); + else if (bdev->bam_pipe_lock && flags & DMA_PREP_UNLOCK) + desc->flags |= cpu_to_le16(DESC_FLAG_UNLOCK); + } + desc->addr = cpu_to_le32(sg_dma_address(sg) + curr_offset); diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index b137fdb56093..70f23068bfdc 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -200,6 +200,10 @@ struct dma_vec { * transaction is marked with DMA_PREP_REPEAT will cause the new transaction * to never be processed and stay in the issued queue forever. The flag is * ignored if the previous transaction is not a repeated transaction. + * @DMA_PREP_LOCK: tell the driver that there is a lock bit set on command + * descriptor. + * @DMA_PREP_UNLOCK: tell the driver that there is a un-lock bit set on command + * descriptor. */ enum dma_ctrl_flags { DMA_PREP_INTERRUPT = (1 << 0), @@ -212,6 +216,8 @@ enum dma_ctrl_flags { DMA_PREP_CMD = (1 << 7), DMA_PREP_REPEAT = (1 << 8), DMA_PREP_LOAD_EOT = (1 << 9), + DMA_PREP_LOCK = (1 << 10), + DMA_PREP_UNLOCK = (1 << 11), }; /** From patchwork Thu Aug 15 08:57:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 13764525 X-Patchwork-Delegate: herbert@gondor.apana.org.au Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD5F81AE87C; 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Thu, 15 Aug 2024 08:57:33 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 47F8u8eC028285; Thu, 15 Aug 2024 08:57:29 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 40xkmhenmm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:29 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vSAZ029649; Thu, 15 Aug 2024 08:57:28 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vSoK029641 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:28 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id 9B58441328; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 04/16] crypto: qce - Add support for crypto address read Date: Thu, 15 Aug 2024 14:27:13 +0530 Message-Id: <20240815085725.2740390-5-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: p3P9FvkGCCxxLnxm90hBxU_-mHEuUf__ X-Proofpoint-ORIG-GUID: p3P9FvkGCCxxLnxm90hBxU_-mHEuUf__ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 spamscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Get crypto base address from DT. This will use for command descriptor support for crypto register r/w via BAM/DMA Signed-off-by: Md Sadre Alam --- Change in [v2] * Addressed all comments from v1 Change in [v1] * Added support to read crypto base address from dt drivers/crypto/qce/core.c | 13 ++++++++++++- drivers/crypto/qce/core.h | 1 + 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 28b5fd823827..9b23a948078a 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -192,6 +192,7 @@ static int qce_crypto_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct qce_device *qce; + struct resource *res; int ret; qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); @@ -201,10 +202,16 @@ static int qce_crypto_probe(struct platform_device *pdev) qce->dev = dev; platform_set_drvdata(pdev, qce); - qce->base = devm_platform_ioremap_resource(pdev, 0); + qce->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(qce->base)) return PTR_ERR(qce->base); + qce->base_dma = dma_map_resource(dev, res->start, + resource_size(res), + DMA_BIDIRECTIONAL, 0); + if (dma_mapping_error(dev, qce->base_dma)) + return -ENXIO; + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret < 0) return ret; @@ -280,6 +287,7 @@ static int qce_crypto_probe(struct platform_device *pdev) static void qce_crypto_remove(struct platform_device *pdev) { struct qce_device *qce = platform_get_drvdata(pdev); + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); tasklet_kill(&qce->done_tasklet); qce_unregister_algs(qce); @@ -287,6 +295,9 @@ static void qce_crypto_remove(struct platform_device *pdev) clk_disable_unprepare(qce->bus); clk_disable_unprepare(qce->iface); clk_disable_unprepare(qce->core); + + dma_unmap_resource(&pdev->dev, qce->base_dma, resource_size(res), + DMA_BIDIRECTIONAL, 0); } static const struct of_device_id qce_crypto_of_match[] = { diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 228fcd69ec51..25e2af45c047 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -39,6 +39,7 @@ struct qce_device { struct qce_dma_data dma; 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Thu, 15 Aug 2024 08:57:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 40xkmhennn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vSAb029649; Thu, 15 Aug 2024 08:57:30 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vTEw029700 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id 9E36141352; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 05/16] crypto: qce - Add bam dma support for crypto register r/w Date: Thu, 15 Aug 2024 14:27:14 +0530 Message-Id: <20240815085725.2740390-6-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: XjZS_Oa-OIQkO5CnGY19a33IGpIX5wKH X-Proofpoint-ORIG-GUID: XjZS_Oa-OIQkO5CnGY19a33IGpIX5wKH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 bulkscore=0 clxscore=1015 phishscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Add BAM/DMA support for crypto register read/write. With this change multiple crypto register will get Written/Read using bam in one go. Signed-off-by: Md Sadre Alam --- Change in [v2] * Addressed all the comments from v1 Change in [v1] * Added initial support to read/write crypto regitser via bam drivers/crypto/qce/core.h | 9 ++ drivers/crypto/qce/dma.c | 227 ++++++++++++++++++++++++++++++++++++++ drivers/crypto/qce/dma.h | 24 +++- 3 files changed, 259 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 25e2af45c047..bf28dedd1509 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -40,6 +40,8 @@ struct qce_device { int burst_size; unsigned int pipe_pair_id; dma_addr_t base_dma; + __le32 *reg_read_buf; + dma_addr_t reg_buf_phys; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret); @@ -59,4 +61,11 @@ struct qce_algo_ops { int (*async_req_handle)(struct crypto_async_request *async_req); }; +int qce_write_reg_dma(struct qce_device *qce, unsigned int offset, u32 val, + int cnt); +int qce_read_reg_dma(struct qce_device *qce, unsigned int offset, void *buff, + int cnt); +void qce_clear_bam_transaction(struct qce_device *qce); +int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags); +struct qce_bam_transaction *qce_alloc_bam_txn(struct qce_dma_data *dma); #endif /* _CORE_H_ */ diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 46db5bf366b4..e4e672d65302 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -4,12 +4,214 @@ */ #include +#include #include +#include "core.h" #include "dma.h" +#define QCE_REG_BUF_DMA_ADDR(qce, vaddr) \ + ((qce)->reg_buf_phys + \ + ((uint8_t *)(vaddr) - (uint8_t *)(qce)->reg_read_buf)) + +void qce_clear_bam_transaction(struct qce_device *qce) +{ + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; + + memset(&qce_bam_txn->qce_bam_ce_index, 0, sizeof(u32) * 8); +} + +static int qce_dma_prep_cmd_sg(struct qce_device *qce, struct dma_chan *chan, + struct scatterlist *qce_bam_sgl, + int qce_sgl_cnt, unsigned long flags, + enum dma_transfer_direction dir_eng, + dma_async_tx_callback cb, void *cb_param) +{ + struct dma_async_tx_descriptor *dma_desc; + struct qce_desc_info *desc; + dma_cookie_t cookie; + + desc = qce->dma.qce_bam_txn->qce_desc; + + if (dir_eng == DMA_MEM_TO_DEV) + desc->dir = DMA_TO_DEVICE; + if (dir_eng == DMA_DEV_TO_MEM) + desc->dir = DMA_FROM_DEVICE; + + if (!qce_bam_sgl || !qce_sgl_cnt) + return -EINVAL; + + if (!dma_map_sg(qce->dev, qce_bam_sgl, + qce_sgl_cnt, desc->dir)) { + dev_err(qce->dev, "failure in mapping sgl for cmd desc\n"); + return -ENOMEM; + } + + dma_desc = dmaengine_prep_slave_sg(chan, qce_bam_sgl, qce_sgl_cnt, + dir_eng, flags); + if (!dma_desc) { + pr_err("%s:failure in prep cmd desc\n", __func__); + dma_unmap_sg(qce->dev, qce_bam_sgl, qce_sgl_cnt, desc->dir); + kfree(desc); + return -EINVAL; + } + + desc->dma_desc = dma_desc; + desc->dma_desc->callback = cb; + desc->dma_desc->callback_param = cb_param; + + cookie = dmaengine_submit(desc->dma_desc); + + return dma_submit_error(cookie); +} + +int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags) +{ + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; + struct dma_chan *chan = qce->dma.rxchan; + unsigned long desc_flags; + int ret = 0; + + desc_flags = DMA_PREP_CMD; + + /* For command descriptor always use consumer pipe + * it recomended as per HPG + */ + + if (qce_bam_txn->qce_read_sgl_cnt) { + ret = qce_dma_prep_cmd_sg(qce, chan, qce_bam_txn->qce_reg_read_sgl, + qce_bam_txn->qce_read_sgl_cnt, + desc_flags, DMA_DEV_TO_MEM, + NULL, NULL); + if (ret) { + pr_err("error while submiting cmd desc for rx\n"); + return ret; + } + } + + if (qce_bam_txn->qce_write_sgl_cnt) { + ret = qce_dma_prep_cmd_sg(qce, chan, qce_bam_txn->qce_reg_write_sgl, + qce_bam_txn->qce_write_sgl_cnt, + desc_flags, DMA_MEM_TO_DEV, + NULL, NULL); + } + + if (ret) { + pr_err("error while submiting cmd desc for tx\n"); + return ret; + } + + qce_dma_issue_pending(&qce->dma); + + if (qce_bam_txn->qce_read_sgl_cnt) + dma_unmap_sg(qce->dev, qce_bam_txn->qce_reg_read_sgl, + qce_bam_txn->qce_read_sgl_cnt, + DMA_FROM_DEVICE); + if (qce_bam_txn->qce_write_sgl_cnt) + dma_unmap_sg(qce->dev, qce_bam_txn->qce_reg_write_sgl, + qce_bam_txn->qce_write_sgl_cnt, + DMA_TO_DEVICE); + + return ret; +} + +static void qce_prep_dma_command_desc(struct qce_device *qce, struct qce_dma_data *dma, + bool read, unsigned int addr, void *buff, int size) +{ + struct qce_bam_transaction *qce_bam_txn = dma->qce_bam_txn; + struct bam_cmd_element *qce_bam_ce_buffer; + int qce_bam_ce_size, cnt, index; + + index = qce_bam_txn->qce_bam_ce_index; + qce_bam_ce_buffer = &qce_bam_txn->qce_bam_ce[index]; + if (read) + bam_prep_ce(qce_bam_ce_buffer, addr, BAM_READ_COMMAND, + QCE_REG_BUF_DMA_ADDR(qce, + (unsigned int *)buff)); + else + bam_prep_ce_le32(qce_bam_ce_buffer, addr, BAM_WRITE_COMMAND, + *((__le32 *)buff)); + + if (read) { + cnt = qce_bam_txn->qce_read_sgl_cnt; + qce_bam_ce_buffer = &qce_bam_txn->qce_bam_ce + [qce_bam_txn->qce_pre_bam_ce_index]; + qce_bam_txn->qce_bam_ce_index += size; + qce_bam_ce_size = (qce_bam_txn->qce_bam_ce_index - + qce_bam_txn->qce_pre_bam_ce_index) * + sizeof(struct bam_cmd_element); + + sg_set_buf(&qce_bam_txn->qce_reg_read_sgl[cnt], + qce_bam_ce_buffer, + qce_bam_ce_size); + + ++qce_bam_txn->qce_read_sgl_cnt; + qce_bam_txn->qce_pre_bam_ce_index = + qce_bam_txn->qce_bam_ce_index; + } else { + cnt = qce_bam_txn->qce_write_sgl_cnt; + qce_bam_ce_buffer = &qce_bam_txn->qce_bam_ce + [qce_bam_txn->qce_pre_bam_ce_index]; + qce_bam_txn->qce_bam_ce_index += size; + qce_bam_ce_size = (qce_bam_txn->qce_bam_ce_index - + qce_bam_txn->qce_pre_bam_ce_index) * + sizeof(struct bam_cmd_element); + + sg_set_buf(&qce_bam_txn->qce_reg_write_sgl[cnt], + qce_bam_ce_buffer, + qce_bam_ce_size); + + ++qce_bam_txn->qce_write_sgl_cnt; + qce_bam_txn->qce_pre_bam_ce_index = + qce_bam_txn->qce_bam_ce_index; + } +} + +int qce_write_reg_dma(struct qce_device *qce, + unsigned int offset, u32 val, int cnt) +{ + qce_prep_dma_command_desc(qce, &qce->dma, false, (qce->base_dma + offset), + &val, cnt); + return 0; +} + +int qce_read_reg_dma(struct qce_device *qce, + unsigned int offset, void *buff, int cnt) +{ + qce_prep_dma_command_desc(qce, &qce->dma, true, (qce->base_dma + offset), + qce->reg_read_buf, cnt); + memcpy(buff, qce->reg_read_buf, 4); + + return 0; +} + +struct qce_bam_transaction *qce_alloc_bam_txn(struct qce_dma_data *dma) +{ + struct qce_bam_transaction *qce_bam_txn; + + dma->qce_bam_txn = kmalloc(sizeof(*qce_bam_txn), GFP_KERNEL); + if (!dma->qce_bam_txn) + return NULL; + + dma->qce_bam_txn->qce_desc = kzalloc(sizeof(*dma->qce_bam_txn->qce_desc), + GFP_KERNEL); + if (!dma->qce_bam_txn->qce_desc) { + kfree(dma->qce_bam_txn); + return NULL; + } + + sg_init_table(dma->qce_bam_txn->qce_reg_write_sgl, + QCE_BAM_CMD_SGL_SIZE); + + sg_init_table(dma->qce_bam_txn->qce_reg_read_sgl, + QCE_BAM_CMD_SGL_SIZE); + + return dma->qce_bam_txn; +} + int qce_dma_request(struct device *dev, struct qce_dma_data *dma) { + struct qce_device *qce = container_of(dma, struct qce_device, dma); int ret; dma->txchan = dma_request_chan(dev, "tx"); @@ -31,7 +233,22 @@ int qce_dma_request(struct device *dev, struct qce_dma_data *dma) dma->ignore_buf = dma->result_buf + QCE_RESULT_BUF_SZ; + dma->qce_bam_txn = qce_alloc_bam_txn(dma); + if (!dma->qce_bam_txn) { + pr_err("Failed to allocate bam transaction\n"); + return -ENOMEM; + } + + qce->reg_read_buf = dmam_alloc_coherent(qce->dev, QCE_MAX_REG_READ * + sizeof(*qce->reg_read_buf), + &qce->reg_buf_phys, GFP_KERNEL); + if (!qce->reg_read_buf) { + pr_err("Failed to allocate reg_read_buf\n"); + return -ENOMEM; + } + return 0; + error_nomem: dma_release_channel(dma->rxchan); error_rx: @@ -41,9 +258,19 @@ int qce_dma_request(struct device *dev, struct qce_dma_data *dma) void qce_dma_release(struct qce_dma_data *dma) { + struct qce_device *qce = container_of(dma, + struct qce_device, dma); + dma_release_channel(dma->txchan); dma_release_channel(dma->rxchan); kfree(dma->result_buf); + if (qce->reg_read_buf) + dmam_free_coherent(qce->dev, QCE_MAX_REG_READ * + sizeof(*qce->reg_read_buf), + qce->reg_read_buf, + qce->reg_buf_phys); + kfree(dma->qce_bam_txn->qce_desc); + kfree(dma->qce_bam_txn); } struct scatterlist * diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index 786402169360..f10991590b3f 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -7,6 +7,7 @@ #define _DMA_H_ #include +#include /* maximum data transfer block size between BAM and CE */ #define QCE_BAM_BURST_SIZE 64 @@ -14,6 +15,10 @@ #define QCE_AUTHIV_REGS_CNT 16 #define QCE_AUTH_BYTECOUNT_REGS_CNT 4 #define QCE_CNTRIV_REGS_CNT 4 +#define QCE_BAM_CMD_SGL_SIZE 64 +#define QCE_BAM_CMD_ELEMENT_SIZE 64 +#define QCE_DMA_DESC_FLAG_BAM_NWD (0x0004) +#define QCE_MAX_REG_READ 8 struct qce_result_dump { u32 auth_iv[QCE_AUTHIV_REGS_CNT]; @@ -27,13 +32,30 @@ struct qce_result_dump { #define QCE_RESULT_BUF_SZ \ ALIGN(sizeof(struct qce_result_dump), QCE_BAM_BURST_SIZE) +struct qce_bam_transaction { + struct bam_cmd_element qce_bam_ce[QCE_BAM_CMD_ELEMENT_SIZE]; + struct scatterlist qce_reg_write_sgl[QCE_BAM_CMD_SGL_SIZE]; + struct scatterlist qce_reg_read_sgl[QCE_BAM_CMD_SGL_SIZE]; + struct qce_desc_info *qce_desc; + u32 qce_bam_ce_index; + u32 qce_pre_bam_ce_index; + u32 qce_write_sgl_cnt; + u32 qce_read_sgl_cnt; +}; + struct qce_dma_data { struct dma_chan *txchan; struct dma_chan *rxchan; struct qce_result_dump *result_buf; + struct qce_bam_transaction *qce_bam_txn; void *ignore_buf; }; +struct qce_desc_info { + struct dma_async_tx_descriptor *dma_desc; + enum dma_data_direction dir; +}; + int qce_dma_request(struct device *dev, struct qce_dma_data *dma); void qce_dma_release(struct qce_dma_data *dma); int qce_dma_prep_sgs(struct qce_dma_data *dma, struct scatterlist *sg_in, @@ -44,5 +66,5 @@ int qce_dma_terminate_all(struct qce_dma_data *dma); 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Thu, 15 Aug 2024 08:57:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 40xkmhennp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8un7C028821; Thu, 15 Aug 2024 08:57:30 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vTPd029703 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id A1F97417EE; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 06/16] crypto: qce - Convert register r/w for skcipher via BAM/DMA Date: Thu, 15 Aug 2024 14:27:15 +0530 Message-Id: <20240815085725.2740390-7-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: NdfFiAGVqSls7NaIJQV8GvOXel00747L X-Proofpoint-ORIG-GUID: NdfFiAGVqSls7NaIJQV8GvOXel00747L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 impostorscore=0 clxscore=1015 malwarescore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Convert register read/write for skcipher via BAM/DMA. with this change all the crypto register configuration will be done via BAM/DMA. This change will prepare command descriptor for all register and write it once. Signed-off-by: Md Sadre Alam --- Change in [v2] * No change Change in [v1] * Added crypto register read/write via bam for skcipher drivers/crypto/qce/common.c | 42 ++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 04253a8d3340..d1da6b1938f3 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -34,7 +34,7 @@ static inline void qce_write_array(struct qce_device *qce, u32 offset, int i; for (i = 0; i < len; i++) - qce_write(qce, offset + i * sizeof(u32), val[i]); + qce_write_reg_dma(qce, offset + i * sizeof(u32), val[i], 1); } static inline void @@ -43,7 +43,7 @@ qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len) int i; for (i = 0; i < len; i++) - qce_write(qce, offset + i * sizeof(u32), 0); + qce_write_reg_dma(qce, offset + i * sizeof(u32), 0, 1); } static u32 qce_config_reg(struct qce_device *qce, int little) @@ -86,16 +86,16 @@ static void qce_setup_config(struct qce_device *qce) config = qce_config_reg(qce, 0); /* clear status */ - qce_write(qce, REG_STATUS, 0); - qce_write(qce, REG_CONFIG, config); + qce_write_reg_dma(qce, REG_STATUS, 0, 1); + qce_write_reg_dma(qce, REG_CONFIG, config, 1); } static inline void qce_crypto_go(struct qce_device *qce, bool result_dump) { if (result_dump) - qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); + qce_write_reg_dma(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT), 1); else - qce_write(qce, REG_GOPROC, BIT(GO_SHIFT)); + qce_write_reg_dma(qce, REG_GOPROC, BIT(GO_SHIFT), 1); } #if defined(CONFIG_CRYPTO_DEV_QCE_SHA) || defined(CONFIG_CRYPTO_DEV_QCE_AEAD) @@ -308,7 +308,7 @@ static void qce_xtskey(struct qce_device *qce, const u8 *enckey, /* Set data unit size to cryptlen. Anything else causes * crypto engine to return back incorrect results. */ - qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen); + qce_write_reg_dma(qce, REG_ENCR_XTS_DU_SIZE, cryptlen, 1); } static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) @@ -325,7 +325,9 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) u32 encr_cfg = 0, auth_cfg = 0, config; unsigned int ivsize = rctx->ivsize; unsigned long flags = rctx->flags; + int ret; + qce_clear_bam_transaction(qce); qce_setup_config(qce); if (IS_XTS(flags)) @@ -336,7 +338,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) qce_cpu_to_be32p_array(enckey, ctx->enc_key, keylen); enckey_words = keylen / sizeof(u32); - qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1); encr_cfg = qce_encr_cfg(flags, keylen); @@ -369,25 +371,31 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) if (IS_ENCRYPT(flags)) encr_cfg |= BIT(ENCODE_SHIFT); - qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg); - qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen); - qce_write(qce, REG_ENCR_SEG_START, 0); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, encr_cfg, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_START, 0, 1); if (IS_CTR(flags)) { - qce_write(qce, REG_CNTR_MASK, ~0); - qce_write(qce, REG_CNTR_MASK0, ~0); - qce_write(qce, REG_CNTR_MASK1, ~0); - qce_write(qce, REG_CNTR_MASK2, ~0); + qce_write_reg_dma(qce, REG_CNTR_MASK, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK0, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK1, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK2, ~0, 1); } - qce_write(qce, REG_SEG_SIZE, rctx->cryptlen); + qce_write_reg_dma(qce, REG_SEG_SIZE, rctx->cryptlen, 1); /* get little endianness */ config = qce_config_reg(qce, 1); - qce_write(qce, REG_CONFIG, config); + qce_write_reg_dma(qce, REG_CONFIG, config, 1); qce_crypto_go(qce, true); + ret = qce_submit_cmd_desc(qce, 0); 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Thu, 15 Aug 2024 08:57:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 40xkmhennr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vUBw029711; Thu, 15 Aug 2024 08:57:30 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vTvw029694 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id A5857417F0; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 07/16] crypto: qce - Convert register r/w for sha via BAM/DMA Date: Thu, 15 Aug 2024 14:27:16 +0530 Message-Id: <20240815085725.2740390-8-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ii5zmbULCk8_n2aWUZ3JCupe2zD-y7nC X-Proofpoint-ORIG-GUID: ii5zmbULCk8_n2aWUZ3JCupe2zD-y7nC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 bulkscore=0 clxscore=1015 phishscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Convert register read/write for sha via BAM/DMA. with this change all the crypto register configuration will be done via BAM/DMA. This change will prepare command descriptor for all register and write it once. Signed-off-by: Md Sadre Alam --- Change in [v2] * No change Change in [v1] * Added initial support for register read/write via bam for SHA drivers/crypto/qce/common.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index d1da6b1938f3..d485762a3fdc 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -157,17 +157,19 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req) __be32 mackey[QCE_SHA_HMAC_KEY_SIZE / sizeof(__be32)] = {0}; u32 auth_cfg = 0, config; unsigned int iv_words; + int ret; /* if not the last, the size has to be on the block boundary */ if (!rctx->last_blk && req->nbytes % blocksize) return -EINVAL; + qce_clear_bam_transaction(qce); qce_setup_config(qce); if (IS_CMAC(rctx->flags)) { - qce_write(qce, REG_AUTH_SEG_CFG, 0); - qce_write(qce, REG_ENCR_SEG_CFG, 0); - qce_write(qce, REG_ENCR_SEG_SIZE, 0); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, 0, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, 0, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, 0, 1); qce_clear_array(qce, REG_AUTH_IV0, 16); qce_clear_array(qce, REG_AUTH_KEY0, 16); qce_clear_array(qce, REG_AUTH_BYTECNT0, 4); @@ -213,18 +215,24 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req) auth_cfg &= ~BIT(AUTH_FIRST_SHIFT); go_proc: - qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); - qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes); - qce_write(qce, REG_AUTH_SEG_START, 0); - qce_write(qce, REG_ENCR_SEG_CFG, 0); - qce_write(qce, REG_SEG_SIZE, req->nbytes); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1); + qce_write_reg_dma(qce, REG_AUTH_SEG_SIZE, req->nbytes, 1); + qce_write_reg_dma(qce, REG_AUTH_SEG_START, 0, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, 0, 1); + qce_write_reg_dma(qce, REG_SEG_SIZE, req->nbytes, 1); /* get little endianness */ config = qce_config_reg(qce, 1); - qce_write(qce, REG_CONFIG, config); + qce_write_reg_dma(qce, REG_CONFIG, config, 1); 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Thu, 15 Aug 2024 08:57:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 40xkmhennu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vUe7029710; Thu, 15 Aug 2024 08:57:30 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vTJh029695 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id A8E53417F2; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 08/16] crypto: qce - Convert register r/w for aead via BAM/DMA Date: Thu, 15 Aug 2024 14:27:17 +0530 Message-Id: <20240815085725.2740390-9-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xlAxxxqmd5PHiw0roT84S5i9Xc_q8yBd X-Proofpoint-ORIG-GUID: xlAxxxqmd5PHiw0roT84S5i9Xc_q8yBd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 bulkscore=0 clxscore=1015 phishscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Convert register read/write for aead via BAM/DMA. with this change all the crypto register configuration will be done via BAM/DMA. This change will prepare command descriptor for all register and write it once. Signed-off-by: Md Sadre Alam --- Change in [v2] * updated commit message Change in [v1] * Added initial support for reagister read/write via bam for aead drivers/crypto/qce/common.c | 38 ++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index d485762a3fdc..ff96f6ba1fc5 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -454,7 +454,9 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) unsigned long flags = rctx->flags; u32 encr_cfg, auth_cfg, config, totallen; u32 iv_last_word; + int ret; + qce_clear_bam_transaction(qce); qce_setup_config(qce); /* Write encryption key */ @@ -467,12 +469,12 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) if (IS_CCM(rctx->flags)) { iv_last_word = enciv[enciv_words - 1]; - qce_write(qce, REG_CNTR3_IV3, iv_last_word + 1); + qce_write_reg_dma(qce, REG_CNTR3_IV3, iv_last_word + 1, 1); qce_write_array(qce, REG_ENCR_CCM_INT_CNTR0, (u32 *)enciv, enciv_words); - qce_write(qce, REG_CNTR_MASK, ~0); - qce_write(qce, REG_CNTR_MASK0, ~0); - qce_write(qce, REG_CNTR_MASK1, ~0); - qce_write(qce, REG_CNTR_MASK2, ~0); + qce_write_reg_dma(qce, REG_CNTR_MASK, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK0, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK1, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK2, ~0, 1); } /* Clear authentication IV and KEY registers of previous values */ @@ -508,7 +510,7 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) encr_cfg = qce_encr_cfg(flags, enc_keylen); if (IS_ENCRYPT(flags)) encr_cfg |= BIT(ENCODE_SHIFT); - qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, encr_cfg, 1); /* Set up AUTH_SEG_CFG */ auth_cfg = qce_auth_cfg(rctx->flags, auth_keylen, ctx->authsize); @@ -525,34 +527,40 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) else auth_cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT; } - qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1); totallen = rctx->cryptlen + rctx->assoclen; /* Set the encryption size and start offset */ if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags)) - qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize, 1); else - qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen); - qce_write(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff, 1); /* Set the authentication size and start offset */ - qce_write(qce, REG_AUTH_SEG_SIZE, totallen); - qce_write(qce, REG_AUTH_SEG_START, 0); + qce_write_reg_dma(qce, REG_AUTH_SEG_SIZE, totallen, 1); + qce_write_reg_dma(qce, REG_AUTH_SEG_START, 0, 1); /* Write total length */ if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags)) - qce_write(qce, REG_SEG_SIZE, totallen + ctx->authsize); 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Signed-off-by: Md Sadre Alam --- Change in [v2] * No change Change in [v1] * Added initial support for lock/un-lock flag drivers/crypto/qce/dma.c | 7 ++++++- drivers/crypto/qce/dma.h | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index e4e672d65302..93d455d1d5b4 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -72,7 +72,12 @@ int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags) unsigned long desc_flags; int ret = 0; - desc_flags = DMA_PREP_CMD; + if (flags & QCE_DMA_DESC_FLAG_LOCK) + desc_flags = DMA_PREP_CMD | DMA_PREP_LOCK; + else if (flags & QCE_DMA_DESC_FLAG_UNLOCK) + desc_flags = DMA_PREP_CMD | DMA_PREP_UNLOCK; + else + desc_flags = DMA_PREP_CMD; /* For command descriptor always use consumer pipe * it recomended as per HPG diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index f10991590b3f..ad8a18a720b1 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -19,6 +19,8 @@ #define QCE_BAM_CMD_ELEMENT_SIZE 64 #define QCE_DMA_DESC_FLAG_BAM_NWD (0x0004) #define QCE_MAX_REG_READ 8 +#define QCE_DMA_DESC_FLAG_LOCK (0x0002) +#define QCE_DMA_DESC_FLAG_UNLOCK (0x0001) struct qce_result_dump { u32 auth_iv[QCE_AUTHIV_REGS_CNT]; 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Date: Thu, 15 Aug 2024 14:27:19 +0530 Message-Id: <20240815085725.2740390-11-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: aEbxav2zSqw_lQbPUAIT3L4L-aZrDzsX X-Proofpoint-ORIG-GUID: aEbxav2zSqw_lQbPUAIT3L4L-aZrDzsX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 impostorscore=0 bulkscore=0 malwarescore=0 spamscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Add support for lock acquire and lock release api. When multiple EE's(Execution Environment) want to access CE5 then there will be race condition b/w multiple EE's. Since each EE's having their dedicated BAM pipe, BAM allows Locking and Unlocking on BAM pipe. So if one EE's requesting for CE5 access then that EE's first has to LOCK the BAM pipe while setting LOCK bit on command descriptor and then access it. After finishing the request EE's has to UNLOCK the BAM pipe so in this way we race condition will not happen. Added these two API qce_bam_acquire_lock() and qce_bam_release_lock() for the same. Signed-off-by: Md Sadre Alam --- Change in [v2] * No chnage Change in [v1] * Added initial support for lock_acquire and lock_release api. drivers/crypto/qce/common.c | 36 ++++++++++++++++++++++++++++++++++++ drivers/crypto/qce/core.h | 2 ++ 2 files changed, 38 insertions(+) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index ff96f6ba1fc5..a8eaffe41101 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -617,3 +617,39 @@ void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step) *minor = (val & CORE_MINOR_REV_MASK) >> CORE_MINOR_REV_SHIFT; *step = (val & CORE_STEP_REV_MASK) >> CORE_STEP_REV_SHIFT; } + +int qce_bam_acquire_lock(struct qce_device *qce) +{ + int ret; + + qce_clear_bam_transaction(qce); + + /* This is just a dummy write to acquire lock on bam pipe */ + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, 0, 1); + + ret = qce_submit_cmd_desc(qce, QCE_DMA_DESC_FLAG_LOCK); + if (ret) { + dev_err(qce->dev, "Error in Locking cmd descriptor\n"); + return ret; + } + + return 0; +} + +int qce_bam_release_lock(struct qce_device *qce) +{ + int ret; + + qce_clear_bam_transaction(qce); + + /* This just dummy write to release lock on bam pipe*/ + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, 0, 1); + + ret = qce_submit_cmd_desc(qce, QCE_DMA_DESC_FLAG_UNLOCK); + if (ret) { + dev_err(qce->dev, "Error in Un-Locking cmd descriptor\n"); + return ret; + } + + return 0; +} diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index bf28dedd1509..d01d810b60ad 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -68,4 +68,6 @@ int qce_read_reg_dma(struct qce_device *qce, unsigned int offset, void *buff, void qce_clear_bam_transaction(struct qce_device *qce); int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags); struct qce_bam_transaction *qce_alloc_bam_txn(struct qce_dma_data *dma); +int qce_bam_acquire_lock(struct qce_device *qce); +int qce_bam_release_lock(struct qce_device *qce); #endif /* _CORE_H_ */ From patchwork Thu Aug 15 08:57:20 2024 Content-Type: text/plain; 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Thu, 15 Aug 2024 08:57:30 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vSMt029648; Thu, 15 Aug 2024 08:57:30 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vT3L029699 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id B2B50417F9; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 11/16] crypto: qce - Add support for lock/unlock in skcipher Date: Thu, 15 Aug 2024 14:27:20 +0530 Message-Id: <20240815085725.2740390-12-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: uW0nZIsmkxrr0mlTT4SxummasRjZlRMe X-Proofpoint-GUID: uW0nZIsmkxrr0mlTT4SxummasRjZlRMe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 phishscore=0 spamscore=0 bulkscore=0 suspectscore=0 adultscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Add support for lock/unlock on bam pipe in skcipher. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- Change in [v2] * Removed unmap_sg() from crypto done api Change in [v1] * Added qce_bam_acquire_lock and qce_bam_release_lock api in skcipher drivers/crypto/qce/skcipher.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index 5b493fdc1e74..a4e09562b5f4 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -52,6 +52,8 @@ static void qce_skcipher_done(void *data) sg_free_table(&rctx->dst_tbl); + qce_bam_release_lock(qce); + error = qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "skcipher operation error (%x)\n", status); @@ -82,6 +84,8 @@ qce_skcipher_async_req_handle(struct crypto_async_request *async_req) dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; + qce_bam_acquire_lock(qce); + rctx->src_nents = sg_nents_for_len(req->src, req->cryptlen); if (diff_dst) rctx->dst_nents = sg_nents_for_len(req->dst, req->cryptlen); From patchwork Thu Aug 15 08:57:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 13764534 X-Patchwork-Delegate: herbert@gondor.apana.org.au Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E4051C9EC7; Thu, 15 Aug 2024 08:57:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723712280; cv=none; b=OpYzwMWEyxVbWUKI11chnNu3x/I9BkV1r+556kn6YrFIPiL+2LQCEN0eWPPHLJ2FEIgQhdDp+SUApz9A7TcGfH0ryjn0ApNlc949Uj5Mjt4p4N6fB/ECShYVv2QE+FO9YdiaN1pNWRmgzjo5nW4xls8csy8o6eN5zFsLC4d2Kuo= ARC-Message-Signature: i=1; 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Thu, 15 Aug 2024 08:57:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 40xkmhennk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vSVw029647; Thu, 15 Aug 2024 08:57:30 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vTZG029701 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id B6086417FA; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 12/16] crypto: qce - Add support for lock/unlock in sha Date: Thu, 15 Aug 2024 14:27:21 +0530 Message-Id: <20240815085725.2740390-13-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BBnqXgs44Wym-yaUwwDjtO__iV4-c6Gd X-Proofpoint-ORIG-GUID: BBnqXgs44Wym-yaUwwDjtO__iV4-c6Gd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 impostorscore=0 clxscore=1015 malwarescore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Add support for lock/unlock on bam pipe in sha. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- Change in [v2] * Removed unmap_sg() from crypto done api Change in [v1] * Added qce_bam_acquire_lock and qce_bam_release_lock api in sha drivers/crypto/qce/sha.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c index fc72af8aa9a7..abfa63ff18d7 100644 --- a/drivers/crypto/qce/sha.c +++ b/drivers/crypto/qce/sha.c @@ -60,6 +60,8 @@ static void qce_ahash_done(void *data) rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]); rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]); + qce_bam_release_lock(qce); + error = qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "ahash operation error (%x)\n", status); @@ -90,6 +92,8 @@ static int qce_ahash_async_req_handle(struct crypto_async_request *async_req) rctx->authklen = AES_KEYSIZE_128; } + qce_bam_acquire_lock(qce); + rctx->src_nents = sg_nents_for_len(req->src, req->nbytes); if (rctx->src_nents < 0) { dev_err(qce->dev, "Invalid numbers of src SG.\n"); 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Thu, 15 Aug 2024 08:57:31 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 40xkmhennv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:31 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vSF6029646; Thu, 15 Aug 2024 08:57:30 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vToF029697 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id B9606417FB; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 13/16] crypto: qce - Add support for lock/unlock in aead Date: Thu, 15 Aug 2024 14:27:22 +0530 Message-Id: <20240815085725.2740390-14-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: pWga5pM_evWnirxuErqi5Phsp8rwPfoA X-Proofpoint-ORIG-GUID: pWga5pM_evWnirxuErqi5Phsp8rwPfoA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 bulkscore=0 clxscore=1015 phishscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Add support for lock/unlock on bam pipe in aead. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- Change in [v2] * Removed unmap_sg() from crypto done api Change in [v1] * Added qce_bam_acquire_lock and qce_bam_release_lock api in aead drivers/crypto/qce/aead.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c index 7d811728f047..13fb7af69f54 100644 --- a/drivers/crypto/qce/aead.c +++ b/drivers/crypto/qce/aead.c @@ -63,6 +63,8 @@ static void qce_aead_done(void *data) sg_free_table(&rctx->dst_tbl); } + qce_bam_release_lock(qce); + error = qce_check_status(qce, &status); if (error < 0 && (error != -EBADMSG)) dev_err(qce->dev, "aead operation error (%x)\n", status); @@ -433,6 +435,8 @@ qce_aead_async_req_handle(struct crypto_async_request *async_req) else rctx->assoclen = req->assoclen; + qce_bam_acquire_lock(qce); + diff_dst = (req->src != req->dst) ? true : false; dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? 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Thu, 15 Aug 2024 08:57:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 40xkmhennt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vSWN029645; Thu, 15 Aug 2024 08:57:30 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vTGh029702 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:30 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id BC7AD417FC; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 14/16] arm64: dts: qcom: ipq9574: enable bam pipe locking/unlocking Date: Thu, 15 Aug 2024 14:27:23 +0530 Message-Id: <20240815085725.2740390-15-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8jli6eJ9Dg6KgG9A_onDxLTPvt2whJPs X-Proofpoint-ORIG-GUID: 8jli6eJ9Dg6KgG9A_onDxLTPvt2whJPs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 impostorscore=0 mlxlogscore=929 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 enable bam pipe locking/unlocking for ipq9507 SoC. Signed-off-by: Md Sadre Alam --- Change in [v2] * enabled locking/unlocking support for ipq9574 Change in [v1] * This patch was not included in [v1] arch/arm64/boot/dts/qcom/ipq9574.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 48dfafea46a7..dacaec62ec39 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -262,6 +262,7 @@ cryptobam: dma-controller@704000 { #dma-cells = <1>; qcom,ee = <1>; qcom,controlled-remotely; + qcom,bam_pipe_lock; }; crypto: crypto@73a000 { From patchwork Thu Aug 15 08:57:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 13764530 X-Patchwork-Delegate: herbert@gondor.apana.org.au Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E34C1C9EC5; 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Signed-off-by: Md Sadre Alam --- Change in [v2] * enabled locking/unlocking support for ipq8074 Change in [v1] * This patch was not included in [v1] arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 284a4553070f..e53d75e3ecef 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -291,6 +291,7 @@ cryptobam: dma-controller@704000 { #dma-cells = <1>; qcom,ee = <1>; qcom,controlled-remotely; + qcom,bam_pipe_lock; status = "disabled"; }; From patchwork Thu Aug 15 08:57:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 13764524 X-Patchwork-Delegate: herbert@gondor.apana.org.au Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD59F199234; 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Signed-off-by: Md Sadre Alam --- Change in [v2] * enabled locking/unlocking support for ipq6018 Change in [v1] * This patch was not included in [v1] arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index e1e45da7f787..652c2bbf5e99 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -354,6 +354,7 @@ cryptobam: dma-controller@704000 { #dma-cells = <1>; qcom,ee = <1>; qcom,controlled-remotely; + qcom,bam_pipe_lock; }; crypto: crypto@73a000 {