From patchwork Thu Aug 15 13:15:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13764799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7356C52D7C for ; Thu, 15 Aug 2024 13:16:32 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.778061.1188116 (Exim 4.92) (envelope-from ) id 1seaKr-0001Az-T9; Thu, 15 Aug 2024 13:16:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 778061.1188116; Thu, 15 Aug 2024 13:16:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seaKr-0001Ar-QK; Thu, 15 Aug 2024 13:16:13 +0000 Received: by outflank-mailman (input) for mailman id 778061; Thu, 15 Aug 2024 13:16:12 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seaKq-0000wG-56 for xen-devel@lists.xenproject.org; Thu, 15 Aug 2024 13:16:12 +0000 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [2a00:1450:4864:20::62f]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 89ae9865-5b08-11ef-a505-bb4a2ccca743; Thu, 15 Aug 2024 15:16:10 +0200 (CEST) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-a7ab5fc975dso104308166b.1 for ; Thu, 15 Aug 2024 06:16:10 -0700 (PDT) Received: from andrewcoop.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383947151sm100868666b.161.2024.08.15.06.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 06:16:07 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 89ae9865-5b08-11ef-a505-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1723727769; x=1724332569; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JXB1cqrzG0ayFT32zCt0qauALpoTTusQsO7LDnR/lNA=; b=Z/MsgLYWPjzZ1Plho9muooR44K3I4F551VxDnLBo112Aktlk3aZnhKhcSW9C3EUxTX D349vCmTTVXAYkGTbW5/7EpR0CLGmhWncfZcXSHHNjrNV6dZf5HFMSL6dRLuWqxdqoc5 j+gQ6Oqdh26j9iyxSN44rhwy+nwnm1snYRk2k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723727769; x=1724332569; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JXB1cqrzG0ayFT32zCt0qauALpoTTusQsO7LDnR/lNA=; b=RhRQG0uujQnwVDKee1uKbUsoEXKctJ5OtlMvLdIwnqd6weMB6wyXn4UffRKLtnFBkA U0ZwRwKJ2vmbfEf+PBuiUrcazLOIAN/oP2vyAOuxgiSptnkF2GK8Z3V/wfJzx6GoF0BB yryRBvi2UDlENG7Yo478sBAsq5noRZnt2kIU9rJP80G7BLnk9UpLmTJf38aamApILtQJ r3VsxNwqQBKCbQt0WCpow521zewB6Ekv9RgZlR7so18Iu9Xc7beegEtfljYiKEy1FRtD 1Cx5VORHrkgUMfb87pR8vkdSfzvFJGRxRHivhKhwF/x3iRc6O/gPZxhrsTC7B/y4ofQO Dwfw== X-Gm-Message-State: AOJu0YzfO6wdQIWPcjnoMN+XccDTwGuiHF7iDWedxfeka4D3VUzBTWec aypFENemmYR/HRw0jrH8MEV3kkjRb2NP/AJ4jeiw0pWDbWMmqcxRTDP2vtNVVOKRyRiFML6+GFH f X-Google-Smtp-Source: AGHT+IFV5dX+MwhHd9oJRxpgf4lcz7LQU+DGTGIlc1EoxXfzjmfYx+hQ6/uhXhOpJYI63eiyg2w88Q== X-Received: by 2002:a17:907:f71a:b0:a7a:a46e:dc37 with SMTP id a640c23a62f3a-a8367049c2emr439509166b.57.1723727768739; Thu, 15 Aug 2024 06:16:08 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= , Jan Beulich , Jan Beulich Subject: [PATCH v2 1/3] x86/pv: Introduce x86_merge_dr6() and fix do_debug() Date: Thu, 15 Aug 2024 14:15:58 +0100 Message-Id: <20240815131600.4037415-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240815131600.4037415-1-andrew.cooper3@citrix.com> References: <20240815131600.4037415-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Pretty much everywhere in Xen the logic to update %dr6 when injecting #DB is buggy. The architectural behaviour is to overwrite B{0..3} (rather than accumulate) and accumulate all other bits. Introduce a new x86_merge_dr6() helper, and start fixing the mess by adjusting the dr6 merge in do_debug(). Also correct the comment. Signed-off-by: Andrew Cooper Reviewed-by: Roger Pau Monné Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné v2: * Rebase (~6y worth) * Split PV changes out of joint HVM patch. In some theoretical future where deubgging is implemented in terms of introspection even for PV guests, the TODO will complete itself. --- xen/arch/x86/debug.c | 20 ++++++++++++++++++++ xen/arch/x86/include/asm/debugreg.h | 8 ++++++++ xen/arch/x86/include/asm/x86-defns.h | 7 +++++++ xen/arch/x86/traps.c | 10 +++++++--- 4 files changed, 42 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/debug.c b/xen/arch/x86/debug.c index 127fe83021cd..429752b8cc83 100644 --- a/xen/arch/x86/debug.c +++ b/xen/arch/x86/debug.c @@ -2,12 +2,32 @@ /* * Copyright (C) 2023 XenServer. */ +#include #include #include #include +unsigned int x86_merge_dr6(const struct cpu_policy *p, unsigned int dr6, + unsigned int pending_dbg) +{ + /* Flip dr6 to have positive polarity. */ + dr6 ^= X86_DR6_DEFAULT; + + /* Sanity check that only known values are passed in. */ + ASSERT(!(dr6 & ~X86_DR6_KNOWN_MASK)); + ASSERT(!(pending_dbg & ~X86_DR6_KNOWN_MASK)); + + /* Breakpoints 0-3 overridden. Others accumulate. */ + dr6 = (dr6 & ~X86_DR6_BP_MASK) | pending_dbg; + + /* Flip dr6 back to having default polarity. */ + dr6 ^= X86_DR6_DEFAULT; + + return x86_adj_dr6_rsvd(p, dr6); +} + unsigned int x86_adj_dr6_rsvd(const struct cpu_policy *p, unsigned int dr6) { unsigned int ones = X86_DR6_DEFAULT; diff --git a/xen/arch/x86/include/asm/debugreg.h b/xen/arch/x86/include/asm/debugreg.h index 96c406ad53c8..969f2697aee1 100644 --- a/xen/arch/x86/include/asm/debugreg.h +++ b/xen/arch/x86/include/asm/debugreg.h @@ -108,4 +108,12 @@ struct cpu_policy; unsigned int x86_adj_dr6_rsvd(const struct cpu_policy *p, unsigned int dr6); unsigned int x86_adj_dr7_rsvd(const struct cpu_policy *p, unsigned int dr7); +/* + * Merging new status bits into dr6 is far from simple. Breakpoints override, + * while others accumulate. New bits to be merged are taken with positive + * polarity. + */ +unsigned int x86_merge_dr6(const struct cpu_policy *p, unsigned int dr6, + unsigned int pending_dbg); + #endif /* _X86_DEBUGREG_H */ diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h index 3bcdbaccd3aa..caa92829eaa9 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -132,6 +132,13 @@ #define X86_DR6_ZEROS _AC(0x00001000, UL) /* %dr6 bits forced to 0 */ #define X86_DR6_DEFAULT _AC(0xffff0ff0, UL) /* Default %dr6 value */ +#define X86_DR6_BP_MASK \ + (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3) + +#define X86_DR6_KNOWN_MASK \ + (X86_DR6_BP_MASK | X86_DR6_BLD | X86_DR6_BD | X86_DR6_BS | \ + X86_DR6_BT | X86_DR6_RTM) + /* * Debug control flags in DR7. */ diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 552a07e6aa56..521ed4dd816d 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2016,9 +2016,13 @@ void asmlinkage do_debug(struct cpu_user_regs *regs) return; } - /* Save debug status register where guest OS can peek at it */ - v->arch.dr6 |= (dr6 & ~X86_DR6_DEFAULT); - v->arch.dr6 &= (dr6 | ~X86_DR6_DEFAULT); + /* + * Update the guest's dr6 so the debugger can peek at it. + * TODO: This should be passed out-of-bad to the debugger, so guest state + * is not corrupted by debugging actions completed behind it's back. + */ + v->arch.dr6 = x86_merge_dr6(v->domain->arch.cpu_policy, + v->arch.dr6, dr6 ^ X86_DR6_DEFAULT); if ( guest_kernel_mode(v, regs) && v->domain->debugger_attached ) { From patchwork Thu Aug 15 13:15:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 13764798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D200C3DA7F for ; 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Thu, 15 Aug 2024 06:16:09 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= , Jan Beulich Subject: [PATCH v2 2/3] x86/pv: Fix merging of new status bits into %dr6 Date: Thu, 15 Aug 2024 14:15:59 +0100 Message-Id: <20240815131600.4037415-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240815131600.4037415-1-andrew.cooper3@citrix.com> References: <20240815131600.4037415-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 All #DB exceptions result in an update of %dr6, but this isn't captured in Xen's handling, and is buggy everywhere. To begin resolving this issue, add a new pending_dbg field to x86_event (unioned with cr2 to avoid taking any extra space), and introduce pv_inject_debug_exn() helpers to replace the current callers using pv_inject_hw_exception(). Push the adjustment of v->arch.dr6 into pv_inject_event(), and use the new x86_merge_dr6() rather than the current incorrect logic. A key property is that pending_dbg is taken with positive polarity to deal with RTM/BLD sensibly. Most callers pass in a constant, but callers passing in a hardware %dr6 value need to XOR the value with X86_DR6_DEFAULT to flip to positive polarity. This fixes the behaviour of the breakpoint status bits; specifically that any left pending are discarded when a new #DB is raised. In principle it would fix RTM/BLD too, except PV guests can't turn these capabilities on to start with. Signed-off-by: Andrew Cooper Reviewed-by: Roger Pau Monné Reviewed-by: Jan Beulich --- v2: * Rebase (~6y worth) * Split PV changes out of joint HVM patch. --- xen/arch/x86/include/asm/domain.h | 12 ++++++++++++ xen/arch/x86/pv/emul-priv-op.c | 5 +---- xen/arch/x86/pv/emulate.c | 6 ++---- xen/arch/x86/pv/ro-page-fault.c | 2 +- xen/arch/x86/pv/traps.c | 16 ++++++++++++---- xen/arch/x86/traps.c | 2 +- xen/arch/x86/x86_emulate/x86_emulate.h | 5 ++++- 7 files changed, 33 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h index bca3258d69ac..90c959996914 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -731,6 +731,18 @@ static inline void pv_inject_hw_exception(unsigned int vector, int errcode) pv_inject_event(&event); } +static inline void pv_inject_debug_exn(unsigned int pending_dbg) +{ + struct x86_event event = { + .vector = X86_EXC_DB, + .type = X86_EVENTTYPE_HW_EXCEPTION, + .error_code = X86_EVENT_NO_EC, + .pending_dbg = pending_dbg, + }; + + pv_inject_event(&event); +} + static inline void pv_inject_page_fault(int errcode, unsigned long cr2) { const struct x86_event event = { diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index aa11ecadaac0..3be02d85f2fe 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -1366,10 +1366,7 @@ int pv_emulate_privileged_op(struct cpu_user_regs *regs) ctxt.bpmatch |= DR_STEP; if ( ctxt.bpmatch ) - { - curr->arch.dr6 |= ctxt.bpmatch | DR_STATUS_RESERVED_ONE; - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); - } + pv_inject_debug_exn(ctxt.bpmatch); /* fall through */ case X86EMUL_RETRY: diff --git a/xen/arch/x86/pv/emulate.c b/xen/arch/x86/pv/emulate.c index e7a1c0a2cc4f..aa8af96c30f3 100644 --- a/xen/arch/x86/pv/emulate.c +++ b/xen/arch/x86/pv/emulate.c @@ -71,11 +71,9 @@ void pv_emul_instruction_done(struct cpu_user_regs *regs, unsigned long rip) { regs->rip = rip; regs->eflags &= ~X86_EFLAGS_RF; + if ( regs->eflags & X86_EFLAGS_TF ) - { - current->arch.dr6 |= DR_STEP | DR_STATUS_RESERVED_ONE; - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); - } + pv_inject_debug_exn(X86_DR6_BS); } uint64_t pv_get_reg(struct vcpu *v, unsigned int reg) diff --git a/xen/arch/x86/pv/ro-page-fault.c b/xen/arch/x86/pv/ro-page-fault.c index cad28ef928ad..73c9f7578a87 100644 --- a/xen/arch/x86/pv/ro-page-fault.c +++ b/xen/arch/x86/pv/ro-page-fault.c @@ -390,7 +390,7 @@ int pv_ro_page_fault(unsigned long addr, struct cpu_user_regs *regs) /* Fallthrough */ case X86EMUL_OKAY: if ( ctxt.retire.singlestep ) - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + pv_inject_debug_exn(X86_DR6_BS); /* Fallthrough */ case X86EMUL_RETRY: diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 83e84e276233..5a7341abf068 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -50,9 +51,9 @@ void pv_inject_event(const struct x86_event *event) tb->cs = ti->cs; tb->eip = ti->address; - if ( event->type == X86_EVENTTYPE_HW_EXCEPTION && - vector == X86_EXC_PF ) + switch ( vector | -(event->type == X86_EVENTTYPE_SW_INTERRUPT) ) { + case X86_EXC_PF: curr->arch.pv.ctrlreg[2] = event->cr2; arch_set_cr2(curr, event->cr2); @@ -62,9 +63,16 @@ void pv_inject_event(const struct x86_event *event) error_code |= PFEC_user_mode; trace_pv_page_fault(event->cr2, error_code); - } - else + break; + + case X86_EXC_DB: + curr->arch.dr6 = x86_merge_dr6(curr->domain->arch.cpu_policy, + curr->arch.dr6, event->pending_dbg); + fallthrough; + default: trace_pv_trap(vector, regs->rip, use_error_code, error_code); + break; + } if ( use_error_code ) { diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 521ed4dd816d..06e4e3e9af90 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2030,7 +2030,7 @@ void asmlinkage do_debug(struct cpu_user_regs *regs) return; } - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + pv_inject_debug_exn(0 /* N/A, already merged */); } void asmlinkage do_entry_CP(struct cpu_user_regs *regs) diff --git a/xen/arch/x86/x86_emulate/x86_emulate.h b/xen/arch/x86/x86_emulate/x86_emulate.h index d92be69d84d9..e8a0e572284c 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.h +++ b/xen/arch/x86/x86_emulate/x86_emulate.h @@ -78,7 +78,10 @@ struct x86_event { uint8_t type; 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Thu, 15 Aug 2024 06:16:10 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Matthew Barnes Subject: [PATCH v2 3/3] x86/pv: Address Coverity complaint in check_guest_io_breakpoint() Date: Thu, 15 Aug 2024 14:16:00 +0100 Message-Id: <20240815131600.4037415-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240815131600.4037415-1-andrew.cooper3@citrix.com> References: <20240815131600.4037415-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Commit 08aacc392d86 ("x86/emul: Fix misaligned IO breakpoint behaviour in PV guests") caused a Coverity INTEGER_OVERFLOW complaint based on the reasoning that width could be 0. It can't, but digging into the code generation, GCC 8 and later (bisected on gotbolt) choose to emit a CSWITCH lookup table, and because the range (bottom 2 bits clear), it's a 16-entry lookup table. So Coverity is correct, given that GCC did emit a (dead) logic path where width stayed 0. Rewrite the logic. Introduce x86_bp_width() which compiles to a single basic block, which replaces the switch() statement. Take the opportunity to also make start and width be loop-scope variables. No practical change, but it should compile better and placate Coverity. Fixes: 08aacc392d86 ("x86/emul: Fix misaligned IO breakpoint behaviour in PV guests") Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné CC: Matthew Barnes --- xen/arch/x86/include/asm/debugreg.h | 26 ++++++++++++++++++++++++++ xen/arch/x86/pv/emul-priv-op.c | 21 ++++++--------------- 2 files changed, 32 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/include/asm/debugreg.h b/xen/arch/x86/include/asm/debugreg.h index 969f2697aee1..cbcc3e83c3d2 100644 --- a/xen/arch/x86/include/asm/debugreg.h +++ b/xen/arch/x86/include/asm/debugreg.h @@ -116,4 +116,30 @@ unsigned int x86_adj_dr7_rsvd(const struct cpu_policy *p, unsigned int dr7); unsigned int x86_merge_dr6(const struct cpu_policy *p, unsigned int dr6, unsigned int pending_dbg); +/* + * Calculate the width of a breakpoint from its dr7 encoding. + * + * The LEN encoding in dr7 is 2 bits wide per breakpoint and encoded a mask + * (0, 1 and 3) for widths of 1, 2 and 4 respectively in the 32bit days. + * + * In 64bit, the unused value (2) was specified to mean a width of 8, which is + * great for encoding efficiency but less great for nicely calculating the + * width. + */ +static inline unsigned int x86_bp_width(unsigned int dr7, unsigned int bp) +{ + unsigned int raw = (dr7 >> (DR_CONTROL_SHIFT + + DR_CONTROL_SIZE * bp + 2)) & 3; + + /* + * If the top bit is set (i.e. we've got a 4 or 8), flip the bottom to + * reverse their order, making them sorted properly. Then it's a simple + * shift to calculate the width. + */ + if ( raw & 2 ) + raw ^= 1; + + return 1U << raw; +} + #endif /* _X86_DEBUGREG_H */ diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 3be02d85f2fe..c89727da43ee 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -323,30 +323,21 @@ static unsigned int check_guest_io_breakpoint(struct vcpu *v, unsigned int port, unsigned int len) { - unsigned int width, i, match = 0; - unsigned long start; + unsigned int i, match = 0; if ( !v->arch.pv.dr7_emul || !(v->arch.pv.ctrlreg[4] & X86_CR4_DE) ) return 0; for ( i = 0; i < 4; i++ ) { + unsigned long start; + unsigned int width; + if ( !(v->arch.pv.dr7_emul & (3 << (i * DR_ENABLE_SIZE))) ) continue; - start = v->arch.dr[i]; - width = 0; - - switch ( (v->arch.dr7 >> - (DR_CONTROL_SHIFT + i * DR_CONTROL_SIZE)) & 0xc ) - { - case DR_LEN_1: width = 1; break; - case DR_LEN_2: width = 2; break; - case DR_LEN_4: width = 4; break; - case DR_LEN_8: width = 8; break; - } - - start &= ~(width - 1UL); + width = x86_bp_width(v->arch.dr7, i); + start = v->arch.dr[i] & ~(width - 1UL); if ( (start < (port + len)) && ((start + width) > port) ) match |= 1u << i;