From patchwork Fri Aug 16 07:23:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13765559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89EC0C3DA4A for ; Fri, 16 Aug 2024 07:23:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1serJ4-0007CC-SX; Fri, 16 Aug 2024 03:23:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1serJ2-00072y-I6 for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:28 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1serIx-00041X-Nj for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:28 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-70d18d4b94cso1381926b3a.2 for ; Fri, 16 Aug 2024 00:23:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1723793000; x=1724397800; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3m/SRRubX++Qz/UwX8F/bni9rPp5FWQysduj2u1aeQc=; b=GnUZL+5iMDYGmIW3Aen2e3fqKANyf1NKssKjRBJ6x8CpBS26EGyncLxzZdyfyevJbF u4wQTK2onBL7SgZ9Ruu1ixrSfLzwKkFV/Y+A2Y8o0Nd7zleVNvxuc+qz2aD6EsqVgAto cPdo0yUEetj/hr3jKuOHz2s+fJQapOFus1syu/AhQCpCEIiAm0dXipLF3zO8KtgwUu+x +ZqEsdaz7l82cIB3BNP4v4XdP4h8G8qLXCnBGUTxP4rBslcAaPgbQSUx5wfOqVVkurJ0 TDJqtQa1BgLJPU0U4UiMkxRiuq34rL3P4PQ/BnwqKbVHJj4ZjYbFa8doaqtypTktKaPm ccDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723793000; x=1724397800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3m/SRRubX++Qz/UwX8F/bni9rPp5FWQysduj2u1aeQc=; b=X21rFg3TCztwVi4++63kQ9aRlOZxZsjRSEwddGh1O2PamHU2gEWCoay5lmR4w/7btf XOg88v8DFV2kLRgstMXW6I9ZU4F/Y0aith739jL2MfEBfyicOdM2HPeA+5BLp5ous1rJ zFl7l/DJS/lOZaoNdSRTpk9JHuiORfOfs6a+j1M8lb+ImSmR4VJOOczfZ9gFgYc5yZBx CtFunnzy5KBTlAxKJLOq6ylDfYqtHnAOUKcaMVD/1DNjwV2qHmyqmuZ+YSXdjRipkLKj /9vRmM0YhXcEMzk6g/XTjdBOSXRSD1y5xX3O+5mWyRLFQyZTa64HH24BZ9YF0OP88GtF TbuA== X-Gm-Message-State: AOJu0YxfxrCORdskC+GRxYArR82w3T88/dr1PAeTsr9xTdGbbb79pw8U wNboiIJ08LuLILhQZuvbFLomNUBLhm2j2UPn4mKsDDr4rq95xT6IvXvBm47WiVA/PQzvq2zFl3E /Dk0= X-Google-Smtp-Source: AGHT+IHpDA9xq5OUaiic8vvGN77FkN9uYrzYlw8wap0RUvcYN+rEjUDaZRzzIPcRX1X4pnxgqvBaEQ== X-Received: by 2002:a05:6a20:9d8e:b0:1c8:bfa8:d55a with SMTP id adf61e73a8af0-1c904faa94amr2686523637.21.1723793000113; Fri, 16 Aug 2024 00:23:20 -0700 (PDT) Received: from stoup.. (2403-580a-f89b-0-1b6b-8c7b-90f9-144f.ip6.aussiebb.net. [2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com, qemu-stable@nongnu.org Subject: [PATCH v3 1/6] target/sparc: Restrict STQF to sparcv9 Date: Fri, 16 Aug 2024 17:23:06 +1000 Message-ID: <20240816072311.353234-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Prior to sparcv9, the same encoding was STDFQ. Cc: qemu-stable@nongnu.org Fixes: 06c060d9e5b ("target/sparc: Move simple fp load/store to decodetree") Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 113639083b..c803e8d1ba 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4521,7 +4521,7 @@ static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) TRANS(STF, ALL, do_st_fpr, a, MO_32) TRANS(STDF, ALL, do_st_fpr, a, MO_64) -TRANS(STQF, ALL, do_st_fpr, a, MO_128) +TRANS(STQF, 64, do_st_fpr, a, MO_128) TRANS(STFA, 64, do_st_fpr, a, MO_32) TRANS(STDFA, 64, do_st_fpr, a, MO_64) From patchwork Fri Aug 16 07:23:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13765567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87A60C531DC for ; Fri, 16 Aug 2024 07:25:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1serJ5-0007GQ-Sl; Fri, 16 Aug 2024 03:23:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1serJ3-000799-Vx for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:30 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1serIy-00041g-L1 for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:29 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-201e64607a5so12642265ad.2 for ; Fri, 16 Aug 2024 00:23:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1723793003; x=1724397803; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gpBjGkW6BU4v1nqztsjjBjF53uYRgoULCdoJY53mCgc=; b=hv7mQFCgQIgC3vJK0aRnIiTcu8vpUYlF0sLpRib+1oau+KeNcOzHzDdZu1SURGdRmn l/0nNS4xEk6zdrS9IpSrhHePeE25QwgqfkMMu9HsjtUMTsXm3QSqOqvgS7tJHaiMCOxr 5IliFdyG+0TUrUV25KHvGVsg0OJ1StwxtPvJxysvCP0D7zFPJVv4ORPDpOY4+72W6DDN nWkrJH5f1AXk8V7Z4I8cinWVtiendAcFh4DMzmg7RBQdX6UXKTmMheH3ODvSf/egsDtP UUdDMhLoFFhJhjRLk2nsYGPAuX4OSjxb5M4ycNT+TE+rW7j4UJP1qm8l6g5sv6+kXhAe jxLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723793003; x=1724397803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gpBjGkW6BU4v1nqztsjjBjF53uYRgoULCdoJY53mCgc=; b=jmwkbw9IwcEvC58mBIYDpJWhwqr47TnQG9fO00G9f7c778+3OdgsK4WfE7Fy4jm9Sv ORG1e9nzX1K58zwcmeZMEiyLk4WgaN42g2oEdMkSwGGtWFtpRYWexTnfFbwNBHV9zViO meP7uCx9NGuwpvUQtILQtnxmHeHIXWSGfQPSJ9l+QjIi2wmAZOY7Cx5zP2MOBq4ms6pD v7Ity+2osVziDeyjjz2DAma2OCQlux+mJ9FzReRWB6PCuwImzBUgNCUn0N8wXQMjkQvy TlRv4ruE6BmqlfI8pfHpy19m2M7Ierdoikmx447xa25pz98Wx3zPWBk63r7DVr1Zel0g JOSg== X-Gm-Message-State: AOJu0YzfHoeYtpchD9501wfdDBQBQdG4bMnkAt4kCVAbKDv7BjLQzU7Y 0KDKK4rpztFkpAHemyyECGLEBtSnEQiRao4+ZZUG6hPzISBoXGDZyWRW0Srk4Jc6DIgqEap8jMs CGGk= X-Google-Smtp-Source: AGHT+IFr2O8vZNyaBw50MbNjqTKEwM9Nmiwdb1WZHp1h8JQLVLFoa230ea5Vc9f6MBX0SOkQogcYxg== X-Received: by 2002:a17:902:ced2:b0:1ff:3c45:48dd with SMTP id d9443c01a7336-20203eb85famr33930975ad.30.1723793002486; Fri, 16 Aug 2024 00:23:22 -0700 (PDT) Received: from stoup.. (2403-580a-f89b-0-1b6b-8c7b-90f9-144f.ip6.aussiebb.net. [2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com Subject: [PATCH v3 2/6] target/sparc: Add FQ and FSR.QNE Date: Fri, 16 Aug 2024 17:23:07 +1000 Message-ID: <20240816072311.353234-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Carl Hauser Add support for, and migrate, a single-entry fp instruction queue for sparc32. Signed-off-by: Carl Hauser [rth: Split from a larger patch; adjust representation with union; add migration state] Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 22 ++++++++++++++++++++++ target/sparc/fop_helper.c | 4 ++++ target/sparc/machine.c | 25 +++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index dfd9512a21..9f2bc44722 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -184,6 +184,8 @@ enum { #define FSR_FTT_SEQ_ERROR (4ULL << 14) #define FSR_FTT_INVAL_FPR (6ULL << 14) +#define FSR_QNE (1ULL << 13) + #define FSR_FCC0_SHIFT 10 #define FSR_FCC1_SHIFT 32 #define FSR_FCC2_SHIFT 34 @@ -438,6 +440,26 @@ struct CPUArchState { uint32_t fsr_cexc_ftt; /* cexc, ftt */ uint32_t fcc[TARGET_FCCREGS]; /* fcc* */ +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) + /* + * Single-element FPU fault queue, with address and insn, + * packaged into the double-word with which it is stored. + */ + uint32_t fsr_qne; /* qne */ + union { + uint64_t d; + struct { +#if HOST_BIG_ENDIAN + uint32_t addr; + uint32_t insn; +#else + uint32_t insn; + uint32_t addr; +#endif + } s; + } fq; +#endif + CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ uint32_t cwp; /* index of current register window (extracted from PSR) */ diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 0b30665b51..b6692382b3 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -545,6 +545,8 @@ target_ulong cpu_get_fsr(CPUSPARCState *env) fsr |= (uint64_t)env->fcc[1] << FSR_FCC1_SHIFT; fsr |= (uint64_t)env->fcc[2] << FSR_FCC2_SHIFT; fsr |= (uint64_t)env->fcc[3] << FSR_FCC3_SHIFT; +#elif !defined(CONFIG_USER_ONLY) + fsr |= env->fsr_qne; #endif /* VER is kept completely separate until re-assembly. */ @@ -591,6 +593,8 @@ void cpu_put_fsr(CPUSPARCState *env, target_ulong fsr) env->fcc[1] = extract64(fsr, FSR_FCC1_SHIFT, 2); env->fcc[2] = extract64(fsr, FSR_FCC2_SHIFT, 2); env->fcc[3] = extract64(fsr, FSR_FCC3_SHIFT, 2); +#elif !defined(CONFIG_USER_ONLY) + env->fsr_qne = fsr & FSR_QNE; #endif set_fsr_nonsplit(env, fsr); diff --git a/target/sparc/machine.c b/target/sparc/machine.c index 48e0cf22f3..222e5709c5 100644 --- a/target/sparc/machine.c +++ b/target/sparc/machine.c @@ -143,6 +143,24 @@ static const VMStateInfo vmstate_xcc = { .get = get_xcc, .put = put_xcc, }; +#else +static bool fq_needed(void *opaque) +{ + SPARCCPU *cpu = opaque; + return cpu->env.fsr_qne; +} + +static const VMStateDescription vmstate_fq = { + .name = "cpu/fq", + .version_id = 1, + .minimum_version_id = 1, + .needed = fq_needed, + .fields = (const VMStateField[]) { + VMSTATE_UINT32(env.fq.s.addr, SPARCCPU), + VMSTATE_UINT32(env.fq.s.insn, SPARCCPU), + VMSTATE_END_OF_LIST() + }, +}; #endif static int cpu_pre_save(void *opaque) @@ -265,4 +283,11 @@ const VMStateDescription vmstate_sparc_cpu = { #endif VMSTATE_END_OF_LIST() }, +#ifndef TARGET_SPARC64 + .subsections = (const VMStateDescription * const []) { + &vmstate_fq, + NULL + }, +#endif + }; From patchwork Fri Aug 16 07:23:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13765568 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D07AC531DE for ; Fri, 16 Aug 2024 07:25:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1serJ5-0007G8-Qk; Fri, 16 Aug 2024 03:23:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1serJ4-00079J-1h for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:30 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1serJ0-00041o-9y for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:29 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-7c3ebba7fbbso1386581a12.1 for ; Fri, 16 Aug 2024 00:23:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1723793005; x=1724397805; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ek2SH+eIGTE6kXSOvmjvmBjlH+328ULsNPwNMVHdkKo=; b=d3d/SGShkXUefdLSt0+gzNOudjjOguduOiflw0+b4mU8BXXVZ5UY4HPBXN20KtD7FE BVlXyk1SlwlY6vFKtpAGx/lGK3+lWIOmcz2OEQvQowUPeOkklSSODd4vnjL10o7zJ0lr yNsycirNjbLXVVSl2nk8/JeQBlCNE1q+3aBkJvptAUtb1WETQDor8cLzCi8FIt2ubWtq p1K+BJiySDwqp9oAbNQLhqlaTFZJq1xaJWK3FHrn4/uREjBLdavlzyk1vacoyrffkt6P r1XfI2kJKPdSEOxR469kSTQtjudOp0bgXhnR/mbTGJH6E905Yic2seFoNPgb4b6zETCz PHaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723793005; x=1724397805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ek2SH+eIGTE6kXSOvmjvmBjlH+328ULsNPwNMVHdkKo=; b=CLzgc3yIiBAwOUjFV0YI1HKdBdcRGIVZnUnn58nwoUfz8WIp59/4FaMsLgG8ebXQQJ 45Fbq9FKrpE8ZSoIBE54F2vdq+e2dM69zN5SJ2ug9NhoqWe0FLB5rfprkHTI1xs4kCM0 Er4NWEIHer3XDPon0nfJK6WlyfhEfaddDa35BdsEH6ExlbFR9QZXTpQrtBFl25nHo4t6 LijODobx26rp24PzB+Yw3HDju+oJBQ+O5xioANQCaIDM41hQhOWnhGsaYMWGImYzfdyE Z4Jep8lXbE3E0SqYBOLQdH9bnuOViyZ3kqF4swRk/MAC57Ix8g8TG7r1Gc4aTGVAtxv2 pgsA== X-Gm-Message-State: AOJu0Yz/k5wPPVVRAIilaPwIwgnIokBUEdyACGjQo9ZzMujR313be/Cv o0J9V5xAY+1wui2TSeLSInMGEb4zE4MD1OQNYwMYKeWx2x1e4JmajtPzJGIhyWPbr8jae1QEQ+U ZLyI= X-Google-Smtp-Source: AGHT+IFPr4Z67P959ODzh1IOqFW0139YPDL0ZJHpy9CtKHLLJJ/bvoox5y4QSKrufw1xwodPhrsOmA== X-Received: by 2002:a05:6a21:392:b0:1be:c6f8:c530 with SMTP id adf61e73a8af0-1c904fc9f79mr2892997637.26.1723793004727; Fri, 16 Aug 2024 00:23:24 -0700 (PDT) Received: from stoup.. (2403-580a-f89b-0-1b6b-8c7b-90f9-144f.ip6.aussiebb.net. [2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com Subject: [PATCH v3 3/6] target/sparc: Populate sparc32 FQ when raising fp exception Date: Fri, 16 Aug 2024 17:23:08 +1000 Message-ID: <20240816072311.353234-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Carl Hauser Implement a single instruction floating point queue, populated while delivering an fp exception. Signed-off-by: Carl Hauser [rth: Split from a larger patch] Signed-off-by: Richard Henderson --- target/sparc/int32_helper.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 6b7d65b031..fb6f3799c8 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -21,10 +21,10 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "trace.h" +#include "exec/cpu_ldst.h" #include "exec/log.h" #include "sysemu/runstate.h" - static const char * const excp_names[0x80] = { [TT_TFAULT] = "Instruction Access Fault", [TT_ILL_INSN] = "Illegal Instruction", @@ -116,22 +116,9 @@ void sparc_cpu_do_interrupt(CPUState *cs) qemu_log("%6d: %s (v=%02x)\n", count, name, intno); log_cpu_state(cs, 0); -#if 0 - { - int i; - uint8_t *ptr; - - qemu_log(" code="); - ptr = (uint8_t *)env->pc; - for (i = 0; i < 16; i++) { - qemu_log(" %02x", ldub(ptr + i)); - } - qemu_log("\n"); - } -#endif count++; } -#if !defined(CONFIG_USER_ONLY) +#ifndef CONFIG_USER_ONLY if (env->psret == 0) { if (cs->exception_index == 0x80 && env->def.features & CPU_FEATURE_TA0_SHUTDOWN) { @@ -143,6 +130,21 @@ void sparc_cpu_do_interrupt(CPUState *cs) } return; } + if (intno == TT_FP_EXCP) { + env->fsr_qne = FSR_QNE; + env->fq.s.addr = env->pc; + env->fq.s.insn = cpu_ldl_code(env, env->pc); + /* + * The sparc32 fpu has three states related to exception handling. + * The FPop that signals an exception transitions from fp_execute + * to fp_exception_pending. A subsequent FPop transitions from + * fp_exception_pending to fp_exception, which forces the trap. + * We do not model the fp_exception_pending state, but we do need + * to advance pc/npc to mimic the delayed trap delivery. + */ + env->pc = env->npc; + env->npc = env->npc + 4; + } #endif env->psret = 0; cwp = cpu_cwp_dec(env, env->cwp - 1); From patchwork Fri Aug 16 07:23:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13765564 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A6FAC531DE for ; Fri, 16 Aug 2024 07:24:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1serJ6-0007JC-JW; Fri, 16 Aug 2024 03:23:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1serJ4-0007As-DE for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:30 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1serJ2-00041w-MK for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:30 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-201ee6b084bso14391565ad.2 for ; Fri, 16 Aug 2024 00:23:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1723793007; x=1724397807; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K5QfoW0VwajlTQd3ELmUEuobbsHpYmua9JmMsJd9x1U=; b=Z/C/VAkUf2viV0Qm/2cl9oG1IIAvZ+SzDH8h30gzrtbAxKfouDHjg5D0P5JxQiLdmT qmCOm8+kGKH1tNCceFPu4IqfA42rg//RISQbcrH+KWiNqqlItnhSifOvv1dNCDAY61/Q pT5VsXk+NONFuOH069uYYi8NHn4Y/ChHdA2sgoP6pbiDLrZACKDeDNYTd/mDPTCkqU47 IpiVJRZenxqQIgA6xPmbLh3i75Tn91heT8ghpFCKaiOvHpHr9E0wy0NYiBJfEjwxBUeH luTuHkpXkCPPYs2EAdUt7urgAbZMbCrBF0LKDzBvTijeBrFV1a5ddG4YAPvtZcLJvWeW 72Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723793007; x=1724397807; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K5QfoW0VwajlTQd3ELmUEuobbsHpYmua9JmMsJd9x1U=; b=lTDXEfPw3aI/gDFPZicdeoFCKppyFPowa7nIh9QWn323q/80WtPtAAt3UAkdqpkRMo PwXn04djV2ZiEGnq2OsY5/Y1+y3bcRAOZluLmh2pD8e8TDCkcI2HqvVstol7QwSZCML6 PhvCUKr5a7zHan6vx35a6GzjTFXLSytf08qJ3NSe5JtLZxFdSkfrSKUvTlk0fZjObLAv kcrk2mt9wqTgcW+rGcTqYAHwmv5RpHbeHtUUiU6kZEb75Opd1wd2Uxkf644T7eBijUdn n4+JOks4Rfax2vj3UpefukWJDhTJa1y/Czb2rE2ohJRaCzRmUKp2QOUbEZErotqC5is4 Zzsg== X-Gm-Message-State: AOJu0Yz3i0K7r2QTRDP8uXdnI+CKrpM6a/bpB7CcyBeklDQkEYUmR6Q4 ZoBGADO2p7MOC2vi9Yr5pH+aitApdxJOHLbiKqEdSRS6Hd9HrTiXVf25GUr0bhuu9njmA6HZYXb g6SE= X-Google-Smtp-Source: AGHT+IEgZPh5rDde9XyAFxUbQHSM8JWx02PqbUfs58RohWXSE/JsTLTkDxJB1OVAmiJpq/UliOw8EA== X-Received: by 2002:a17:903:32c8:b0:1fb:9627:b348 with SMTP id d9443c01a7336-20203f53eb2mr25162275ad.58.1723793007072; Fri, 16 Aug 2024 00:23:27 -0700 (PDT) Received: from stoup.. (2403-580a-f89b-0-1b6b-8c7b-90f9-144f.ip6.aussiebb.net. [2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com Subject: [PATCH v3 4/6] target/sparc: Add FSR_QNE to tb_flags Date: Fri, 16 Aug 2024 17:23:09 +1000 Message-ID: <20240816072311.353234-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 8 +++++++- target/sparc/translate.c | 10 +++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 9f2bc44722..f517e5a383 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -744,6 +744,7 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_AM_ENABLED (1 << 5) #define TB_FLAG_SUPER (1 << 6) #define TB_FLAG_HYPER (1 << 7) +#define TB_FLAG_FSR_QNE (1 << 8) #define TB_FLAG_ASI_SHIFT 24 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, @@ -775,7 +776,12 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, if (env->psref) { flags |= TB_FLAG_FPU_ENABLED; } -#endif +#ifndef CONFIG_USER_ONLY + if (env->fsr_qne) { + flags |= TB_FLAG_FSR_QNE; + } +#endif /* !CONFIG_USER_ONLY */ +#endif /* TARGET_SPARC64 */ *pflags = flags; } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index c803e8d1ba..eb0158a11d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -185,6 +185,8 @@ typedef struct DisasContext { bool supervisor; #ifdef TARGET_SPARC64 bool hypervisor; +#else + bool fsr_qne; #endif #endif @@ -5596,13 +5598,15 @@ static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags); #ifndef CONFIG_USER_ONLY dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0; +# ifdef TARGET_SPARC64 + dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0; +# else + dc->fsr_qne = (dc->base.tb->flags & TB_FLAG_FSR_QNE) != 0; +# endif #endif #ifdef TARGET_SPARC64 dc->fprs_dirty = 0; dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; -#ifndef CONFIG_USER_ONLY - dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0; -#endif #endif /* * if we reach a page boundary, we stop generation so that the From patchwork Fri Aug 16 07:23:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13765563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02F8BC3DA4A for ; Fri, 16 Aug 2024 07:24:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1serJ8-0007Sp-Oq; Fri, 16 Aug 2024 03:23:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1serJ7-0007Mc-9M for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:33 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1serJ5-00043l-E2 for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:32 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-201df0b2df4so15000015ad.0 for ; Fri, 16 Aug 2024 00:23:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1723793009; x=1724397809; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kbgug2KmicUlkOb+wrePUsXTI50rlI7sMrXGG0mr2zY=; b=W94Y7PIN4osfRxMcN0WMG8/uBfuu0qjO1Q8PFhqHxeFy1QgKq3c1NV+LMi5RH1PwEl nRQ64kE/4ewupNJ7+lmcH8/ztA3eFQMM9H+W3qS6WBNQJsRIjgMijj6QW2FQlL1L4jod 4D086qeCQOUaCLQNiSiOUIudNgvi3Z0j4Tfth7NLmFnOvJ5ed3U3Q/KWHaip0BPlsPmz EJ4dNqJS0GvsjxdECHnOr5bQzynoQ3yYYOhm7XQRtS37F1o1jC1T0f42M9wRK2Ap2CS/ syx5IP2R6BNkFwZsH0o4vYTqr/pPcgys0qq5/6OVHrbChvcvhEzaDo3IQcaY6cy/rWw/ agew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723793009; x=1724397809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kbgug2KmicUlkOb+wrePUsXTI50rlI7sMrXGG0mr2zY=; b=v6QsXgPTmZ8635RQ1rg3qzfftmf33LaiCklAwmtGnwimBmDORD6+hLb6snwcCV4v+F uGdw0YCZdGEPktVdzrtWUkvWW8VyNnBWO8XyzgHZ+hS1ra0Y+R1IsyuGCginE5JPWu2f iIh74aFhx11uxt2ZDmUEW00U8auztEOCbNyrwzd2/AFTMQAMmYK6wTKBVK7doVmRs2KS 5mkPkBGIX8OVgzHwcE9HkTzbeB0T6slJBqE0ft1rXXSh1zaXCGDwEy00WkZhiXUPrAkH a3g/A8PfneBocW25ntOO1d1jI+RaYQCVyEqbWYQmUye4sNH2YjHkBcu/pIK90WVfU5PF EysQ== X-Gm-Message-State: AOJu0YxgFT0UtwJE/QSgMwPsBT/wvcsXpL7JFyE814YrI3itTY2RbfT1 yf5GMIxd9cqnLmIfTUY4heEuTz5wCxIIjnginPxZanzKtLy6VwjYU/EX16hsSA//MlRdTfReQUd 2ipo= X-Google-Smtp-Source: AGHT+IFqObAsAnQn0XVCwl1Bqnf2UjMwIkvpMiiTVmYVLPOkaqiP17I5jfgtmQ2wtcNkefvQRStzGQ== X-Received: by 2002:a17:902:e849:b0:202:708:3443 with SMTP id d9443c01a7336-2020708378fmr16542325ad.27.1723793009453; Fri, 16 Aug 2024 00:23:29 -0700 (PDT) Received: from stoup.. (2403-580a-f89b-0-1b6b-8c7b-90f9-144f.ip6.aussiebb.net. [2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com Subject: [PATCH v3 5/6] target/sparc: Implement STDFQ Date: Fri, 16 Aug 2024 17:23:10 +1000 Message-ID: <20240816072311.353234-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Invalid encoding of addr should raise TT_ILL_INSN, so check before supervisor, which might raise TT_PRIV_INSN. Clear QNE after execution. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 24 +++++++++++++++++++++++- target/sparc/insns.decode | 4 ++-- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index eb0158a11d..6d4c0e79c9 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4531,17 +4531,39 @@ TRANS(STQFA, 64, do_st_fpr, a, MO_128) static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a) { + TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (!avail_32(dc)) { return false; } + if (addr == NULL) { + return false; + } if (!supervisor(dc)) { return raise_priv(dc); } +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) if (gen_trap_ifnofpu(dc)) { return true; } - gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); + if (dc->fsr_qne) { + TCGv_i64 fq = tcg_temp_new_i64(); + + /* Store the single element from the queue. */ + tcg_gen_ld_i64(fq, tcg_env, offsetof(CPUSPARCState, fq.d)); + tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN_4); + + /* Mark the queue empty, transitioning to fp_execute state. */ + tcg_gen_st_i32(tcg_constant_i32(0), tcg_env, + offsetof(CPUSPARCState, fsr_qne)); + dc->fsr_qne = 0; + } else { + gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); + } return true; +#else + qemu_build_not_reached(); +#endif } static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index fbcb4f7aef..923f348580 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -644,8 +644,8 @@ STF 11 ..... 100100 ..... . ............. @r_r_ri_na STFSR 11 00000 100101 ..... . ............. @n_r_ri STXFSR 11 00001 100101 ..... . ............. @n_r_ri { - STQF 11 ..... 100110 ..... . ............. @q_r_ri_na - STDFQ 11 ----- 100110 ----- - ------------- + STQF 11 ..... 100110 ..... . ............. @q_r_ri_na # v9 + STDFQ 11 ..... 100110 ..... . ............. @r_r_ri # v7,v8 } STDF 11 ..... 100111 ..... . ............. @d_r_ri_na From patchwork Fri Aug 16 07:23:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13765562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04A7FC531DE for ; Fri, 16 Aug 2024 07:24:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1serJB-0007d4-A9; Fri, 16 Aug 2024 03:23:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1serJ9-0007XG-QX for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:35 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1serJ7-00044i-QV for qemu-devel@nongnu.org; Fri, 16 Aug 2024 03:23:35 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-20202df1c2fso5491355ad.1 for ; Fri, 16 Aug 2024 00:23:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1723793012; x=1724397812; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eY2K2/64+QKeWeBSKyuHFBnKeWv7V3FsHg7jq9ZTy0Y=; b=htwc9HDy9A5i1b3ySgrLTt1bDGsUOaAmdgPBG0/do1ATFHrmTXxwJhbsUOJxcUkgks 2bvnHhCOx+8wf93ftYdnWZE+xkGt+P02M726jFFdMD98p+Da0D+dL/TONOLivyTj53Dl G9GHCDsX/jqSIKOunuW4V5eKkD19eq/pcLvq/nYGqVS/iEPosbQpCzt/HxNus/O/AYHc U1xB160psscd2/9S+CH9tyc5Rw//1fRVh/W5gBiKLl5CmyDURmlcovbAK9mbZ6njKvGF qfZ7c85gkwpCXq8Yo5C8gbvb4QiQpINAFKAhI0Azx1+gQqDm6hfgG1Mz1/Ja0x3T9+Ag CXvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723793012; x=1724397812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eY2K2/64+QKeWeBSKyuHFBnKeWv7V3FsHg7jq9ZTy0Y=; b=aEkRVIHTCkMDgEzCqjPHup06gaMx9rrFRQwWoOt4hFd+u0MeQNLiIciwoUjM2Yk6IF 2vW1vcruTaRgzgyIj542BgNrZWzwRI1Y97cP3krbYs6SxJ6gxvJEE9SLAw8VnrBCUqrm ISQb1O/cC4huvW70urRW3iAnx1VmF5Zt1dCT1V6/PvDT9MWclEgf4mikGoy/wJFD5T2y MCmKUbHyzga3gRoCJ/yvRVb7pV+MzFBdB735+sJnMzcqgnUhTIlqOudeWpmLmBrQwIzt a+IsswkJirRwo4v9lIX+YleOyYbiynBEgL7gHrzQG+Qm/m8PvWFcam7J5Ee+UWlWNrZI Yd9g== X-Gm-Message-State: AOJu0Yyxe1p5PqoDUhqxZZI0Mm+yuNgLW3Gw4erF+Xbqj/c1PEvflOBg sgKiQPjneV0b3sP1Sq6C0Ljzj4/sK1zOqz8kJ5JE/SEMZYnJ0B/uLBk6H9eZfUcJWh+TFST/mzZ /S2I= X-Google-Smtp-Source: AGHT+IETvN1H6mgHjSKA+hzSjemJzQx9Q9EdAwQuyAtKy/60xf74yVwhro81lq6qRMuY8/6RW0s+fg== X-Received: by 2002:a17:903:3607:b0:1fb:9cbf:b4e3 with SMTP id d9443c01a7336-2020625cdf1mr30627165ad.22.1723793011911; Fri, 16 Aug 2024 00:23:31 -0700 (PDT) Received: from stoup.. (2403-580a-f89b-0-1b6b-8c7b-90f9-144f.ip6.aussiebb.net. [2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com Subject: [PATCH v3 6/6] target/sparc: Add gen_trap_if_nofpu_fpexception Date: Fri, 16 Aug 2024 17:23:11 +1000 Message-ID: <20240816072311.353234-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Model fp_exception state, in which only fp stores are allowed until such time as the FQ has been flushed. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 90 +++++++++++++++++++++++++++------------- 1 file changed, 61 insertions(+), 29 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6d4c0e79c9..46eb27c497 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1465,15 +1465,48 @@ static void gen_op_fpexception_im(DisasContext *dc, int ftt) gen_exception(dc, TT_FP_EXCP); } -static int gen_trap_ifnofpu(DisasContext *dc) +static bool gen_trap_ifnofpu(DisasContext *dc) { #if !defined(CONFIG_USER_ONLY) if (!dc->fpu_enabled) { gen_exception(dc, TT_NFPU_INSN); - return 1; + return true; } #endif - return 0; + return false; +} + +static bool gen_trap_iffpexception(DisasContext *dc) +{ +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) + /* + * There are 3 states for the sparc32 fpu: + * Normally the fpu is in fp_execute, and all insns are allowed. + * When an exception is signaled, it moves to fp_exception_pending state. + * Upon seeing the next FPop, the fpu moves to fp_exception state, + * populates the FQ, and generates an fp_exception trap. + * The fpu remains in fp_exception state until FQ becomes empty + * after execution of a STDFQ instruction. While the fpu is in + * fp_exception state, and FPop, fp load or fp branch insn will + * return to fp_exception_pending state, set FSR.FTT to sequence_error, + * and the insn will not be entered into the FQ. + * + * In QEMU, we do not model the fp_exception_pending state and + * instead populate FQ and raise the exception immediately. + * But we can still honor fp_exception state by noticing when + * the FQ is not empty. + */ + if (dc->fsr_qne) { + gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); + return true; + } +#endif + return false; +} + +static bool gen_trap_if_nofpu_fpexception(DisasContext *dc) +{ + return gen_trap_ifnofpu(dc) || gen_trap_iffpexception(dc); } /* asi moves */ @@ -2643,7 +2676,7 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) { DisasCompare cmp; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } gen_fcompare(&cmp, a->cc, a->cond); @@ -4482,7 +4515,7 @@ static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) if (addr == NULL) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (sz == MO_128 && gen_trap_float128(dc)) { @@ -4510,6 +4543,7 @@ static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) if (addr == NULL) { return false; } + /* Store insns are ok in fp_exception_pending state. */ if (gen_trap_ifnofpu(dc)) { return true; } @@ -4574,7 +4608,7 @@ static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) if (addr == NULL) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4598,7 +4632,7 @@ static bool do_ldxfsr(DisasContext *dc, arg_r_r_ri *a, bool entire) if (addr == NULL) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4635,6 +4669,7 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) if (addr == NULL) { return false; } + /* Store insns are ok in fp_exception_pending state. */ if (gen_trap_ifnofpu(dc)) { return true; } @@ -4677,7 +4712,7 @@ static bool do_ff(DisasContext *dc, arg_r_r *a, { TCGv_i32 tmp; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4718,7 +4753,7 @@ static bool do_env_ff(DisasContext *dc, arg_r_r *a, { TCGv_i32 tmp; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4738,7 +4773,7 @@ static bool do_env_fd(DisasContext *dc, arg_r_r *a, TCGv_i32 dst; TCGv_i64 src; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4758,7 +4793,7 @@ static bool do_dd(DisasContext *dc, arg_r_r *a, { TCGv_i64 dst, src; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4780,7 +4815,7 @@ static bool do_env_dd(DisasContext *dc, arg_r_r *a, { TCGv_i64 dst, src; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4820,7 +4855,7 @@ static bool do_env_df(DisasContext *dc, arg_r_r *a, TCGv_i64 dst; TCGv_i32 src; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4863,7 +4898,7 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, { TCGv_i128 t; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -4884,7 +4919,7 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, TCGv_i128 src; TCGv_i32 dst; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -4907,7 +4942,7 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, TCGv_i128 src; TCGv_i64 dst; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -4930,7 +4965,7 @@ static bool do_env_qf(DisasContext *dc, arg_r_r *a, TCGv_i32 src; TCGv_i128 dst; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -4953,10 +4988,7 @@ static bool do_env_qd(DisasContext *dc, arg_r_r *a, TCGv_i64 src; TCGv_i128 dst; - if (gen_trap_ifnofpu(dc)) { - return true; - } - if (gen_trap_float128(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -5013,7 +5045,7 @@ static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, { TCGv_i32 src1, src2; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -5222,7 +5254,7 @@ static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, { TCGv_i64 dst, src1, src2; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -5246,7 +5278,7 @@ static bool trans_FsMULd(DisasContext *dc, arg_r_r_r *a) TCGv_i64 dst; TCGv_i32 src1, src2; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (!(dc->def->features & CPU_FEATURE_FSMULD)) { @@ -5355,7 +5387,7 @@ static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, { TCGv_i128 src1, src2; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -5379,7 +5411,7 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a) TCGv_i64 src1, src2; TCGv_i128 dst; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -5469,7 +5501,7 @@ static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, bool e) if (avail_32(dc) && a->cc != 0) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -5493,7 +5525,7 @@ static bool do_fcmpd(DisasContext *dc, arg_FCMPd *a, bool e) if (avail_32(dc) && a->cc != 0) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -5517,7 +5549,7 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e) if (avail_32(dc) && a->cc != 0) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) {