From patchwork Thu Aug 15 18:26:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonino Maniscalco X-Patchwork-Id: 13765609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42101C3DA4A for ; Fri, 16 Aug 2024 07:39:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8585410E5B3; Fri, 16 Aug 2024 07:39:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IQ2yt28F"; dkim-atps=neutral Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by gabe.freedesktop.org (Postfix) with ESMTPS id A9EF510E4E8; Thu, 15 Aug 2024 18:27:39 +0000 (UTC) Received: by mail-lj1-f181.google.com with SMTP id 38308e7fff4ca-2f01e9f53e3so19442741fa.1; Thu, 15 Aug 2024 11:27:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723746457; x=1724351257; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kfyNitr7n9IBeiytQhNaMqBxtLdQ27gFGfEYrZl43AU=; b=IQ2yt28Flnt5/cW6s4gd9CWZQT8kby8S7qVgVEPmKbuP6pXRJmdTzLgB5xTXiDvSUW qNnmDi0Zji/Yc3gP/T263OM+OPLXcklviRS9Oabz9Nz+FO+Kfh772n5ZHF4F9j0PUVoE 3RQwM92KadroZhWrnqsxtnbSpubp7hUS/EkeMOViJvGpjS4ydSek1D3ep/HBX6CT/wDp tTRhtayYaqBPTF+Kpn+PR4Z6PnrxuPgXX75epe6DFsB0Xt1GIwK4H2hCeT9xm5BvHeyH KdjOq/0cyjRKU8Dc251AqM/45K8rmCOkSofp/8Ah0SUUZ1Y4L5drkQZ1EQaUaZQmC2Am qipQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723746457; x=1724351257; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kfyNitr7n9IBeiytQhNaMqBxtLdQ27gFGfEYrZl43AU=; b=ENK2l9j33t6mtIX10lWEqsZG599C50hJBLSG8Loazvu6FlxYGATZ+5DG+TA2XMfcmW eEnLD79KQz7dOnx6h6xYl9/8hgcyDp6jTe20lYCjP5fmin2+JcJkslQ7KlUsEX7XiZYj ZPDX7R5EFEyRmMgZqVe0mTBZNYJYT9LMfRvosdXqLqHA1MY7ZldtuRQerH6/G8hBaAoL i/VhaN6tZBjFUdwkr3U+PheKD442SkZWyddz6rp42tY+LASJ1EVfHXlATYft+Vh2LltB 7aTqQ0UVmCV9gHfvlbnuQqA0kHr2J5lvCAT8Bnn7ZrDv0BbbwNVLVsiPgdVRBFtRTSk5 tt1A== X-Forwarded-Encrypted: i=1; AJvYcCUBdl0KWsI9vO5rF6TwvSoRzg8fGcyRrfpLNwu0bx+22KRbvPxHqHaoPoi4Ub/8OeYDFtFNhq1sn/qylxTkPQecr0HdZs9A/VugvFcmyo2+MOC+4jdyvAe2kUiFNp5HlQ/1Pe2eNqGRiWWKaTE9a16j X-Gm-Message-State: AOJu0Yy+s7hhQCz2Hhat8tp+vXZj0E3hDf9lwHkyKj4tKlWsAMFx4CkJ Qg9jtXuo4/vuh2ddZNc2cUm3JOG68x+kfcaBEYpcYPaGEBC7d/MD X-Google-Smtp-Source: AGHT+IFBVz0TzJtS4M+sYECsv1VIhUSvNMY2XP3x5/1iARu7qmeuI+rqZuBoqE29ZD802zvcHsRFxg== X-Received: by 2002:a2e:9053:0:b0:2ef:2e98:9718 with SMTP id 38308e7fff4ca-2f3be583963mr4671051fa.15.1723746457166; Thu, 15 Aug 2024 11:27:37 -0700 (PDT) Received: from [192.168.1.13] (host-79-35-172-29.retail.telecomitalia.it. [79.35.172.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383947187sm133814366b.166.2024.08.15.11.27.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 11:27:36 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 15 Aug 2024 20:26:11 +0200 Subject: [PATCH 1/7] drm/msm: Fix bv_fence being used as bv_rptr MIME-Version: 1.0 Message-Id: <20240815-preemption-a750-t-v1-1-7bda26c34037@gmail.com> References: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> In-Reply-To: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Antonino Maniscalco X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723746454; l=1437; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=5UQUbB4gp80E1aCA4nhyaMM7cChO8qWJiCOBtxcnjyU=; b=WStWfdviZV2WJZlLrsE28/bmfEOARulhUrSCokZ1bsiJf3LoqdAH8EezgpQo+F4dfCNvp1rag EzGAwabZffKAK0pipd9g5pUbKWt31CzLyz3RML+2SXrAEHDR2OM2fKI X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= X-Mailman-Approved-At: Fri, 16 Aug 2024 07:39:16 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The bv_fence field of rbmemptrs was being used incorrectly as the BV rptr shadow pointer in some places. Add a bv_rptr field and change the code to use that instead. Signed-off-by: Antonino Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index bcaec86ac67a..32a4faa93d7f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1132,7 +1132,7 @@ static int hw_init(struct msm_gpu *gpu) /* ..which means "always" on A7xx, also for BV shadow */ if (adreno_is_a7xx(adreno_gpu)) { gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR, - rbmemptr(gpu->rb[0], bv_fence)); + rbmemptr(gpu->rb[0], bv_rptr)); } /* Always come up on rb 0 */ diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h index 0d6beb8cd39a..40791b2ade46 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -31,6 +31,7 @@ struct msm_rbmemptrs { volatile uint32_t rptr; volatile uint32_t fence; /* Introduced on A7xx */ + volatile uint32_t bv_rptr; volatile uint32_t bv_fence; volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; From patchwork Thu Aug 15 18:26:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonino Maniscalco X-Patchwork-Id: 13765613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2ED9BC531DE for ; Fri, 16 Aug 2024 07:39:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AADA310E5B8; Fri, 16 Aug 2024 07:39:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KP6KJPl0"; dkim-atps=neutral Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3C1FE10E4E8; Thu, 15 Aug 2024 18:27:41 +0000 (UTC) Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-5bd1a9bdce4so1629629a12.3; Thu, 15 Aug 2024 11:27:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723746459; x=1724351259; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IJZcAdXengnxQsRuBCfXSm3/IR7ldhfXkm+AS24y8lo=; b=KP6KJPl0V4LH8ng39rItus3Ic9tOA2t3BSOMl2Yyik521ao5okoDXfvz9VKJnkCE7g rgh3kLw7t5WyWADcJPhvBJRdZlzUtVcy9Z0woX5jau1IKyDT7BXkx7uBBNF7piZ2U7RF t3v267JmMeidHyj05QbAg0R+41MppFHH3lf9Z/tPe6tioKGqZ9/sVWkWlqgvM3cYju7R KCqhKCiqLGBgUdr0JonaxaztrO6qOBbLkYeXw0tL36f/5mndOr8NtJHfLV2Bmi/E3rv6 zbniEDTUAnQj3/M69YH4J5Vj6ALxNcXmTBvxGLykUj0HAQWGNpA9GjU9WaI4gz72ni2T guFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723746459; x=1724351259; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IJZcAdXengnxQsRuBCfXSm3/IR7ldhfXkm+AS24y8lo=; b=EZE64qbQS+fmqXn7sHJybmE5q5y3tKG8XGZ2WTn5NKn0xxTnIlPjwtcdRGdFTbeM5r i7GTknYrpITCZ+uardMOCYf4KdCMl/YiLTUQKGfNesMQfDUk71CDcwpRXYW+9tJf3Nyq sTr6hblCKtLOY07w0gLsyqwkfj6PuzFEw95tFRh3CnQLUXTuxLZxSMXXBjc8GptfRJoe ZTD/y2xdYQT6mfU+kQDx5tvoSJzWxpC1lmZIJt5wTQq+LLa5xW0eMFxGa9sKgqimcNyZ 3jkxDO/u6eM0/djHnT/Z1kCQiqPHM80/ulOktPWxM7jFk0Qjaq6HJOmEXCc5sL4m9M7t uz3g== X-Forwarded-Encrypted: i=1; AJvYcCWxGL/QIsL0FrFVejbmcxNLaEARlV6vcVPABBt9mKVIb7IJCsgwDSgJLQmVpRcgocVtmFiW3d73Em7bGcFy1ESKDATz+zjDOE1zQJt2Y/sL/C5nZadv7//v/B5OmQIVeZW021cL4fO1XgC3JmTiILc7 X-Gm-Message-State: AOJu0Yzi1H921QVe1/FMcYxHFjNlWrBrdIcPOP54wG1gDXpB1RrHT6Yl /Yk9GALqe7PIQiz0uwfJp4pOn4+JV9Q0ipGcRkjh2ddcUfdsa+qv X-Google-Smtp-Source: AGHT+IHF29C4IC0GAOmzG1LjmAPZsf2ZGqUe1rN816bkCVSN1Wb+2P06Jr/oWhrvp2Jca9UErpPefQ== X-Received: by 2002:a17:906:d54e:b0:a77:aa6d:e0c7 with SMTP id a640c23a62f3a-a839293e973mr28486566b.30.1723746458735; Thu, 15 Aug 2024 11:27:38 -0700 (PDT) Received: from [192.168.1.13] (host-79-35-172-29.retail.telecomitalia.it. [79.35.172.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383947187sm133814366b.166.2024.08.15.11.27.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 11:27:38 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 15 Aug 2024 20:26:12 +0200 Subject: [PATCH 2/7] drm/msm: Add submitqueue setup and close MIME-Version: 1.0 Message-Id: <20240815-preemption-a750-t-v1-2-7bda26c34037@gmail.com> References: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> In-Reply-To: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Antonino Maniscalco , Sharat Masetty X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723746454; l=2616; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=20oAYS3mWUIGbiEDLsRaCMFHZNrME6mT7hQZgI2Sra8=; b=vSb1NAIThr44gOy1adLEVkRxa/kzpiR9f4HJ/bpnUqNFI0dToOp74LyZ/El4114l5ebgPe7oT 7zYefoUGrPpA0Sj1m4eI+T3puPlPLI0vLUu2IaZ+1tO/TWm9qvPGIln X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= X-Mailman-Approved-At: Fri, 16 Aug 2024 07:39:16 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This patch adds a bit of infrastructure to give the different Adreno targets the flexibility to setup the submitqueues per their needs. Signed-off-by: Sharat Masetty Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/msm_gpu.h | 7 +++++++ drivers/gpu/drm/msm/msm_submitqueue.c | 10 ++++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 1f02bb9956be..70f5c18e5aee 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -92,6 +92,10 @@ struct msm_gpu_funcs { * for cmdstream that is buffered in this FIFO upstream of the CP fw. */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); + int (*submitqueue_setup)(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue); + void (*submitqueue_close)(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue); }; /* Additional state for iommu faults: */ @@ -522,6 +526,9 @@ struct msm_gpu_submitqueue { struct mutex lock; struct kref ref; struct drm_sched_entity *entity; + struct msm_gpu *gpu; + struct drm_gem_object *bo; + uint64_t bo_iova; }; struct msm_gpu_state_bo { diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index 0e803125a325..4ffb336d9a60 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -71,6 +71,11 @@ void msm_submitqueue_destroy(struct kref *kref) struct msm_gpu_submitqueue *queue = container_of(kref, struct msm_gpu_submitqueue, ref); + struct msm_gpu *gpu = queue->gpu; + + if (gpu && gpu->funcs->submitqueue_close) + gpu->funcs->submitqueue_close(gpu, queue); + idr_destroy(&queue->fence_idr); msm_file_private_put(queue->ctx); @@ -160,6 +165,7 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, { struct msm_drm_private *priv = drm->dev_private; struct msm_gpu_submitqueue *queue; + struct msm_gpu *gpu = priv->gpu; enum drm_sched_priority sched_prio; unsigned ring_nr; int ret; @@ -195,6 +201,7 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, queue->ctx = msm_file_private_get(ctx); queue->id = ctx->queueid++; + queue->gpu = gpu; if (id) *id = queue->id; @@ -207,6 +214,9 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, write_unlock(&ctx->queuelock); + if (gpu && gpu->funcs->submitqueue_setup) + gpu->funcs->submitqueue_setup(gpu, queue); + return 0; } From patchwork Thu Aug 15 18:26:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonino Maniscalco X-Patchwork-Id: 13765607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D16DC3DA4A for ; Fri, 16 Aug 2024 07:39:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0133210E5B1; Fri, 16 Aug 2024 07:39:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Xd4N3p1l"; dkim-atps=neutral Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3740A10E4E8; Thu, 15 Aug 2024 18:27:42 +0000 (UTC) Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-5a156557029so1483433a12.2; Thu, 15 Aug 2024 11:27:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723746460; x=1724351260; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=urijkc3f3VRhrpzAWKCHRZEPKCuPoQovMvk9GPz7bsI=; b=Xd4N3p1lrjn6qnlKEasfl9xNXZmFKW8HgeTd8dgR92slnOovc/HNvHM7n6HnFyr5j2 28+nF5vzNsbbPIDpc3W24dMr2onjsztf7JCHD0ZHlvr0OhfgdYLzv0/r1I3jDwH4YBoa 9wNWbuLqdEEhOr8lz+BHn0xuOEL/sk/52SIp9aGdXd2SZrVcrCh0J8KM65cBICAwrozF I52zNpfHaZ8G+Qrgatcx0KPZvn1AwOdgSaSiMwmEb+csszmQyMFiv0rHTyhzyiTQVXut 2O6vnY4HB8H3dY1kN2Y1i2uMX4FJlmrQh2l9NEJ/iwtaFdyvN6sFFs4Cm6lnqo4nIYrw uGiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723746460; x=1724351260; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=urijkc3f3VRhrpzAWKCHRZEPKCuPoQovMvk9GPz7bsI=; b=XkSv93GOJYyWg31vGH1N+Irs/i05tQtExwnv3EMIdgarQp9Jzpw1R+NOhtcHgrvis2 MSUri0dr9e2A7wOOFfCmNiXQoR9ryyjgU7003QCC5GIRNMb7EumobkmtoCKX7qwjL8d+ 4W+FdSe9dBCd5yKZnOGTD3BFCeypjR3/n4VEWwyH46tnBYFdSm+gBz4IFOCbUaK72tvT 4OTVCMDJ1B9x/ZFAWqQC0qnLxGnYviZE+lxIr6j3KFFERo3hQGsj1+GcrminA5O65MUK AQF6mQqZMbob4qx7hSxyaA2LL4czYmoFVPHcxGcJ13GEMLfYD2G5lqrQzIVoDINml/+N VnuQ== X-Forwarded-Encrypted: i=1; AJvYcCV3jjaetszaBiAlq22jM8CWzmc9TLsdzLxd+2av2NUfgjelEVzEoaIIosfTNx6BVCQtMZaQiAUrgb99G6PuBbChO/SfOY94CquuNY5SVNbcEgRgtN0KKhJNEUQOS22EfSDTJF0LRI+qm1gWRNqcevn5 X-Gm-Message-State: AOJu0YwGw8INxB13pKjwrqnSVEccZAByN3Y361URWkNMHXZ7K4jBkYU5 JRpsKIlnzlELIDaK/bn9DFCfijB27qEmnVsADVQQ7rD7Qq5ijVvu X-Google-Smtp-Source: AGHT+IFPZ04x5q729U6SozDVg01mhTEcXdVagZpRJc7WA7XSPWNkD+YY2Ys5R20/caD9P8YjpOsVag== X-Received: by 2002:a17:907:2da6:b0:a7a:9144:e23b with SMTP id a640c23a62f3a-a83928d3597mr32453666b.19.1723746460231; Thu, 15 Aug 2024 11:27:40 -0700 (PDT) Received: from [192.168.1.13] (host-79-35-172-29.retail.telecomitalia.it. [79.35.172.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383947187sm133814366b.166.2024.08.15.11.27.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 11:27:39 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 15 Aug 2024 20:26:13 +0200 Subject: [PATCH 3/7] drm/msm: Add a `preempt_record_size` field MIME-Version: 1.0 Message-Id: <20240815-preemption-a750-t-v1-3-7bda26c34037@gmail.com> References: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> In-Reply-To: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Antonino Maniscalco X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723746454; l=1771; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=WIdWkEj6n6EKxeTaGaPrvswEStAjEcIUss+Uq6HmkxU=; b=cdA5UOeldSfzsfOh+2uPqUWo4UgfkDMyDFPeXHAf7JKUKQafh23+o+lNgxZesuz8HMBjNfJT2 XbSJ7pdMUM5AcJb2XW8N5sEn/s5iwrMC+/Huel9if6lm001Kp49EV+9 X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= X-Mailman-Approved-At: Fri, 16 Aug 2024 07:39:16 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Adds a field to `adreno_info` to store the GPU specific preempt record size. Signed-off-by: Antonino Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 3 +++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 68ba9aed5506..4cee54d57646 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1190,6 +1190,7 @@ static const struct adreno_info a7xx_gpus[] = { .protect = &a730_protect, }, .address_space_size = SZ_16G, + .preempt_record_size = 2860 * SZ_1K, }, { .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ .family = ADRENO_7XX_GEN2, @@ -1209,6 +1210,7 @@ static const struct adreno_info a7xx_gpus[] = { .gmu_chipid = 0x7020100, }, .address_space_size = SZ_16G, + .preempt_record_size = 4192 * SZ_1K, }, { .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ .family = ADRENO_7XX_GEN2, @@ -1245,6 +1247,7 @@ static const struct adreno_info a7xx_gpus[] = { .gmu_chipid = 0x7090100, }, .address_space_size = SZ_16G, + .preempt_record_size = 3572 * SZ_1K, } }; DECLARE_ADRENO_GPULIST(a7xx); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 1ab523a163a0..6b1888280a83 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -111,6 +111,7 @@ struct adreno_info { * {SHRT_MAX, 0} sentinal. */ struct adreno_speedbin *speedbins; + u64 preempt_record_size; }; #define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 } From patchwork Thu Aug 15 18:26:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonino Maniscalco X-Patchwork-Id: 13765615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69A94C3DA4A for ; Fri, 16 Aug 2024 07:39:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BB74810E5B9; Fri, 16 Aug 2024 07:39:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VK5G8BBk"; dkim-atps=neutral Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) by gabe.freedesktop.org (Postfix) with ESMTPS id 563CF10E4E8; Thu, 15 Aug 2024 18:27:44 +0000 (UTC) Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-a7abe5aa9d5so140393366b.1; Thu, 15 Aug 2024 11:27:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723746462; x=1724351262; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hBU4OJ15B2DN4aV48MLFoxYLZXdk+QK/fVuJgHm1UC8=; b=VK5G8BBkZ6r2gBHOsZ7U6oXhXJbJ1iiHe/n8unRnUPNBp6DmVCcmnltAk7gQmpeQEO kECbc6tRR7+G+EEsD7vzXaA+kHQl8yQ0NHVfNsXUd5G5tsGlcleJC2LvMmLHYSUpIdLq GOVL3vHV4C8xrEvFPKNRh3Mx6hobvyVi/F3ttwaJQ3VeeK82eHdsuK74dLdSYqMs1Mhf L0zZ40VQHWpyRCpLXJ0/1ILqbr3xvv2xSHGjiBW5nB/BqVR1D9nxmaWNbLFV5XLQWmPI XCOHWIb5azpZkcwGm2Ip/QumGW4tp0d/QVRAjUkyo58Wq3dPpmmVBDjWglxIqKSb29OS 3k9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723746462; x=1724351262; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hBU4OJ15B2DN4aV48MLFoxYLZXdk+QK/fVuJgHm1UC8=; b=rg6WHw1HIhwKXGd0OpYl/Joj8Q+AIKQaMa6sJm7ZRLWBzsg0G5BZBb3ThKgO8UTA0G aUHCa8lYXADM2a3Q434GB6bbQvY3ajYSLBqqrjNWOBi8erze8awC2gSH7WR0d29vknGC uY+S9wNkDAdqQXUys64WRujkUU5KtLttiP4OI9tJkONTF1MNhd0W66pDWmHUwC6zpCoH 0+VKA2nbn4de/8tdbSUI1zAQwYXsBLIxr3/It1bwMXnMjYphzmQntRBC4jrAwzUFnoIr 3s2y4BxJ1JaEEfgBMCSpUWtCXCzRPQgRUWI+S3BN0CxUAyUeBOwrXVt0VOAlBCJp8jEy nNtQ== X-Forwarded-Encrypted: i=1; AJvYcCUwxFifdsoR/4d7PRCAEB6Y7m5PzaBWRO0+Tu2aXb31UqtS64VGCK/1uhtfpRgPqDOqHF6SExJ7owHQpHT1OnMlTagfqIxFJ1DT9XWnjsPCB7wCbQJPbqPNBY1XBnMeYuc7s5AlCyDAf0nkoN7ZZGDb X-Gm-Message-State: AOJu0YxnLOSwiisZA3CBwYb7ddksUVwPvqEXNO1u9cbzs+gAxnzQ1mPd pfdaIdKHl9A0caICE4wfcZqCsrew5if09MAzuSXv5Sagj27lBZ1j X-Google-Smtp-Source: AGHT+IG33l9Eeu0I0HnbeXsnjHSt7HZ/zUzc5bqfMn5D9+G9vA9odesvW0sqBjQLxAIIR5gCInUZIw== X-Received: by 2002:a17:907:72c7:b0:a7a:ca07:1de3 with SMTP id a640c23a62f3a-a8392a38521mr32185866b.56.1723746462034; Thu, 15 Aug 2024 11:27:42 -0700 (PDT) Received: from [192.168.1.13] (host-79-35-172-29.retail.telecomitalia.it. [79.35.172.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383947187sm133814366b.166.2024.08.15.11.27.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 11:27:41 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 15 Aug 2024 20:26:14 +0200 Subject: [PATCH 4/7] drm/msm/A6xx: Implement preemption for A7XX targets MIME-Version: 1.0 Message-Id: <20240815-preemption-a750-t-v1-4-7bda26c34037@gmail.com> References: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> In-Reply-To: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Antonino Maniscalco , Sharat Masetty X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723746454; l=38004; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=xXPhqSrr01z43rwuIsFXQgcvJvf6kjAdgk4HF1hFwR4=; b=kBL09ZVa0+EYVtBpYYT6aPPzIACyJopSFjCWdrinqB+6U2gmIFEpzvOS1Aoi8zntRe2bf6v25 VDnW110vX5uB3aTbWFIS2uSjcQ1NPSmJYcomOCwyO4YF08sp7bcSlBu X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= X-Mailman-Approved-At: Fri, 16 Aug 2024 07:39:16 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This patch implements preemption feature for A6xx targets, this allows the GPU to switch to a higher priority ringbuffer if one is ready. A6XX hardware as such supports multiple levels of preemption granularities, ranging from coarse grained(ringbuffer level) to a more fine grained such as draw-call level or a bin boundary level preemption. This patch enables the basic preemption level, with more fine grained preemption support to follow. Signed-off-by: Sharat Masetty Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 323 +++++++++++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 168 ++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 434 ++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_ringbuffer.h | 7 + 5 files changed, 924 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index f5e2838c6a76..32e915109a59 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -23,6 +23,7 @@ adreno-y := \ adreno/a6xx_gpu.o \ adreno/a6xx_gmu.o \ adreno/a6xx_hfi.o \ + adreno/a6xx_preempt.o \ adreno-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 32a4faa93d7f..1a90db5759b8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -16,6 +16,83 @@ #define GPU_PAS_ID 13 +/* IFPC & Preemption static powerup restore list */ +static const uint32_t a7xx_pwrup_reglist[] = { + REG_A6XX_UCHE_TRAP_BASE, + REG_A6XX_UCHE_TRAP_BASE + 1, + REG_A6XX_UCHE_WRITE_THRU_BASE, + REG_A6XX_UCHE_WRITE_THRU_BASE + 1, + REG_A6XX_UCHE_GMEM_RANGE_MIN, + REG_A6XX_UCHE_GMEM_RANGE_MIN + 1, + REG_A6XX_UCHE_GMEM_RANGE_MAX, + REG_A6XX_UCHE_GMEM_RANGE_MAX + 1, + REG_A6XX_UCHE_CACHE_WAYS, + REG_A6XX_UCHE_MODE_CNTL, + REG_A6XX_RB_NC_MODE_CNTL, + REG_A6XX_RB_CMP_DBG_ECO_CNTL, + REG_A7XX_GRAS_NC_MODE_CNTL, + REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, + REG_A6XX_UCHE_GBIF_GX_CONFIG, + REG_A6XX_UCHE_CLIENT_PF, +}; + +static const uint32_t a7xx_ifpc_pwrup_reglist[] = { + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A6XX_CP_DBG_ECO_CNTL, + REG_A6XX_CP_PROTECT_CNTL, + REG_A6XX_CP_PROTECT(0), + REG_A6XX_CP_PROTECT(1), + REG_A6XX_CP_PROTECT(2), + REG_A6XX_CP_PROTECT(3), + REG_A6XX_CP_PROTECT(4), + REG_A6XX_CP_PROTECT(5), + REG_A6XX_CP_PROTECT(6), + REG_A6XX_CP_PROTECT(7), + REG_A6XX_CP_PROTECT(8), + REG_A6XX_CP_PROTECT(9), + REG_A6XX_CP_PROTECT(10), + REG_A6XX_CP_PROTECT(11), + REG_A6XX_CP_PROTECT(12), + REG_A6XX_CP_PROTECT(13), + REG_A6XX_CP_PROTECT(14), + REG_A6XX_CP_PROTECT(15), + REG_A6XX_CP_PROTECT(16), + REG_A6XX_CP_PROTECT(17), + REG_A6XX_CP_PROTECT(18), + REG_A6XX_CP_PROTECT(19), + REG_A6XX_CP_PROTECT(20), + REG_A6XX_CP_PROTECT(21), + REG_A6XX_CP_PROTECT(22), + REG_A6XX_CP_PROTECT(23), + REG_A6XX_CP_PROTECT(24), + REG_A6XX_CP_PROTECT(25), + REG_A6XX_CP_PROTECT(26), + REG_A6XX_CP_PROTECT(27), + REG_A6XX_CP_PROTECT(28), + REG_A6XX_CP_PROTECT(29), + REG_A6XX_CP_PROTECT(30), + REG_A6XX_CP_PROTECT(31), + REG_A6XX_CP_PROTECT(32), + REG_A6XX_CP_PROTECT(33), + REG_A6XX_CP_PROTECT(34), + REG_A6XX_CP_PROTECT(35), + REG_A6XX_CP_PROTECT(36), + REG_A6XX_CP_PROTECT(37), + REG_A6XX_CP_PROTECT(38), + REG_A6XX_CP_PROTECT(39), + REG_A6XX_CP_PROTECT(40), + REG_A6XX_CP_PROTECT(41), + REG_A6XX_CP_PROTECT(42), + REG_A6XX_CP_PROTECT(43), + REG_A6XX_CP_PROTECT(44), + REG_A6XX_CP_PROTECT(45), + REG_A6XX_CP_PROTECT(46), + REG_A6XX_CP_PROTECT(47), + REG_A6XX_CP_AHB_CNTL, +}; + + static inline bool _a6xx_check_idle(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -68,6 +145,8 @@ static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); uint32_t wptr; unsigned long flags; @@ -81,12 +160,26 @@ static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) /* Make sure to wrap wptr if we need to */ wptr = get_wptr(ring); - spin_unlock_irqrestore(&ring->preempt_lock, flags); - /* Make sure everything is posted before making a decision */ mb(); - gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); + /* Update HW if this is the current ring and we are not in preempt*/ + if (!a6xx_in_preempt(a6xx_gpu)) { + /* + * Order the reads of the preempt state and cur_ring. This + * matches the barrier after writing cur_ring. + */ + rmb(); + + if (a6xx_gpu->cur_ring == ring) + gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); + else + ring->skip_inline_wptr = true; + } else { + ring->skip_inline_wptr = true; + } + + spin_unlock_irqrestore(&ring->preempt_lock, flags); } static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, @@ -138,12 +231,14 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, /* * Write the new TTBR0 to the memstore. This is good for debugging. + * Needed for preemption */ - OUT_PKT7(ring, CP_MEM_WRITE, 4); + OUT_PKT7(ring, CP_MEM_WRITE, 5); OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); OUT_RING(ring, lower_32_bits(ttbr)); - OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); + OUT_RING(ring, upper_32_bits(ttbr)); + OUT_RING(ring, ctx->seqno); /* * Sync both threads after switching pagetables and enable BR only @@ -268,12 +363,55 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a6xx_flush(gpu, ring); } +static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring, + struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue) +{ + u64 preempt_offset_priv_secure; + + OUT_PKT7(ring, CP_SET_PSEUDO_REG, 15); + + OUT_RING(ring, SMMU_INFO); + /* don't save SMMU, we write the record from the kernel instead */ + OUT_RING(ring, 0); + OUT_RING(ring, 0); + + /* privileged and non secure buffer save */ + OUT_RING(ring, NON_SECURE_SAVE_ADDR); + OUT_RING(ring, lower_32_bits( + a6xx_gpu->preempt_iova[ring->id] + PREEMPT_OFFSET_PRIV_NON_SECURE)); + OUT_RING(ring, upper_32_bits( + a6xx_gpu->preempt_iova[ring->id] + PREEMPT_OFFSET_PRIV_NON_SECURE)); + OUT_RING(ring, SECURE_SAVE_ADDR); + preempt_offset_priv_secure = + PREEMPT_OFFSET_PRIV_SECURE(a6xx_gpu->base.info->preempt_record_size); + OUT_RING(ring, lower_32_bits( + a6xx_gpu->preempt_iova[ring->id] + preempt_offset_priv_secure)); + OUT_RING(ring, upper_32_bits( + a6xx_gpu->preempt_iova[ring->id] + preempt_offset_priv_secure)); + + /* user context buffer save */ + OUT_RING(ring, NON_PRIV_SAVE_ADDR); + if (queue) { + OUT_RING(ring, lower_32_bits(queue->bo_iova)); + OUT_RING(ring, upper_32_bits(queue->bo_iova)); + } else { + OUT_RING(ring, 0); + OUT_RING(ring, 0); + } + + OUT_RING(ring, COUNTER); + /* seems OK to set to 0 to disable it */ + OUT_RING(ring, 0); + OUT_RING(ring, 0); +} + static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct msm_ringbuffer *ring = submit->ring; + uint64_t scratch_dest = SCRATCH_USER_CTX_IOVA(ring->id, a6xx_gpu); unsigned int i, ibs = 0; /* @@ -283,6 +421,25 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) OUT_PKT7(ring, CP_THREAD_CONTROL, 1); OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); + /* + * If preemption is enabled, then set the pseudo register for the save + * sequence + */ + if (gpu->nr_rings > 1) { + a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue); + + /* + * Ask CP to save the user context buffer's iova address to a + * scratch memory region, this is needed if the CP preempts + * this ring in between this submit's IB list. + */ + OUT_PKT7(ring, CP_MEM_WRITE, 4); + OUT_RING(ring, lower_32_bits(scratch_dest)); + OUT_RING(ring, upper_32_bits(scratch_dest)); + OUT_RING(ring, lower_32_bits(submit->queue->bo_iova)); + OUT_RING(ring, upper_32_bits(submit->queue->bo_iova)); + } + a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), @@ -376,6 +533,8 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); OUT_RING(ring, submit->seqno); + a6xx_gpu->last_seqno[ring->id] = submit->seqno; + /* write the ringbuffer timestamp */ OUT_PKT7(ring, CP_EVENT_WRITE, 4); OUT_RING(ring, CACHE_CLEAN | CP_EVENT_WRITE_0_IRQ | BIT(27)); @@ -389,10 +548,42 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) OUT_PKT7(ring, CP_SET_MARKER, 1); OUT_RING(ring, 0x100); /* IFPC enable */ + /* If preemption is enabled */ + if (gpu->nr_rings > 1) { + /* + * Reset the scratch region as we are done with the + * IB list of this submission + */ + OUT_PKT7(ring, CP_MEM_WRITE, 4); + OUT_RING(ring, lower_32_bits(scratch_dest)); + OUT_RING(ring, upper_32_bits(scratch_dest)); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + + /* Yield the floor on command completion */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + + /* + * If dword[2:1] are non zero, they specify an address for + * the CP to write the value of dword[3] to on preemption + * complete. Write 0 to skip the write + */ + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + /* Data value - not used if the address above is 0 */ + OUT_RING(ring, 0x01); + /* generate interrupt on preemption completion */ + OUT_RING(ring, 0x00); + } + + trace_msm_gpu_submit_flush(submit, gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); a6xx_flush(gpu, ring); + + /* Check to see if we need to start preemption */ + a6xx_preempt_trigger(gpu); } static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) @@ -588,6 +779,89 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); } +static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct adreno_reglist_list reglist[2]; + void *ptr = a6xx_gpu->pwrup_reglist_ptr; + struct cpu_gpu_lock *lock = ptr; + u32 *dest = (u32 *)&lock->regs[0]; + int i, j; + + lock->gpu_req = lock->cpu_req = lock->turn = 0; + lock->ifpc_list_len = ARRAY_SIZE(a7xx_ifpc_pwrup_reglist); + lock->preemption_list_len = ARRAY_SIZE(a7xx_pwrup_reglist); + + /* Static IFPC-only registers */ + reglist[0].regs = a7xx_ifpc_pwrup_reglist; + reglist[0].count = ARRAY_SIZE(a7xx_ifpc_pwrup_reglist); + lock->ifpc_list_len = reglist[0].count; + + /* Static IFPC + preemption registers */ + reglist[1].regs = a7xx_pwrup_reglist; + reglist[1].count = ARRAY_SIZE(a7xx_pwrup_reglist); + lock->preemption_list_len = reglist[1].count; + + /* + * For each entry in each of the lists, write the offset and the current + * register value into the GPU buffer + */ + for (i = 0; i < 2; i++) { + const u32 *r = reglist[i].regs; + + for (j = 0; j < reglist[i].count; j++) { + *dest++ = r[j]; + *dest++ = gpu_read(gpu, r[j]); + } + } + + /* + * The overall register list is composed of + * 1. Static IFPC-only registers + * 2. Static IFPC + preemption registers + * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects) + * + * The first two lists are static. Size of these lists are stored as + * number of pairs in ifpc_list_len and preemption_list_len + * respectively. With concurrent binning, Some of the perfcounter + * registers being virtualized, CP needs to know the pipe id to program + * the aperture inorder to restore the same. Thus, third list is a + * dynamic list with triplets as + * (
), and the length is + * stored as number for triplets in dynamic_list_len. + */ + lock->dynamic_list_len = 0; +} + +static int a7xx_preempt_start(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring = gpu->rb[0]; + + if (gpu->nr_rings <= 1) + return 0; + + /* Turn CP protection off */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); + + /* Yield the floor on command completion */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x01); + /* Generate interrupt on preemption completion */ + OUT_RING(ring, 0x00); + + a6xx_flush(gpu, ring); + + return a6xx_idle(gpu, ring) ? 0 : -EINVAL; +} + static int a6xx_cp_init(struct msm_gpu *gpu) { struct msm_ringbuffer *ring = gpu->rb[0]; @@ -619,6 +893,8 @@ static int a6xx_cp_init(struct msm_gpu *gpu) static int a7xx_cp_init(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct msm_ringbuffer *ring = gpu->rb[0]; u32 mask; @@ -626,6 +902,8 @@ static int a7xx_cp_init(struct msm_gpu *gpu) OUT_PKT7(ring, CP_THREAD_CONTROL, 1); OUT_RING(ring, BIT(27)); + a7xx_patch_pwrup_reglist(gpu); + OUT_PKT7(ring, CP_ME_INIT, 7); /* Use multiple HW contexts */ @@ -656,11 +934,11 @@ static int a7xx_cp_init(struct msm_gpu *gpu) /* *Don't* send a power up reg list for concurrent binning (TODO) */ /* Lo address */ - OUT_RING(ring, 0x00000000); + OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova)); /* Hi address */ - OUT_RING(ring, 0x00000000); + OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova)); /* BIT(31) set => read the regs from the list */ - OUT_RING(ring, 0x00000000); + OUT_RING(ring, BIT(31)); a6xx_flush(gpu, ring); return a6xx_idle(gpu, ring) ? 0 : -EINVAL; @@ -784,6 +1062,16 @@ static int a6xx_ucode_load(struct msm_gpu *gpu) msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); } + a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE, + MSM_BO_WC | MSM_BO_MAP_PRIV, + gpu->aspace, &a6xx_gpu->pwrup_reglist_bo, + &a6xx_gpu->pwrup_reglist_iova); + + if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr)) + return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr); + + msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist"); + return 0; } @@ -1127,6 +1415,8 @@ static int hw_init(struct msm_gpu *gpu) if (a6xx_gpu->shadow_bo) { gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, shadowptr(a6xx_gpu, gpu->rb[0])); + for (unsigned int i = 0; i < gpu->nr_rings; i++) + a6xx_gpu->shadow[i] = 0; } /* ..which means "always" on A7xx, also for BV shadow */ @@ -1135,6 +1425,8 @@ static int hw_init(struct msm_gpu *gpu) rbmemptr(gpu->rb[0], bv_rptr)); } + a6xx_preempt_hw_init(gpu); + /* Always come up on rb 0 */ a6xx_gpu->cur_ring = gpu->rb[0]; @@ -1180,6 +1472,10 @@ static int hw_init(struct msm_gpu *gpu) out: if (adreno_has_gmu_wrapper(adreno_gpu)) return ret; + + /* Last step - yield the ringbuffer */ + a7xx_preempt_start(gpu); + /* * Tell the GMU that we are done touching the GPU and it can start power * management @@ -1557,8 +1853,13 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) a7xx_sw_fuse_violation_irq(gpu); - if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) + if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { msm_gpu_retire(gpu); + a6xx_preempt_trigger(gpu); + } + + if (status & A6XX_RBBM_INT_0_MASK_CP_SW) + a6xx_preempt_irq(gpu); return IRQ_HANDLED; } @@ -2165,6 +2466,8 @@ static const struct adreno_gpu_funcs funcs = { .active_ring = a6xx_active_ring, .irq = a6xx_irq, .destroy = a6xx_destroy, + .submitqueue_setup = a6xx_preempt_submitqueue_setup, + .submitqueue_close = a6xx_preempt_submitqueue_close, #if defined(CONFIG_DRM_MSM_GPU_STATE) .show = a6xx_show, #endif @@ -2331,6 +2634,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_fault_handler); a6xx_calc_ubwc_config(adreno_gpu); + /* Set up the preemption specific bits and pieces for each ringbuffer */ + a6xx_preempt_init(gpu); return gpu; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index e3e5c53ae8af..652e49f01428 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -12,6 +12,31 @@ extern bool hang_debug; +struct cpu_gpu_lock { + uint32_t gpu_req; + uint32_t cpu_req; + uint32_t turn; + union { + struct { + uint16_t list_length; + uint16_t list_offset; + }; + struct { + uint8_t ifpc_list_len; + uint8_t preemption_list_len; + uint16_t dynamic_list_len; + }; + }; + uint64_t regs[62]; +}; + +struct adreno_reglist_list { + /** @reg: List of register **/ + const u32 *regs; + /** @count: Number of registers in the list **/ + u32 count; +}; + /** * struct a6xx_info - a6xx specific information from device table * @@ -31,6 +56,24 @@ struct a6xx_gpu { uint64_t sqe_iova; struct msm_ringbuffer *cur_ring; + struct msm_ringbuffer *next_ring; + + struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS]; + void *preempt[MSM_GPU_MAX_RINGS]; + uint64_t preempt_iova[MSM_GPU_MAX_RINGS]; + uint32_t last_seqno[MSM_GPU_MAX_RINGS]; + + atomic_t preempt_state; + spinlock_t eval_lock; + struct timer_list preempt_timer; + + unsigned int preempt_level; + bool uses_gmem; + bool skip_save_restore; + + struct drm_gem_object *scratch_bo; + void *scratch_ptr; + uint64_t scratch_iova; struct a6xx_gmu gmu; @@ -38,6 +81,10 @@ struct a6xx_gpu { uint64_t shadow_iova; uint32_t *shadow; + struct drm_gem_object *pwrup_reglist_bo; + void *pwrup_reglist_ptr; + uint64_t pwrup_reglist_iova; + bool has_whereami; void __iomem *llc_mmio; @@ -49,6 +96,108 @@ struct a6xx_gpu { #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) +#define SCRATCH_USER_CTX_IOVA(ring_id, a6xx_gpu) \ + (a6xx_gpu->scratch_iova + (ring_id * sizeof(uint64_t))) + +/* + * In order to do lockless preemption we use a simple state machine to progress + * through the process. + * + * PREEMPT_NONE - no preemption in progress. Next state START. + * PREEMPT_START - The trigger is evaluating if preemption is possible. Next + * states: TRIGGERED, NONE + * PREEMPT_FINISH - An intermediate state before moving back to NONE. Next + * state: NONE. + * PREEMPT_TRIGGERED: A preemption has been executed on the hardware. Next + * states: FAULTED, PENDING + * PREEMPT_FAULTED: A preemption timed out (never completed). This will trigger + * recovery. Next state: N/A + * PREEMPT_PENDING: Preemption complete interrupt fired - the callback is + * checking the success of the operation. Next state: FAULTED, NONE. + */ + +enum a6xx_preempt_state { + PREEMPT_NONE = 0, + PREEMPT_START, + PREEMPT_FINISH, + PREEMPT_TRIGGERED, + PREEMPT_FAULTED, + PREEMPT_PENDING, +}; + +/* + * struct a6xx_preempt_record is a shared buffer between the microcode and the + * CPU to store the state for preemption. The record itself is much larger + * (2112k) but most of that is used by the CP for storage. + * + * There is a preemption record assigned per ringbuffer. When the CPU triggers a + * preemption, it fills out the record with the useful information (wptr, ring + * base, etc) and the microcode uses that information to set up the CP following + * the preemption. When a ring is switched out, the CP will save the ringbuffer + * state back to the record. In this way, once the records are properly set up + * the CPU can quickly switch back and forth between ringbuffers by only + * updating a few registers (often only the wptr). + * + * These are the CPU aware registers in the record: + * @magic: Must always be 0xAE399D6EUL + * @info: Type of the record - written 0 by the CPU, updated by the CP + * @errno: preemption error record + * @data: Data field in YIELD and SET_MARKER packets, Written and used by CP + * @cntl: Value of RB_CNTL written by CPU, save/restored by CP + * @rptr: Value of RB_RPTR written by CPU, save/restored by CP + * @wptr: Value of RB_WPTR written by CPU, save/restored by CP + * @_pad: Reserved/padding + * @rptr_addr: Value of RB_RPTR_ADDR_LO|HI written by CPU, save/restored by CP + * @rbase: Value of RB_BASE written by CPU, save/restored by CP + * @counter: GPU address of the storage area for the preemption counters + */ +struct a6xx_preempt_record { + u32 magic; + u32 info; + u32 errno; + u32 data; + u32 cntl; + u32 rptr; + u32 wptr; + u32 _pad; + u64 rptr_addr; + u64 rbase; + u64 counter; + u64 bv_rptr_addr; +}; + +#define A6XX_PREEMPT_RECORD_MAGIC 0xAE399D6EUL + +#define PREEMPT_RECORD_SIZE_FALLBACK(size) \ + ((size) == 0 ? 4192 * SZ_1K : (size)) + +#define PREEMPT_OFFSET_SMMU_INFO 0 +#define PREEMPT_OFFSET_PRIV_NON_SECURE (PREEMPT_OFFSET_SMMU_INFO + 4096) +#define PREEMPT_OFFSET_PRIV_SECURE(size) \ + (PREEMPT_OFFSET_PRIV_NON_SECURE + PREEMPT_RECORD_SIZE_FALLBACK(size)) +#define PREEMPT_SIZE(size) \ + (PREEMPT_OFFSET_PRIV_SECURE(size) + PREEMPT_RECORD_SIZE_FALLBACK(size)) + +/* + * The preemption counter block is a storage area for the value of the + * preemption counters that are saved immediately before context switch. We + * append it on to the end of the allocation for the preemption record. + */ +#define A6XX_PREEMPT_COUNTER_SIZE (16 * 4) + +#define A6XX_PREEMPT_USER_RECORD_SIZE (192 * 1024) + +struct a7xx_cp_smmu_info { + u32 magic; + u32 _pad4; + u64 ttbr0; + u32 asid; + u32 context_idr; + u32 context_bank; +}; + +#define GEN7_CP_SMMU_INFO_MAGIC 0x241350d5UL + /* * Given a register and a count, return a value to program into * REG_CP_PROTECT_REG(n) - this will block both reads and writes for @@ -106,6 +255,25 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); +void a6xx_preempt_init(struct msm_gpu *gpu); +void a6xx_preempt_hw_init(struct msm_gpu *gpu); +void a6xx_preempt_trigger(struct msm_gpu *gpu); +void a6xx_preempt_irq(struct msm_gpu *gpu); +void a6xx_preempt_fini(struct msm_gpu *gpu); +int a6xx_preempt_submitqueue_setup(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue); +void a6xx_preempt_submitqueue_close(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue); + +/* Return true if we are in a preempt state */ +static inline bool a6xx_in_preempt(struct a6xx_gpu *a6xx_gpu) +{ + int preempt_state = atomic_read(&a6xx_gpu->preempt_state); + + return !(preempt_state == PREEMPT_NONE || + preempt_state == PREEMPT_FINISH); +} + void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, bool suspended); unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c new file mode 100644 index 000000000000..0d402a3bcf5a --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2023 Collabora, Ltd. */ +/* Copyright (c) 2024 Valve Corporation */ + +#include "msm_gem.h" +#include "a6xx_gpu.h" +#include "a6xx_gmu.xml.h" +#include "msm_mmu.h" + +#define FENCE_STATUS_WRITEDROPPED0_MASK 0x1 +#define FENCE_STATUS_WRITEDROPPED1_MASK 0x2 + +/* + * Try to transition the preemption state from old to new. Return + * true on success or false if the original state wasn't 'old' + */ +static inline bool try_preempt_state(struct a6xx_gpu *a6xx_gpu, + enum a6xx_preempt_state old, enum a6xx_preempt_state new) +{ + enum a6xx_preempt_state cur = atomic_cmpxchg(&a6xx_gpu->preempt_state, + old, new); + + return (cur == old); +} + +/* + * Force the preemption state to the specified state. This is used in cases + * where the current state is known and won't change + */ +static inline void set_preempt_state(struct a6xx_gpu *gpu, + enum a6xx_preempt_state new) +{ + /* + * preempt_state may be read by other cores trying to trigger a + * preemption or in the interrupt handler so barriers are needed + * before... + */ + smp_mb__before_atomic(); + atomic_set(&gpu->preempt_state, new); + /* ... and after*/ + smp_mb__after_atomic(); +} + +/* Write the most recent wptr for the given ring into the hardware */ +static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + unsigned long flags; + uint32_t wptr, cur_wptr; + + if (!ring) + return; + + spin_lock_irqsave(&ring->preempt_lock, flags); + + if (ring->skip_inline_wptr) { + wptr = get_wptr(ring); + + gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); + + ring->skip_inline_wptr = false; + } + + spin_unlock_irqrestore(&ring->preempt_lock, flags); +} + +/* Return the highest priority ringbuffer with something in it */ +static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + + unsigned long flags; + int i; + + for (i = 0; i < gpu->nr_rings; i++) { + bool empty; + struct msm_ringbuffer *ring = gpu->rb[i]; + + spin_lock_irqsave(&ring->preempt_lock, flags); + empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); + if (!empty && ring == a6xx_gpu->cur_ring) + empty = ring->memptrs->fence == a6xx_gpu->last_seqno[i]; + spin_unlock_irqrestore(&ring->preempt_lock, flags); + + if (!empty) + return ring; + } + + return NULL; +} + +static void a6xx_preempt_timer(struct timer_list *t) +{ + struct a6xx_gpu *a6xx_gpu = from_timer(a6xx_gpu, t, preempt_timer); + struct msm_gpu *gpu = &a6xx_gpu->base.base; + struct drm_device *dev = gpu->dev; + + if (!try_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED, PREEMPT_FAULTED)) + return; + + dev_err(dev->dev, "%s: preemption timed out\n", gpu->name); + kthread_queue_work(gpu->worker, &gpu->recover_work); +} + +void a6xx_preempt_irq(struct msm_gpu *gpu) +{ + uint32_t status; + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct drm_device *dev = gpu->dev; + + if (!try_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED, PREEMPT_PENDING)) + return; + + /* Delete the preemption watchdog timer */ + del_timer(&a6xx_gpu->preempt_timer); + + /* + * The hardware should be setting the stop bit of CP_CONTEXT_SWITCH_CNTL + * to zero before firing the interrupt, but there is a non zero chance + * of a hardware condition or a software race that could set it again + * before we have a chance to finish. If that happens, log and go for + * recovery + */ + status = gpu_read(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL); + if (unlikely(status & 0x1)) { + DRM_DEV_ERROR(&gpu->pdev->dev, + "!!!!!!!!!!!!!!!! preemption faulted !!!!!!!!!!!!!! irq\n"); + set_preempt_state(a6xx_gpu, PREEMPT_FAULTED); + dev_err(dev->dev, "%s: Preemption failed to complete\n", + gpu->name); + kthread_queue_work(gpu->worker, &gpu->recover_work); + return; + } + + a6xx_gpu->cur_ring = a6xx_gpu->next_ring; + a6xx_gpu->next_ring = NULL; + + /* Make sure the write to cur_ring is posted before the change in state */ + wmb(); + + set_preempt_state(a6xx_gpu, PREEMPT_FINISH); + + update_wptr(gpu, a6xx_gpu->cur_ring); + + set_preempt_state(a6xx_gpu, PREEMPT_NONE); + + /* + * Retrigger preemption to avoid a deadlock that might occur when preemption + * is skipped due to it being already in flight when requested. + */ + a6xx_preempt_trigger(gpu); +} + +void a6xx_preempt_hw_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + int i; + + /* No preemption if we only have one ring */ + if (gpu->nr_rings == 1) + return; + + for (i = 0; i < gpu->nr_rings; i++) { + struct a6xx_preempt_record *record_ptr = + a6xx_gpu->preempt[i] + PREEMPT_OFFSET_PRIV_NON_SECURE; + record_ptr->wptr = 0; + record_ptr->rptr = 0; + record_ptr->rptr_addr = shadowptr(a6xx_gpu, gpu->rb[i]); + record_ptr->info = 0; + record_ptr->data = 0; + record_ptr->rbase = gpu->rb[i]->iova; + } + + /* Write a 0 to signal that we aren't switching pagetables */ + gpu_write64(gpu, REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, 0); + + /* Enable the GMEM save/restore feature for preemption */ + gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 0x1); + + /* Reset the preemption state */ + set_preempt_state(a6xx_gpu, PREEMPT_NONE); + + spin_lock_init(&a6xx_gpu->eval_lock); + + /* Always come up on rb 0 */ + a6xx_gpu->cur_ring = gpu->rb[0]; +} + +void a6xx_preempt_trigger(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + u64 preempt_offset_priv_secure; + unsigned long flags; + struct msm_ringbuffer *ring; + uint64_t user_ctx_iova; + unsigned int cntl; + + if (gpu->nr_rings == 1) + return; + + /* + * Lock to make sure another thread attempting preemption doesn't skip it + * while we are still evaluating the next ring. This makes sure the other + * thread does start preemption if we abort it and avoids a soft lock. + */ + spin_lock_irqsave(&a6xx_gpu->eval_lock, flags); + + /* + * Try to start preemption by moving from NONE to START. If + * unsuccessful, a preemption is already in flight + */ + if (!try_preempt_state(a6xx_gpu, PREEMPT_NONE, PREEMPT_START)) { + spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags); + return; + } + + cntl = (((a6xx_gpu->preempt_level << 6) & 0xC0) | + ((a6xx_gpu->skip_save_restore << 9) & 0x200) | + ((a6xx_gpu->uses_gmem << 8) & 0x100) | 0x1); + + /* Get the next ring to preempt to */ + ring = get_next_ring(gpu); + + /* + * If no ring is populated or the highest priority ring is the current + * one do nothing except to update the wptr to the latest and greatest + */ + if (!ring || (a6xx_gpu->cur_ring == ring)) { + set_preempt_state(a6xx_gpu, PREEMPT_FINISH); + update_wptr(gpu, a6xx_gpu->cur_ring); + set_preempt_state(a6xx_gpu, PREEMPT_NONE); + spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags); + return; + } + + spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags); + + spin_lock_irqsave(&ring->preempt_lock, flags); + + struct a7xx_cp_smmu_info *smmu_info_ptr = + a6xx_gpu->preempt[ring->id] + PREEMPT_OFFSET_SMMU_INFO; + struct a6xx_preempt_record *record_ptr = + a6xx_gpu->preempt[ring->id] + PREEMPT_OFFSET_PRIV_NON_SECURE; + u64 ttbr0 = ring->memptrs->ttbr0; + u32 context_idr = ring->memptrs->context_idr; + + smmu_info_ptr->ttbr0 = ttbr0; + smmu_info_ptr->context_idr = context_idr; + record_ptr->wptr = get_wptr(ring); + + /* + * The GPU will write the wptr we set above when we preempt. Reset + * skip_inline_wptr to make sure that we don't write WPTR to the same + * thing twice. It's still possible subsequent submissions will update + * wptr again, in which case they will set the flag to true. This has + * to be protected by the lock for setting the flag and updating wptr + * to be atomic. + */ + ring->skip_inline_wptr = false; + + spin_unlock_irqrestore(&ring->preempt_lock, flags); + + gpu_write64(gpu, + REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, + a6xx_gpu->preempt_iova[ring->id] + PREEMPT_OFFSET_SMMU_INFO); + + gpu_write64(gpu, + REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR, + a6xx_gpu->preempt_iova[ring->id] + PREEMPT_OFFSET_PRIV_NON_SECURE); + + preempt_offset_priv_secure = + PREEMPT_OFFSET_PRIV_SECURE(adreno_gpu->info->preempt_record_size); + gpu_write64(gpu, + REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR, + a6xx_gpu->preempt_iova[ring->id] + preempt_offset_priv_secure); + + /* + * Use the user context iova from the scratch memory that the CP may + * have written as part of the ring switch out. + */ + user_ctx_iova = *((uint64_t *)a6xx_gpu->scratch_ptr + ring->id); + + gpu_write64(gpu, + REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR, + user_ctx_iova); + + a6xx_gpu->next_ring = ring; + + /* Start a timer to catch a stuck preemption */ + mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); + + /* Set the preemption state to triggered */ + set_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED); + + /* Make sure any previous writes to WPTR are posted */ + gpu_read(gpu, REG_A6XX_CP_RB_WPTR); + + /* Make sure everything is written before hitting the button */ + wmb(); + + /* Trigger the preemption */ + gpu_write(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL, cntl); +} + +static int preempt_init_ring(struct a6xx_gpu *a6xx_gpu, + struct msm_ringbuffer *ring) +{ + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + struct msm_gpu *gpu = &adreno_gpu->base; + struct drm_gem_object *bo = NULL; + phys_addr_t ttbr; + u64 iova = 0; + void *ptr; + int asid; + + ptr = msm_gem_kernel_new(gpu->dev, + PREEMPT_SIZE(adreno_gpu->info->preempt_record_size), + MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova); + + memset(ptr, 0, PREEMPT_SIZE(adreno_gpu->info->preempt_record_size)); + + if (IS_ERR(ptr)) + return PTR_ERR(ptr); + + a6xx_gpu->preempt_bo[ring->id] = bo; + a6xx_gpu->preempt_iova[ring->id] = iova; + a6xx_gpu->preempt[ring->id] = ptr; + + struct a7xx_cp_smmu_info *smmu_info_ptr = ptr + PREEMPT_OFFSET_SMMU_INFO; + struct a6xx_preempt_record *record_ptr = ptr + PREEMPT_OFFSET_PRIV_NON_SECURE; + + msm_iommu_pagetable_params(gpu->aspace->mmu, &ttbr, &asid); + + smmu_info_ptr->magic = GEN7_CP_SMMU_INFO_MAGIC; + smmu_info_ptr->ttbr0 = ttbr; + smmu_info_ptr->asid = 0xdecafbad; + smmu_info_ptr->context_idr = 0; + + /* Set up the defaults on the preemption record */ + record_ptr->magic = A6XX_PREEMPT_RECORD_MAGIC; + record_ptr->info = 0; + record_ptr->data = 0; + record_ptr->rptr = 0; + record_ptr->wptr = 0; + record_ptr->cntl = MSM_GPU_RB_CNTL_DEFAULT; + record_ptr->rbase = ring->iova; + record_ptr->counter = 0; + record_ptr->bv_rptr_addr = rbmemptr(ring, bv_rptr); + + return 0; +} + +void a6xx_preempt_fini(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + int i; + + for (i = 0; i < gpu->nr_rings; i++) + msm_gem_kernel_put(a6xx_gpu->preempt_bo[i], gpu->aspace); +} + +void a6xx_preempt_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + int i; + + /* No preemption if we only have one ring */ + if (gpu->nr_rings <= 1) + return; + + for (i = 0; i < gpu->nr_rings; i++) { + if (preempt_init_ring(a6xx_gpu, gpu->rb[i])) + goto fail; + } + + /* TODO: make this configurable? */ + a6xx_gpu->preempt_level = 1; + a6xx_gpu->uses_gmem = 1; + a6xx_gpu->skip_save_restore = 1; + + a6xx_gpu->scratch_ptr = msm_gem_kernel_new(gpu->dev, + gpu->nr_rings * sizeof(uint64_t), MSM_BO_WC, + gpu->aspace, &a6xx_gpu->scratch_bo, + &a6xx_gpu->scratch_iova); + + if (IS_ERR(a6xx_gpu->scratch_ptr)) + goto fail; + + timer_setup(&a6xx_gpu->preempt_timer, a6xx_preempt_timer, 0); + + return; +fail: + /* + * On any failure our adventure is over. Clean up and + * set nr_rings to 1 to force preemption off + */ + a6xx_preempt_fini(gpu); + gpu->nr_rings = 1; + + return; +} + +void a6xx_preempt_submitqueue_close(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue) +{ + if (!queue->bo) + return; + + msm_gem_kernel_put(queue->bo, gpu->aspace); +} + +int a6xx_preempt_submitqueue_setup(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue) +{ + void *ptr; + + /* + * Create a per submitqueue buffer for the CP to save and restore user + * specific information such as the VPC streamout data. + */ + ptr = msm_gem_kernel_new(gpu->dev, A6XX_PREEMPT_USER_RECORD_SIZE, + MSM_BO_WC, gpu->aspace, &queue->bo, &queue->bo_iova); + + if (IS_ERR(ptr)) + return PTR_ERR(ptr); + + return 0; +} diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h index 40791b2ade46..7dde6a312511 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -36,6 +36,7 @@ struct msm_rbmemptrs { volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; volatile u64 ttbr0; + volatile u32 context_idr; }; struct msm_cp_state { @@ -100,6 +101,12 @@ struct msm_ringbuffer { * preemption. Can be aquired from irq context. */ spinlock_t preempt_lock; + + /* + * Whether we skipped writing wptr and it needs to be updated in the + * future when the ring becomes current. + */ + bool skip_inline_wptr; }; struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, From patchwork Thu Aug 15 18:26:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonino Maniscalco X-Patchwork-Id: 13765611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CA37C531DE for ; Fri, 16 Aug 2024 07:39:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B3C710E5B6; Fri, 16 Aug 2024 07:39:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="lGGa9c1t"; dkim-atps=neutral Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5AF3D10E4E8; Thu, 15 Aug 2024 18:27:45 +0000 (UTC) Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-a7aac70e30dso145060866b.1; Thu, 15 Aug 2024 11:27:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723746464; x=1724351264; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Tg0KctwqLqyFAo+4ao7jjZ1lcNMm+hl+ZjYOpPS5yMA=; b=lGGa9c1tqarEsy02g83EFjcu76Gy9SS/iHn6lrj9+3bK6eawu4dy/QbPr0q9o4YqVp M/GfrqrUDEwtfteo0ItE6+ZU2bS0+hL2fsy1c4pGKhWyMccnDI6P+1ushSil4wA0yBY0 7WSmqzEijan0piwnEbFfaRf6PZz1FmSQVMSYOBiURmFeic+CVvMVRB1QK/F0eWiClsge SunWAMD+0k49Cas7AbcVR7egOlwGcuDXdmeP12W7Iz49bCq58Ew9CCvBd4ekmCCGV45l 5N3nvn93HJ85JYP5Gvkm9vV884vN5np8T8Dxg5Z1zuosUpipVOah9BLvf9caCIZSVnWD Xoug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723746464; x=1724351264; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tg0KctwqLqyFAo+4ao7jjZ1lcNMm+hl+ZjYOpPS5yMA=; b=X9HNhOLg2K3tN8Wn3NZKLbN+Nza+pxMzbxItkGGZsRxEG2ov+2n68EjZGQLOviMs// EluHtrw+ktez5JRA5yyoZAVDC5LLsGkHtmlYumzYSEWUo5dASTKcc7NH3RS4EO6dVEtM dsa+9TqX4AJ+oeWCx0K1U0VnDVwEO+LZef1ue3qvtAf5VqtFhG8tOgXR04hNOpbjloVf 6zi1PYeV6ryZ+Gf2mTnPy76UtWfiojC/Z9sfhLa2lUZjIS35HFrYRvJMdqvqocjdSBZN iCtl5tVVlK9FcE8s2MltYbws7RtgLeOebtw2w9iLTlRpe0QiGJcRgq4pssPSxe53fvs1 RNgw== X-Forwarded-Encrypted: i=1; AJvYcCXjSd5Zij/vZ0+dG0WQNgw9b/3zQgDdu40JgVkwOfQjuq+uAo1v86LEuz53FCPNyyK0FqXj9t3o2D+eAsUn8eGSCH5s7plT66gtexZWssCOqyGatnnoOsAKhjtznJ07u0yEtFcteV/NL+wLiK/hWlia X-Gm-Message-State: AOJu0YxkX9WnmwZcIKZFsXqR4dmth4EAW5dFobzDkz2StyuOD4zU2x9d UBb8LWsfpz7+BLIz7vRGz0/jCzK1IGWtnaub3YhocuBNXuUw8x0v X-Google-Smtp-Source: AGHT+IFx/oFpTN7DjKnoRNWugjy0ykwyE+NteAI/sn+WwtRauwUVB8/OZuWOH38vkF2aAbfsnprrYw== X-Received: by 2002:a17:907:7fa5:b0:a80:aefa:14d3 with SMTP id a640c23a62f3a-a8392a4128amr36267966b.63.1723746463495; Thu, 15 Aug 2024 11:27:43 -0700 (PDT) Received: from [192.168.1.13] (host-79-35-172-29.retail.telecomitalia.it. [79.35.172.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383947187sm133814366b.166.2024.08.15.11.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 11:27:43 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 15 Aug 2024 20:26:15 +0200 Subject: [PATCH 5/7] drm/msm/A6xx: Add traces for preemption MIME-Version: 1.0 Message-Id: <20240815-preemption-a750-t-v1-5-7bda26c34037@gmail.com> References: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> In-Reply-To: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Antonino Maniscalco X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723746454; l=2516; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=DLafHpP62zkOHtSD80kKPRoUh5A+Qyukl3VsQmH39Qc=; b=icdUKlpDMF2mVoh3JZqkgkjybL+RiUKZ0urWvjJ6sWmpBaEiMn7wHC4EkTZSN3u+1onK3gsCs +k8jqD6zTGCB/NV3x/BaC3XEyt+3NzIBzDusevWF8bGcHALiM3hTXlS X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= X-Mailman-Approved-At: Fri, 16 Aug 2024 07:39:16 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add trace points corresponding to preemption being triggered and being completed for latency measurement purposes. Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 7 +++++++ drivers/gpu/drm/msm/msm_gpu_trace.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c index 0d402a3bcf5a..2606835f3c6d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c @@ -7,6 +7,7 @@ #include "a6xx_gpu.h" #include "a6xx_gmu.xml.h" #include "msm_mmu.h" +#include "msm_gpu_trace.h" #define FENCE_STATUS_WRITEDROPPED0_MASK 0x1 #define FENCE_STATUS_WRITEDROPPED1_MASK 0x2 @@ -146,6 +147,8 @@ void a6xx_preempt_irq(struct msm_gpu *gpu) set_preempt_state(a6xx_gpu, PREEMPT_NONE); + trace_msm_gpu_preemption_irq(a6xx_gpu->cur_ring->id); + /* * Retrigger preemption to avoid a deadlock that might occur when preemption * is skipped due to it being already in flight when requested. @@ -262,6 +265,10 @@ void a6xx_preempt_trigger(struct msm_gpu *gpu) */ ring->skip_inline_wptr = false; + trace_msm_gpu_preemption_trigger( + a6xx_gpu->cur_ring ? a6xx_gpu->cur_ring->id : -1, + ring ? ring->id : -1); + spin_unlock_irqrestore(&ring->preempt_lock, flags); gpu_write64(gpu, diff --git a/drivers/gpu/drm/msm/msm_gpu_trace.h b/drivers/gpu/drm/msm/msm_gpu_trace.h index ac40d857bc45..7f863282db0d 100644 --- a/drivers/gpu/drm/msm/msm_gpu_trace.h +++ b/drivers/gpu/drm/msm/msm_gpu_trace.h @@ -177,6 +177,34 @@ TRACE_EVENT(msm_gpu_resume, TP_printk("%u", __entry->dummy) ); +TRACE_EVENT(msm_gpu_preemption_trigger, + TP_PROTO(int ring_id_from, int ring_id_to), + TP_ARGS(ring_id_from, ring_id_to), + TP_STRUCT__entry( + __field(int, ring_id_from) + __field(int, ring_id_to) + ), + TP_fast_assign( + __entry->ring_id_from = ring_id_from; + __entry->ring_id_to = ring_id_to; + ), + TP_printk("preempting %u -> %u", + __entry->ring_id_from, + __entry->ring_id_to) +); + +TRACE_EVENT(msm_gpu_preemption_irq, + TP_PROTO(u32 ring_id), + TP_ARGS(ring_id), + TP_STRUCT__entry( + __field(u32, ring_id) + ), + TP_fast_assign( + __entry->ring_id = ring_id; + ), + TP_printk("preempted to %u", __entry->ring_id) +); + #endif #undef TRACE_INCLUDE_PATH From patchwork Thu Aug 15 18:26:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonino Maniscalco X-Patchwork-Id: 13765608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52688C531DC for ; Fri, 16 Aug 2024 07:39:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7BB7C10E5B2; Fri, 16 Aug 2024 07:39:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Y34mK5tS"; dkim-atps=neutral Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) by gabe.freedesktop.org (Postfix) with ESMTPS id D85F610E4E8; Thu, 15 Aug 2024 18:27:46 +0000 (UTC) Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-a7aac70e30dso145063166b.1; Thu, 15 Aug 2024 11:27:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723746465; x=1724351265; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GYNQ3Kd9tk4rueRVocGNtRpvnUgsUyrxTXFbooCVABo=; b=Y34mK5tS7pKEpi8Jg77I1CXJfFTQKpW97YPUl0TJYvaUbeU6E1IvSAZobzafYgPNlU swQs50JqQBRVcgivuXTxFXyYgYnkhFvyFSkCKojMgWAlT7Jsyh5aMuMqk1fuiYGxZxHB nQ0Rz4WS7va4aio4Cdf2d7f7ibH8ERZFbRxefRNUWICIVMlW55/U6BJNXlYBnNd7gRK9 M26XzDvgaIgqM7yYHxttUxWRbv1RxVqq+BKnb67tn7f08ARG9QFdIj6Ih9EFXdwWXS/A Rv8GtOjit5OVf2T7B1ZKo0smCGTRX7Ad8DRHoYQdjBehoueDdNHFw2jUTgYMPbARZv92 lW9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723746465; x=1724351265; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GYNQ3Kd9tk4rueRVocGNtRpvnUgsUyrxTXFbooCVABo=; b=D+HxaMXCEj8zR1y+yJNLOE62uSoK4A06CvZRkU+Q9DB1QVrLFp3s+/lzrgyLilx6bK j9iTzh+4ddXBakJHi5QHVP6f9VV58HIExW7xjJN8IbWmFzpQRSGFd/7eqHG9F2aJ6b8d GXx2mbQjNA01VtcgJ8NgYzuS1vp8lMDiCSAQiePuwkzLKh8Pez7GfjRw+tvwQQjdkxb6 AKjpQaaaNvyS+DoCXeq2hoPF/ffj5QqmH3Q+WoCejk8ctrlMS+cD7ZOLPpQL9sIj8RDZ ufFCCh+W+ANl5FVllSnOu81f6HUMxthAJmrhe4qGYnD6JVd3Igk00y5eE4m4RTYIq61O ftZw== X-Forwarded-Encrypted: i=1; AJvYcCWtBr/QI9Iz7mJ+w8yrRJ8gIkDMIuYizEEKp9qx2M6wun5nnmwNt/z0qjcBhfiikhr89xUSens0khXnOPcN3p4ZyyHV/CJM4/xpF1aALmPw5zTpqZPmrSrcUgtmI91Y0YP9oJ6MIwKYTmqvrh6emRLg X-Gm-Message-State: AOJu0Yx0G67G6qtbpYLtQ5/Lh8Jpho6S9D79NFmH27bfHMClpcESKg6I JWRoFSpH216t+QPKA6k7jR0EZJR3c8+fcc1HiL7/jzJD7yLvIT/9 X-Google-Smtp-Source: AGHT+IG7eGtE09/Qx++WFHjUPm+osUtSJegCIrquQ4d7QvqeC3N59wMKxmmm6RyPv1HQ4dTZwDJezg== X-Received: by 2002:a17:907:7b8c:b0:a75:2495:a6a3 with SMTP id a640c23a62f3a-a8392a411d4mr27182466b.67.1723746465046; Thu, 15 Aug 2024 11:27:45 -0700 (PDT) Received: from [192.168.1.13] (host-79-35-172-29.retail.telecomitalia.it. [79.35.172.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383947187sm133814366b.166.2024.08.15.11.27.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 11:27:44 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 15 Aug 2024 20:26:16 +0200 Subject: [PATCH 6/7] drm/msm/A6XX: Add a flag to allow preemption to submitqueue_create MIME-Version: 1.0 Message-Id: <20240815-preemption-a750-t-v1-6-7bda26c34037@gmail.com> References: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> In-Reply-To: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Antonino Maniscalco X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723746454; l=2101; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=GF/BCimeWie0a1inww3pyOMeudVhMYIVzh+LjcDJs6s=; b=7HXl9WtNfMMnNqPPtxHK4bSQyelfqNTETs83haTMurX8wKTu4RJi0olnliHSZG+aSrcc1BFA4 Fb6DGs0HiwfDpe+qhFQtvcM0V7GXvWxo8k4YHDpUSlNkevPyRyU2K7P X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= X-Mailman-Approved-At: Fri, 16 Aug 2024 07:39:16 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some userspace changes are necessary so add a flag for userspace to advertise support for preemption. Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 ++++++++---- include/uapi/drm/msm_drm.h | 5 ++++- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 1a90db5759b8..86357016db8d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -453,8 +453,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) OUT_PKT7(ring, CP_SET_MARKER, 1); OUT_RING(ring, 0x101); /* IFPC disable */ - OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, 0x00d); /* IB1LIST start */ + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { + OUT_PKT7(ring, CP_SET_MARKER, 1); + OUT_RING(ring, 0x00d); /* IB1LIST start */ + } /* Submit the commands */ for (i = 0; i < submit->nr_cmds; i++) { @@ -485,8 +487,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) update_shadow_rptr(gpu, ring); } - OUT_PKT7(ring, CP_SET_MARKER, 1); - OUT_RING(ring, 0x00e); /* IB1LIST end */ + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { + OUT_PKT7(ring, CP_SET_MARKER, 1); + OUT_RING(ring, 0x00e); /* IB1LIST end */ + } get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), rbmemptr_stats(ring, index, cpcycles_end)); diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 3fca72f73861..f37858db34e6 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -345,7 +345,10 @@ struct drm_msm_gem_madvise { * backwards compatibility as a "default" submitqueue */ -#define MSM_SUBMITQUEUE_FLAGS (0) +#define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001 +#define MSM_SUBMITQUEUE_FLAGS ( \ + MSM_SUBMITQUEUE_ALLOW_PREEMPT | \ + 0) /* * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1, From patchwork Thu Aug 15 18:26:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonino Maniscalco X-Patchwork-Id: 13765612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96663C531DF for ; Fri, 16 Aug 2024 07:39:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 814C310E5B5; Fri, 16 Aug 2024 07:39:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FfIUkfIl"; dkim-atps=neutral Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3B12F10E4E9; Thu, 15 Aug 2024 18:27:48 +0000 (UTC) Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-a7d26c2297eso150262666b.2; Thu, 15 Aug 2024 11:27:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723746466; x=1724351266; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VIguaDw6K3AjrU3ab+I5U80CnBvjwafBtu7HcwHufJ0=; b=FfIUkfIlYGGI+Khy71v+Ym9vzskU0PmYKkZruJ78BOa8wk3D9h5sPXJl6xWDk/+YLL W2NarWABAbCCukEUGSh95doP0U1w8BWvrtwmBYowimSTIo14aQ2ZxhDVHvW3r3gIMQIL AqCz5tngzppQrsZ92jPxvD0aUKeEaIg0Zk6ixes/gpzf+nCclC+uf2omti0m3Lz4B7Ya +AF8fP3Mljvch6H8LkuDOak2hG7i+AikpNIEpJFRi/TaYeoyxGeUtd78VyL9mx4Td/0t 5bgXsylN9w7n54aLrFPLhSkxveJaVVKKZF8c5FwyDL1SplJq5YpmwK7NVobhnRwsL+wE o8Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723746466; x=1724351266; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VIguaDw6K3AjrU3ab+I5U80CnBvjwafBtu7HcwHufJ0=; b=CaaNFhHOQxU5w1ync8VrNXQhkz/yuvTJt4fj8ka5iq5sfkjNvA5DFZPpoJ92YffRk2 GgMUmYOjH3Iublkv7FpZThRrvqfV2zeM8gfh8rHR0ZIWjojcW+dwwPsm5aeIjE+/eg5k l1qh5AmgJ8eeNct9NpaPEfBjWh03WUeSaRsgdVvRm9oqqhSinOAX69UACfUH5/fb9duX A7ZiaGxqhOBmhjhvD21RxVPrQ7OVvd6tWf9SI2TGu8FpJkgLPr+R2+JypV3vcu1GJ6hB MWIIBGvtH96vT+JQXrUrxEySBV/rN6pClj+YWoGiievzHfSgmAAtCuBbvPQGncptMzRb RKyw== X-Forwarded-Encrypted: i=1; AJvYcCWy8cZzyLMp6h/M2T2McugmlaGJHz5n8TTsgrp+XydT+xrPsXoXYnYNEmQ8WIP3dGntqLA4MkpzNXWIiV6p5Se4iM4vsCnKGh5JMXfMwjHVaix5lXHYKpMaxjq8fb431fkbjesbnGo/dbNKpxGT96E4 X-Gm-Message-State: AOJu0Yzbz3qLFBOvM4jbDC+bOgP8pc6pMTi2jWJbGwiUFrCqnnohfMBr EIUE8l7lvzdn25CXl3MOrp+ZT4zjWf7kcWsEJkEHS4Dgzh56XIfv X-Google-Smtp-Source: AGHT+IGwoWk5WigfEZ1u01jT4wrcamE5rN3NcH4p3UsMjt+Xgy/YrHe3X+lScoeKehIQ0Q1UjZVh6Q== X-Received: by 2002:a17:907:6d2a:b0:a77:d773:54ec with SMTP id a640c23a62f3a-a83928a35abmr32107066b.8.1723746466408; Thu, 15 Aug 2024 11:27:46 -0700 (PDT) Received: from [192.168.1.13] (host-79-35-172-29.retail.telecomitalia.it. [79.35.172.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383947187sm133814366b.166.2024.08.15.11.27.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 11:27:46 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 15 Aug 2024 20:26:17 +0200 Subject: [PATCH 7/7] drm/msm/A6xx: Enable preemption for A7xx targets MIME-Version: 1.0 Message-Id: <20240815-preemption-a750-t-v1-7-7bda26c34037@gmail.com> References: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> In-Reply-To: <20240815-preemption-a750-t-v1-0-7bda26c34037@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Antonino Maniscalco X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723746454; l=810; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=F0OWbgiTE8fXGsmJh+q0opfj9AJfdT04FvOWvOdcCSQ=; b=BFztRTD/A4FOBfCMtIL+mnc65TjK9/VuvpVb9pb+7bPx7c+q5F8Yozv2Fh++miUCLueSfzHDl jiVeUjL6PywDxlHahr7xKLG9M5lR4H+maEVZooy3X2FuQINLuCThaxb X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= X-Mailman-Approved-At: Fri, 16 Aug 2024 07:39:16 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Initialize with 4 rings to enable preemption. Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 86357016db8d..dfcbe08f2161 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2598,7 +2598,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) } if (is_a7xx) - ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); else if (adreno_has_gmu_wrapper(adreno_gpu)) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); else