From patchwork Fri Aug 16 11:10:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13765979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6FE6C531DE for ; Fri, 16 Aug 2024 11:11:00 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.778530.1188592 (Exim 4.92) (envelope-from ) id 1seur4-0006bR-Vw; Fri, 16 Aug 2024 11:10:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 778530.1188592; Fri, 16 Aug 2024 11:10:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seur4-0006bK-TP; Fri, 16 Aug 2024 11:10:50 +0000 Received: by outflank-mailman (input) for mailman id 778530; Fri, 16 Aug 2024 11:10:49 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seur3-0006aw-KN for xen-devel@lists.xenproject.org; Fri, 16 Aug 2024 11:10:49 +0000 Received: from pb-smtp21.pobox.com (pb-smtp21.pobox.com [173.228.157.53]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2f9b20fb-5bc0-11ef-8776-851b0ebba9a2; Fri, 16 Aug 2024 13:10:47 +0200 (CEST) Received: from pb-smtp21.pobox.com (unknown [127.0.0.1]) by pb-smtp21.pobox.com (Postfix) with ESMTP id 10C581AD20; Fri, 16 Aug 2024 07:10:45 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp21.sea.icgroup.com (unknown [127.0.0.1]) by pb-smtp21.pobox.com (Postfix) with ESMTP id 092211AD1F; Fri, 16 Aug 2024 07:10:45 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp21.pobox.com (Postfix) with ESMTPSA id 9F7F61AD1E; Fri, 16 Aug 2024 07:10:41 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2f9b20fb-5bc0-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=jlgPaY/GIjAxFDl/srIa2LTto 2punK5EfkiByCImD2s=; b=qW7qseu1JtMjy76Gb8GMh6hfOPq6GzFCzEpW1kdSx OmnuYkkYYOYtyy0Yox8ubVan40i537yAmDQrcgDup06oRL37yaXVxcdtyED1PacF tB/O3HUSmTxlHP5W9zMDGDihZu8wF3hBZOTdWp3MCkWomw4b9b9rJZUtvjU9txbk XE= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Alejandro Vallejo , Jan Beulich Subject: [XEN PATCH v2 1/5] x86/Kconfig: introduce CENTAUR, HYGON & SHANGHAI config options Date: Fri, 16 Aug 2024 14:10:37 +0300 Message-Id: <2a217c9602e92f92050cb4894bb9a42ee99a84ea.1723806405.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 2CE33EEA-5BC0-11EF-A193-E92ED1CD468F-90055647!pb-smtp21.pobox.com These options aim to represent what's currently supported by Xen, and later to allow tuning for specific platform(s) only. HYGON and SHANGHAI options depend on AMD and INTEL as there're build dependencies on support code for AMD and Intel CPUs respectively. Signed-off-by: Sergiy Kibrik CC: Alejandro Vallejo CC: Jan Beulich Reviewed-by: Alejandro Vallejo --- xen/arch/x86/Kconfig.cpu | 29 +++++++++++++++++++++++++++++ xen/arch/x86/cpu/Makefile | 6 +++--- xen/arch/x86/cpu/common.c | 6 ++++++ 3 files changed, 38 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/Kconfig.cpu b/xen/arch/x86/Kconfig.cpu index 5fb18db1aa..ac8f41d464 100644 --- a/xen/arch/x86/Kconfig.cpu +++ b/xen/arch/x86/Kconfig.cpu @@ -10,6 +10,25 @@ config AMD May be turned off in builds targetting other vendors. Otherwise, must be enabled for Xen to work suitably on AMD platforms. +config CENTAUR + bool "Support Centaur CPUs" + default y + help + Detection, tunings and quirks for VIA platforms. + + May be turned off in builds targeting other vendors. Otherwise, must + be enabled for Xen to work suitably on VIA platforms. + +config HYGON + bool "Support Hygon CPUs" + depends on AMD + default y + help + Detection, tunings and quirks for Hygon platforms. + + May be turned off in builds targeting other vendors. Otherwise, must + be enabled for Xen to work suitably on Hygon platforms. + config INTEL bool "Support Intel CPUs" default y @@ -19,4 +38,14 @@ config INTEL May be turned off in builds targetting other vendors. Otherwise, must be enabled for Xen to work suitably on Intel platforms. +config SHANGHAI + bool "Support Shanghai CPUs" + depends on INTEL + default y + help + Detection, tunings and quirks for Zhaoxin platforms. + + May be turned off in builds targeting other vendors. Otherwise, must + be enabled for Xen to work suitably on Zhaoxin platforms. + endmenu diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index eafce5f204..80739d0256 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -3,13 +3,13 @@ obj-y += microcode/ obj-y += mtrr/ obj-y += amd.o -obj-y += centaur.o +obj-$(CONFIG_CENTAUR) += centaur.o obj-y += common.o -obj-y += hygon.o +obj-$(CONFIG_HYGON) += hygon.o obj-y += intel.o obj-y += intel_cacheinfo.o obj-y += mwait-idle.o -obj-y += shanghai.o +obj-$(CONFIG_SHANGHAI) += shanghai.o obj-y += vpmu.o obj-$(CONFIG_AMD) += vpmu_amd.o obj-$(CONFIG_INTEL) += vpmu_intel.o diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index ff4cd22897..dcc2753212 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -339,9 +339,15 @@ void __init early_cpu_init(bool verbose) case X86_VENDOR_INTEL: intel_unlock_cpuid_leaves(c); actual_cpu = intel_cpu_dev; break; case X86_VENDOR_AMD: actual_cpu = amd_cpu_dev; break; +#ifdef CONFIG_CENTAUR case X86_VENDOR_CENTAUR: actual_cpu = centaur_cpu_dev; break; +#endif +#ifdef CONFIG_SHANGHAI case X86_VENDOR_SHANGHAI: actual_cpu = shanghai_cpu_dev; break; +#endif +#ifdef CONFIG_HYGON case X86_VENDOR_HYGON: actual_cpu = hygon_cpu_dev; break; +#endif default: actual_cpu = default_cpu; if (!verbose) From patchwork Fri Aug 16 11:12:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13766012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB49EC531DE for ; Fri, 16 Aug 2024 11:13:05 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.778547.1188602 (Exim 4.92) (envelope-from ) id 1seut7-0007FT-AB; Fri, 16 Aug 2024 11:12:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 778547.1188602; Fri, 16 Aug 2024 11:12:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seut7-0007FM-74; Fri, 16 Aug 2024 11:12:57 +0000 Received: by outflank-mailman (input) for mailman id 778547; Fri, 16 Aug 2024 11:12:55 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seut5-0007FE-Ri for xen-devel@lists.xenproject.org; Fri, 16 Aug 2024 11:12:55 +0000 Received: from pb-smtp21.pobox.com (pb-smtp21.pobox.com [173.228.157.53]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7b37e106-5bc0-11ef-8776-851b0ebba9a2; Fri, 16 Aug 2024 13:12:54 +0200 (CEST) Received: from pb-smtp21.pobox.com (unknown [127.0.0.1]) by pb-smtp21.pobox.com (Postfix) with ESMTP id B5CB31AE7F; Fri, 16 Aug 2024 07:12:52 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp21.sea.icgroup.com (unknown [127.0.0.1]) by pb-smtp21.pobox.com (Postfix) with ESMTP id AECE81AE7E; Fri, 16 Aug 2024 07:12:52 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp21.pobox.com (Postfix) with ESMTPSA id 2D6301AE7D; Fri, 16 Aug 2024 07:12:48 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7b37e106-5bc0-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=jjmqvyUqyJfIGrS4f+TrQFvun Q78NoLP29D4JepiAmo=; b=shUH7MPAYLzOTjQiHky6yVpIBMv11b4GqhQh0zHYl 44mLjLb75TqVpnPW7FxaXxLgVA1AkvkS49UUik4syQsmi8zea7hdCwTMT3zXvul2 CddQspko9iXte9cxRCPhsrlt9ijiTLPQdWvNz9Ksxnb+6Vu+JD32crOMoNc0fgs/ Ng= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Jan Beulich Subject: [XEN PATCH v2 2/5] x86/amd: configurable handling of AMD-specific MSRs access Date: Fri, 16 Aug 2024 14:12:44 +0300 Message-Id: <917d2186db56c6f4c820f6b9e26b29fbe93301d6.1723806405.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 784DA14A-5BC0-11EF-81D0-E92ED1CD468F-90055647!pb-smtp21.pobox.com Do not compile handlers of guest access to AMD-specific MSRs when CONFIG_AMD=n. Signed-off-by: Sergiy Kibrik CC: Jan Beulich --- xen/arch/x86/msr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 289cf10b78..4567de7fc8 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -219,6 +219,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) *val = msrs->tsc_aux; break; +#ifdef CONFIG_AMD case MSR_K8_SYSCFG: case MSR_K8_TOP_MEM1: case MSR_K8_TOP_MEM2: @@ -281,6 +282,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) ? 0 : (msr - MSR_AMD64_DR1_ADDRESS_MASK + 1), ARRAY_SIZE(msrs->dr_mask))]; break; +#endif /* CONFIG_AMD */ /* * TODO: Implement when we have better topology representation. @@ -552,6 +554,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) wrmsr_tsc_aux(val); break; +#ifdef CONFIG_AMD case MSR_VIRT_SPEC_CTRL: if ( !cp->extd.virt_ssbd ) goto gp_fault; @@ -598,6 +601,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) if ( v == curr && (curr->arch.dr7 & DR7_ACTIVE_MASK) ) wrmsrl(msr, val); break; +#endif /* CONFIG_AMD */ default: return X86EMUL_UNHANDLEABLE; From patchwork Fri Aug 16 11:14:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13766013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7A6AC3DA4A for ; Fri, 16 Aug 2024 11:15:20 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.778555.1188611 (Exim 4.92) (envelope-from ) id 1seuvF-0007s2-P3; Fri, 16 Aug 2024 11:15:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 778555.1188611; Fri, 16 Aug 2024 11:15:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seuvF-0007rv-MI; Fri, 16 Aug 2024 11:15:09 +0000 Received: by outflank-mailman (input) for mailman id 778555; Fri, 16 Aug 2024 11:15:08 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seuvE-0007rp-Bj for xen-devel@lists.xenproject.org; Fri, 16 Aug 2024 11:15:08 +0000 Received: from pb-smtp21.pobox.com (pb-smtp21.pobox.com [173.228.157.53]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id ca007d53-5bc0-11ef-8776-851b0ebba9a2; Fri, 16 Aug 2024 13:15:06 +0200 (CEST) Received: from pb-smtp21.pobox.com (unknown [127.0.0.1]) by pb-smtp21.pobox.com (Postfix) with ESMTP id 4A9DA1AE93; Fri, 16 Aug 2024 07:15:04 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp21.sea.icgroup.com (unknown [127.0.0.1]) by pb-smtp21.pobox.com (Postfix) with ESMTP id 320161AE92; Fri, 16 Aug 2024 07:15:04 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp21.pobox.com (Postfix) with ESMTPSA id 85F981AE8E; Fri, 16 Aug 2024 07:15:00 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ca007d53-5bc0-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=SImZJDa/oxwFzFRYOBx72eonr TZPtSmDNOl28smcrN4=; b=W5GAoZqVvANw8VMDmkR8LKn9oLIJKvQ04wCU9ocs6 aP3eA5UnByYIn0h5IeATBNHlr510pSfxazBe/tnaFYbyXwWhwNvp7pVOnhqvxcaR ZlIve0cLYYu1UzZVofENQElpHkSXjnk58nDtshhERb/lsK9STNb4P1W8jS4u0FHv 5c= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Jan Beulich Subject: [XEN PATCH v2 3/5] x86/spec-ctrl: configurable Intlel/AMD-specific calculations Date: Fri, 16 Aug 2024 14:14:52 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: C7331240-5BC0-11EF-94DE-E92ED1CD468F-90055647!pb-smtp21.pobox.com Put platforms-specific code under #ifdef CONFIG_{AMD,INTEL} so that when corresponding CPU support is disabled by configuration less dead code will end up in the build. This includes re-ordering of calls to ibpb_calculations() & div_calculations(), but since they don't access common variables or feature bits it should be safe to do. Signed-off-by: Sergiy Kibrik CC: Jan Beulich --- xen/arch/x86/spec_ctrl.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 75a4177a75..ba6c3e80d2 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -1012,6 +1012,7 @@ static bool __init should_use_eager_fpu(void) } } +#ifdef CONFIG_AMD /* * https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf */ @@ -1110,6 +1111,7 @@ static void __init div_calculations(bool hw_smt_enabled) "enabled. Please assess your configuration and choose an\n" "explicit 'smt=' setting. See XSA-439.\n"); } +#endif /* CONFIG_AMD */ static void __init ibpb_calculations(void) { @@ -1319,6 +1321,7 @@ static __init void l1tf_calculations(void) : (3UL << (paddr_bits - 2)))); } +#ifdef CONFIG_INTEL /* Calculate whether this CPU is vulnerable to MDS. */ static __init void mds_calculations(void) { @@ -1730,6 +1733,8 @@ static void __init bhi_calculations(void) } } +#endif /* CONFIG_INTEL */ + void spec_ctrl_init_domain(struct domain *d) { bool pv = is_pv_domain(d); @@ -2025,11 +2030,13 @@ void __init init_speculation_mitigations(void) default_scf |= SCF_ist_rsb; } +#ifdef CONFIG_AMD srso_calculations(hw_smt_enabled); - ibpb_calculations(); - div_calculations(hw_smt_enabled); +#endif + + ibpb_calculations(); /* Check whether Eager FPU should be enabled by default. */ if ( opt_eager_fpu == -1 ) @@ -2136,9 +2143,10 @@ void __init init_speculation_mitigations(void) * - March 2023, for RFDS. Enumerate RFDS_CLEAR to mean that VERW now * scrubs non-architectural entries from certain register files. */ +#ifdef CONFIG_INTEL mds_calculations(); rfds_calculations(); - +#endif /* * Parts which enumerate FB_CLEAR are those with now-updated microcode * which weren't susceptible to the original MFBDS (and therefore didn't @@ -2255,7 +2263,6 @@ void __init init_speculation_mitigations(void) opt_tsx = 0; tsx_init(); } -#endif /* * On some SRBDS-affected hardware, it may be safe to relax srb-lock by @@ -2286,6 +2293,8 @@ void __init init_speculation_mitigations(void) bhi_calculations(); +#endif /* CONFIG_INTEL */ + print_details(thunk); /* From patchwork Fri Aug 16 11:17:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13766016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA819C3DA4A for ; Fri, 16 Aug 2024 11:17:23 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.778578.1188623 (Exim 4.92) (envelope-from ) id 1seuxF-0001ES-69; Fri, 16 Aug 2024 11:17:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 778578.1188623; Fri, 16 Aug 2024 11:17:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seuxF-0001EL-1p; Fri, 16 Aug 2024 11:17:13 +0000 Received: by outflank-mailman (input) for mailman id 778578; Fri, 16 Aug 2024 11:17:11 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1seuxD-0000sM-Rl for xen-devel@lists.xenproject.org; Fri, 16 Aug 2024 11:17:11 +0000 Received: from pb-smtp1.pobox.com (pb-smtp1.pobox.com [64.147.108.70]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 12eb44ea-5bc1-11ef-a505-bb4a2ccca743; Fri, 16 Aug 2024 13:17:10 +0200 (CEST) Received: from pb-smtp1.pobox.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 47DFF27A4F; Fri, 16 Aug 2024 07:17:07 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp1.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 2F8E927A4E; Fri, 16 Aug 2024 07:17:07 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp1.pobox.com (Postfix) with ESMTPSA id 4F14E27A4D; Fri, 16 Aug 2024 07:17:06 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 12eb44ea-5bc1-11ef-a505-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=0sUZEfq34Jce26Uo7t070vVwu CBDfAUvgjTre/OP4Yc=; b=IVOGs9bG+DjAJ2zbS6AfIdx+jBRUgAfr9RkT6v8dJ 6s9qqB8rE/GWW5x0V7M/k/tuQjc1rzM8vxEqeS95MHPRWs4/tNWrRNMN2dW8JvM/ V58MiOOqUzDkianP/8rqDT/9A4BBYzZfHSyrIzmn6vCKmmeEEtyeyITXVOh3+I0i Rg= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Alejandro Vallejo , Jan Beulich Subject: [XEN PATCH v2 4/5] x86/intel: optional build of intel.c Date: Fri, 16 Aug 2024 14:17:03 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 122BD1E2-5BC1-11EF-B11F-2BAEEB2EC81B-90055647!pb-smtp1.pobox.com With specific config option INTEL in place and most of the code that depends on intel.c now can be optionally enabled/disabled it's now possible to put the whole intel.c under INTEL option as well. This will allow for a Xen build without Intel CPU support. Signed-off-by: Sergiy Kibrik CC: Alejandro Vallejo CC: Jan Beulich Acked-by: Jan Beulich --- changes in v2: - drop set_in_mcu_opt_ctrl() stub --- xen/arch/x86/cpu/Makefile | 4 ++-- xen/arch/x86/cpu/common.c | 2 ++ xen/arch/x86/include/asm/processor.h | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index 80739d0256..eeb9ebe562 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -6,8 +6,8 @@ obj-y += amd.o obj-$(CONFIG_CENTAUR) += centaur.o obj-y += common.o obj-$(CONFIG_HYGON) += hygon.o -obj-y += intel.o -obj-y += intel_cacheinfo.o +obj-$(CONFIG_INTEL) += intel.o +obj-$(CONFIG_INTEL) += intel_cacheinfo.o obj-y += mwait-idle.o obj-$(CONFIG_SHANGHAI) += shanghai.o obj-y += vpmu.o diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index dcc2753212..580b01d6d5 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -336,8 +336,10 @@ void __init early_cpu_init(bool verbose) c->x86_vendor = x86_cpuid_lookup_vendor(ebx, ecx, edx); switch (c->x86_vendor) { +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: intel_unlock_cpuid_leaves(c); actual_cpu = intel_cpu_dev; break; +#endif case X86_VENDOR_AMD: actual_cpu = amd_cpu_dev; break; #ifdef CONFIG_CENTAUR case X86_VENDOR_CENTAUR: actual_cpu = centaur_cpu_dev; break; diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/asm/processor.h index 66463f6a6d..a52f8b0a83 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -507,13 +507,14 @@ static inline uint8_t get_cpu_family(uint32_t raw, uint8_t *model, extern int8_t opt_tsx; extern bool rtm_disabled; void tsx_init(void); +void update_mcu_opt_ctrl(void); #else #define opt_tsx 0 /* explicitly indicate TSX is off */ #define rtm_disabled false /* RTM was not force-disabled */ static inline void tsx_init(void) {} +static inline void update_mcu_opt_ctrl(void) {} #endif -void update_mcu_opt_ctrl(void); void set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val); enum ap_boot_method { From patchwork Fri Aug 16 11:19:07 2024 Content-Type: text/plain; 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Fri, 16 Aug 2024 07:19:09 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5c64582a-5bc1-11ef-a505-bb4a2ccca743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=PjnMO2z53AIZ819k6PFRrFgWX 6KC8ZTHVSlS1GFYRHg=; b=RJz3lELjHQkcdAJIiw2+DyP48jnGSsN1JYu3eQHWc jtU59lDyc4nd30jCzlyT8o6C/gaDivwYg3gGIPjKH7Jl4EXigYR9aB8MVrLNZeru 9RC6cNsNRIRQWU38oFmQM09dQ9eyiLCF63HfhlnHNs0AfX+PRu+oOyt32eXLluIA aM= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Jan Beulich Subject: [XEN PATCH v2 5/5] x86/amd: optional build of amd.c Date: Fri, 16 Aug 2024 14:19:07 +0300 Message-Id: <3c641433fa7cfe1f7fdc918ab32086835a2e13eb.1723806405.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 5BA4DA1C-5BC1-11EF-AEDC-9B0F950A682E-90055647!pb-smtp2.pobox.com Similar to making Intel CPU support optional -- as we've got CONFIG_AMD option now, we can put arch/x86/cpu/amd.c under it and make it possible to build Xen without AMD CPU support. One possible use case is to dispose of dead code in Intel-only systems. Signed-off-by: Sergiy Kibrik CC: Jan Beulich --- changes in v2: - drop routines-stubs in amd.h, handle call sites instead - cpu_has_amd_erratum() return int instead of bool --- xen/arch/x86/cpu/Makefile | 2 +- xen/arch/x86/cpu/common.c | 4 +++- xen/arch/x86/hvm/svm/svm.c | 6 ++++-- xen/arch/x86/include/asm/amd.h | 20 ++++++++++++++++++-- xen/arch/x86/spec_ctrl.c | 2 ++ 5 files changed, 28 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index eeb9ebe562..2c34597136 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -2,7 +2,7 @@ obj-y += mcheck/ obj-y += microcode/ obj-y += mtrr/ -obj-y += amd.o +obj-$(CONFIG_AMD) += amd.o obj-$(CONFIG_CENTAUR) += centaur.o obj-y += common.o obj-$(CONFIG_HYGON) += hygon.o diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 580b01d6d5..5930b712bf 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -194,7 +194,7 @@ void ctxt_switch_levelling(const struct vcpu *next) if (cpu_has_cpuid_faulting) set_cpuid_faulting(enable_cpuid_faulting); - else + else if ( IS_ENABLED(CONFIG_AMD) ) amd_set_cpuid_user_dis(enable_cpuid_faulting); return; @@ -340,7 +340,9 @@ void __init early_cpu_init(bool verbose) case X86_VENDOR_INTEL: intel_unlock_cpuid_leaves(c); actual_cpu = intel_cpu_dev; break; #endif +#ifdef CONFIG_AMD case X86_VENDOR_AMD: actual_cpu = amd_cpu_dev; break; +#endif #ifdef CONFIG_CENTAUR case X86_VENDOR_CENTAUR: actual_cpu = centaur_cpu_dev; break; #endif diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 92bb10c504..88902e2d3a 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -919,7 +919,8 @@ static void cf_check svm_ctxt_switch_from(struct vcpu *v) * Possibly clear previous guest selection of SSBD if set. Note that * SPEC_CTRL.SSBD is already handled by svm_vmexit_spec_ctrl. */ - if ( v->arch.msrs->virt_spec_ctrl.raw & SPEC_CTRL_SSBD ) + if ( IS_ENABLED(CONFIG_AMD) && + v->arch.msrs->virt_spec_ctrl.raw & SPEC_CTRL_SSBD ) { ASSERT(v->domain->arch.cpuid->extd.virt_ssbd); amd_set_legacy_ssbd(false); @@ -953,7 +954,8 @@ static void cf_check svm_ctxt_switch_to(struct vcpu *v) wrmsr_tsc_aux(v->arch.msrs->tsc_aux); /* Load SSBD if set by the guest. */ - if ( v->arch.msrs->virt_spec_ctrl.raw & SPEC_CTRL_SSBD ) + if ( IS_ENABLED(CONFIG_AMD) && + v->arch.msrs->virt_spec_ctrl.raw & SPEC_CTRL_SSBD ) { ASSERT(v->domain->arch.cpuid->extd.virt_ssbd); amd_set_legacy_ssbd(true); diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h index fa4e0fc766..da35b82d5a 100644 --- a/xen/arch/x86/include/asm/amd.h +++ b/xen/arch/x86/include/asm/amd.h @@ -158,20 +158,36 @@ #define is_zen4_uarch() boot_cpu_has(X86_FEATURE_AUTO_IBRS) struct cpuinfo_x86; +#ifdef CONFIG_AMD int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, int osvw_id, ...); +#else +static inline int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, + int osvw_id, ...) +{ + return 0; +} +#endif extern s8 opt_allow_unsafe; void fam10h_check_enable_mmcfg(void); void check_enable_amd_mmconf_dmi(void); -extern bool amd_acpi_c1e_quirk; void amd_check_disable_c1e(unsigned int port, u8 value); extern bool amd_legacy_ssbd; -extern bool amd_virt_spec_ctrl; bool amd_setup_legacy_ssbd(void); void amd_set_legacy_ssbd(bool enable); void amd_set_cpuid_user_dis(bool enable); +#ifdef CONFIG_AMD +extern bool amd_acpi_c1e_quirk; +extern bool amd_virt_spec_ctrl; +#else + +#define amd_acpi_c1e_quirk (false) +#define amd_virt_spec_ctrl (false) + +#endif + #endif /* __AMD_H__ */ diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index ba6c3e80d2..1964a417de 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -1893,10 +1893,12 @@ void __init init_speculation_mitigations(void) setup_force_cpu_cap(X86_FEATURE_SC_MSR_HVM); } +#ifdef CONFIG_AMD /* Support VIRT_SPEC_CTRL.SSBD if AMD_SSBD is not available. */ if ( opt_msr_sc_hvm && !cpu_has_amd_ssbd && (cpu_has_virt_ssbd || (amd_legacy_ssbd && amd_setup_legacy_ssbd())) ) amd_virt_spec_ctrl = true; +#endif /* Figure out default_xen_spec_ctrl. */ if ( has_spec_ctrl && ibrs )