From patchwork Sat Aug 17 21:00:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEA92C531DF for ; Sat, 17 Aug 2024 21:00:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 67C7510E119; Sat, 17 Aug 2024 21:00:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hIktokVV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1731510E111; Sat, 17 Aug 2024 21:00:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723928451; x=1755464451; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=27Dy3QHgbxGK5t8zCgoF+EsYEVf6jHP8Qa4lYzM5n2s=; b=hIktokVV3S/0kKXgZdysxJPHFKpjvFPDOQu+Kdlby6EN2EhMvIz9rPGv ZQecHUxZ3Icz9nCRP08AHKRjUX3zVutmVeBKDwF9tPenp5HO6Ph/WC02V YB5T6u8SyVdfTXZVu7gqYTrtNwHfeyEK6lgk2XvFMvDgm+hMFh/YaJa2c Rh9DzLDALkSC6EHevR+T4HYKFN4lcSH7XbteUbEG8Bk7uASd2X6IQABpA aZH3hyuEDCcEfn419KMfEg5UVm3DISTris+bKry92DrLaIWOhHyifCm94 tr0nb6oK4282PRz+XsYlW6L7FGlIi7Txswl3ogrdZGN1Gv3UKwM9BZlcI A==; X-CSE-ConnectionGUID: eRZFoXRASdebbvzKHA7IHA== X-CSE-MsgGUID: 7VOJ3hT+RISWcDXrqQ8B/w== X-IronPort-AV: E=McAfee;i="6700,10204,11167"; a="44725420" X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="44725420" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:00:51 -0700 X-CSE-ConnectionGUID: AU3/WUcLTxWGQBHCrLvELw== X-CSE-MsgGUID: uRDi0srsQwCZei9KkMl+Sg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="59635906" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:00:48 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH v2 01/11] drm/i915/gt: Move the CCS mode variable to a global position Date: Sat, 17 Aug 2024 23:00:16 +0200 Message-ID: <20240817210026.310645-2-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Store the CCS mode value in the intel_gt->ccs structure to make it available for future instances that may need to change its value. Name it mode_reg_val because it holds the value that will be written into the CCS_MODE register, determining the CCS balancing and, consequently, the number of engines generated. Create a mutex to control access to the mode_reg_val variable. No functional changes intended. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++ drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 13 ++++++++++--- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 3 ++- drivers/gpu/drm/i915/gt/intel_gt_types.h | 12 ++++++++++++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++--- 5 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index a6c69a706fd7..5af0527d822d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -18,6 +18,7 @@ #include "intel_ggtt_gmch.h" #include "intel_gt.h" #include "intel_gt_buffer_pool.h" +#include "intel_gt_ccs_mode.h" #include "intel_gt_clock_utils.h" #include "intel_gt_debugfs.h" #include "intel_gt_mcr.h" @@ -136,6 +137,8 @@ int intel_gt_init_mmio(struct intel_gt *gt) intel_sseu_info_init(gt); intel_gt_mcr_init(gt); + intel_gt_ccs_mode_init(gt); + return intel_engines_init_mmio(gt); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 3c62a44e9106..19e0bc359861 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -8,14 +8,16 @@ #include "intel_gt_ccs_mode.h" #include "intel_gt_regs.h" -unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) +void intel_gt_apply_ccs_mode(struct intel_gt *gt) { int cslice; u32 mode = 0; int first_ccs = __ffs(CCS_MASK(gt)); + lockdep_assert_held(>->ccs.mutex); + if (!IS_DG2(gt->i915)) - return 0; + return; /* Build the value for the fixed CCS load balancing */ for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { @@ -35,5 +37,10 @@ unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) XEHP_CCS_MODE_CSLICE_MASK); } - return mode; + gt->ccs.mode_reg_val = mode; +} + +void intel_gt_ccs_mode_init(struct intel_gt *gt) +{ + mutex_init(>->ccs.mutex); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 55547f2ff426..e646ab595ded 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -8,6 +8,7 @@ struct intel_gt; -unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); +void intel_gt_apply_ccs_mode(struct intel_gt *gt); +void intel_gt_ccs_mode_init(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index bcee084b1f27..8df8fac066c0 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -207,12 +207,24 @@ struct intel_gt { [MAX_ENGINE_INSTANCE + 1]; enum intel_submission_method submission_method; + /* + * Track fixed mapping between CCS engines and compute slices. + * + * In order to w/a HW that has the inability to dynamically load + * balance between CCS engines and EU in the compute slices, we have to + * reconfigure a static mapping on the fly. + * + * The mode variable is set by the user and sets the balancing mode, + * i.e. how the CCS streams are distributed amongs the slices. + */ struct { /* * Mask of the non fused CCS slices * to be used for the load balancing */ intel_engine_mask_t cslices; + struct mutex mutex; + u32 mode_reg_val; } ccs; /* diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index bfe6d8fc820f..daa11e11d68f 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2727,7 +2727,6 @@ add_render_compute_tuning_settings(struct intel_gt *gt, static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct intel_gt *gt = engine->gt; - u32 mode; if (!IS_DG2(gt->i915)) return; @@ -2744,8 +2743,10 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li * After having disabled automatic load balancing we need to * assign all slices to a single CCS. We will call it CCS mode 1 */ - mode = intel_gt_apply_ccs_mode(gt); - wa_masked_en(wal, XEHP_CCS_MODE, mode); + mutex_lock(>->ccs.mutex); + intel_gt_apply_ccs_mode(gt); + wa_masked_en(wal, XEHP_CCS_MODE, gt->ccs.mode_reg_val); + mutex_unlock(>->ccs.mutex); } /* From patchwork Sat Aug 17 21:00:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFE6EC531DF for ; Sat, 17 Aug 2024 21:00:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 454FB10E0F4; Sat, 17 Aug 2024 21:00:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="VWpxTU9A"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 41CCC10E0F0; Sat, 17 Aug 2024 21:00:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723928457; x=1755464457; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s9cPQTojqszj+XOenc3Whuv3c+51r8FcL6ydwiO+u0k=; b=VWpxTU9AC+CXWVu3aGBTF3xmIRL5slFMQqsyftfB4R8rvtD/BrUXtlwJ 8TkNPfyGD1PaCv/gYvqN9vVbxqsKs2mJxbAwigbWjUTy1YzgqKOkqvqoC FS6owfzJrs9KGKBvkvOuzKsJLvDfSTI7BYIy+UOYy8jVeN+CDb0dzHFrg rXqhwlL5ASJ9trXeXFP99osNa7Y46wbbQKrjb4Aa7kVSPb0/xCJBT/mva C9/r2mo9ARCRb5Hij7kAseZ7XZ0mfHFv3a2zsX+Fe5naTigbG2ULtXnOn y4I/MPAoKhudEY6etkE/mPGnP48UU9zQUxrsSCHQd1/wEztqjyGSLfL5Q Q==; X-CSE-ConnectionGUID: maAlE068Q6WXkEj4U8qMVQ== X-CSE-MsgGUID: D3Q0zLrbR3SOEjwV0MNEww== X-IronPort-AV: E=McAfee;i="6700,10204,11167"; a="44725424" X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="44725424" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:00:57 -0700 X-CSE-ConnectionGUID: jCNR9VbpQfKDSuxD8Hg0Zw== X-CSE-MsgGUID: P9UQnbDOQLqD29z+O2wPTw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="59635929" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:00:54 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH v2 02/11] drm/i915/gt: Allow the creation of multi-mode CCS masks Date: Sat, 17 Aug 2024 23:00:17 +0200 Message-ID: <20240817210026.310645-3-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Until now, we have only set CCS mode balancing to 1, which means that only one compute engine is exposed to the user. The stream of compute commands submitted to that engine is then shared among all the dedicated execution units. This is done by calling the 'intel_gt_apply_ccs_mode(); function. With this change, the aforementioned function takes an additional parameter called 'mode' that specifies the desired mode to be set for the CCS engines balancing. The mode parameter can have the following values: - mode = 0: CCS load balancing mode 1 (1 CCS engine exposed) - mode = 1: CCS load balancing mode 2 (2 CCS engines exposed) - mode = 3: CCS load balancing mode 4 (4 CCS engines exposed) This allows us to generate the appropriate register value to be written to CCS_MODE, configuring how the exposed engine streams will be submitted to the execution units. No functional changes are intended yet, as no mode higher than '0' is currently being set. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 78 ++++++++++++++++----- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 4 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- 3 files changed, 65 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 19e0bc359861..6afd44ffc358 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -4,37 +4,83 @@ */ #include "i915_drv.h" -#include "intel_gt.h" #include "intel_gt_ccs_mode.h" #include "intel_gt_regs.h" -void intel_gt_apply_ccs_mode(struct intel_gt *gt) +void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode) { + unsigned long cslices_mask = gt->ccs.cslices; + u32 mode_val = 0; + u32 m = mode; + int ccs_id; int cslice; - u32 mode = 0; - int first_ccs = __ffs(CCS_MASK(gt)); lockdep_assert_held(>->ccs.mutex); if (!IS_DG2(gt->i915)) return; - /* Build the value for the fixed CCS load balancing */ - for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { - if (gt->ccs.cslices & BIT(cslice)) - /* - * If available, assign the cslice - * to the first available engine... - */ - mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs); + /* + * The mode has two bit dedicated for each engine + * that will be used for the CCS balancing algorithm: + * + * BIT | CCS slice + * ------------------ + * 0 | CCS slice + * 1 | 0 + * ------------------ + * 2 | CCS slice + * 3 | 1 + * ------------------ + * 4 | CCS slice + * 5 | 2 + * ------------------ + * 6 | CCS slice + * 7 | 3 + * ------------------ + * + * When a CCS slice is not available, then we will write 0x7, + * oterwise we will write the user engine id which load will + * be forwarded to that slice. + * + * The possible configurations are: + * + * 1 engine (ccs0): + * slice 0, 1, 2, 3: ccs0 + * + * 2 engines (ccs0, ccs1): + * slice 0, 2: ccs0 + * slice 1, 3: ccs1 + * + * 4 engines (ccs0, ccs1, ccs2, ccs3): + * slice 0: ccs0 + * slice 1: ccs1 + * slice 2: ccs2 + * slice 3: ccs3 + */ + ccs_id = __ffs(cslices_mask); - else + for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { + if (!(cslices_mask & BIT(cslice))) { /* - * ... otherwise, mark the cslice as - * unavailable if no CCS dispatches here + * If not available, mark the slice as unavailable + * and no task will be dispatched here. */ - mode |= XEHP_CCS_MODE_CSLICE(cslice, + mode_val |= XEHP_CCS_MODE_CSLICE(cslice, XEHP_CCS_MODE_CSLICE_MASK); + continue; + } + + mode_val |= XEHP_CCS_MODE_CSLICE(cslice, ccs_id); + + if (!m) { + m = mode; + ccs_id = __ffs(cslices_mask); + continue; + } + + m--; + ccs_id = find_next_bit(&cslices_mask, I915_MAX_CCS, ccs_id + 1); } gt->ccs.mode_reg_val = mode; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index e646ab595ded..0e1c43ea1d54 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -6,9 +6,9 @@ #ifndef __INTEL_GT_CCS_MODE_H__ #define __INTEL_GT_CCS_MODE_H__ -struct intel_gt; +#include "intel_gt.h" -void intel_gt_apply_ccs_mode(struct intel_gt *gt); +void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode); void intel_gt_ccs_mode_init(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index daa11e11d68f..203f2bb00e30 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2744,7 +2744,7 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li * assign all slices to a single CCS. We will call it CCS mode 1 */ mutex_lock(>->ccs.mutex); - intel_gt_apply_ccs_mode(gt); + intel_gt_apply_ccs_mode(gt, 0); wa_masked_en(wal, XEHP_CCS_MODE, gt->ccs.mode_reg_val); mutex_unlock(>->ccs.mutex); } From patchwork Sat Aug 17 21:00:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECCDAC531DF for ; Sat, 17 Aug 2024 21:01:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6531B10E0E9; Sat, 17 Aug 2024 21:01:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jMv8tx1J"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id A3BE410E0E9; Sat, 17 Aug 2024 21:01:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723928465; x=1755464465; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JGqZlLASKOiUpSGJmG2JheBwcGaqDp6yUy/4Dd817zo=; b=jMv8tx1Jupnl/9H2w1MHMOIb06y7lItaFzUBVHwTyNsTDT6pZ7Vz0qOK nv8nyBmGabj8hs6D/RWqEtajSwLGr7l57x2umDiQle72MYpLPLpF/aNTG ViXyv4EaljfM0MwDD9vNXqLaHt1oCqRVog893+qptkGGFedcPB/FmAbAq E9E3sGW/G4DrWWsEySMcGaffthqiSmpXDLjLlmY+shB3wZrlp0vqiET+j p1EbtmLGNCrAocT2+Twi5pgGI/mcNL5N5IJWuHzEz8KWL2ATHGJrSqFCZ R0K+1w7L/hqSNgo2Nra4dV2p+yKNrMTDWt6bO0+WIN1h3jksnoG3gouXi g==; X-CSE-ConnectionGUID: CRyRv9mJR02tzGG93yFNFg== X-CSE-MsgGUID: 9kiof9ElTP2vV4/kUnAs2g== X-IronPort-AV: E=McAfee;i="6700,10204,11167"; a="44725430" X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="44725430" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:04 -0700 X-CSE-ConnectionGUID: uJ31W5azTO6yUiNDucTstA== X-CSE-MsgGUID: wMRgCN/MRKuQQZ9mzJujIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="59635982" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:01 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti , Tvrtko Ursulin Subject: [RFC PATCH v2 03/11] drm/i915/gt: Refactor uabi engine class/instance list creation Date: Sat, 17 Aug 2024 23:00:18 +0200 Message-ID: <20240817210026.310645-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For the upcoming changes we need a cleaner way to build the list of uabi engines. Suggested-by: Tvrtko Ursulin Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 ++++++++++++--------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 833987015b8b..11cc06c0c785 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -203,7 +203,7 @@ static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 void intel_engines_driver_register(struct drm_i915_private *i915) { - u16 name_instance, other_instance = 0; + u16 class_instance[I915_LAST_UABI_ENGINE_CLASS + 2] = { }; struct legacy_ring ring = {}; struct list_head *it, *next; struct rb_node **p, *prev; @@ -214,6 +214,8 @@ void intel_engines_driver_register(struct drm_i915_private *i915) prev = NULL; p = &i915->uabi_engines.rb_node; list_for_each_safe(it, next, &engines) { + u16 uabi_class; + struct intel_engine_cs *engine = container_of(it, typeof(*engine), uabi_list); @@ -222,15 +224,14 @@ void intel_engines_driver_register(struct drm_i915_private *i915) GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes)); engine->uabi_class = uabi_classes[engine->class]; - if (engine->uabi_class == I915_NO_UABI_CLASS) { - name_instance = other_instance++; - } else { - GEM_BUG_ON(engine->uabi_class >= - ARRAY_SIZE(i915->engine_uabi_class_count)); - name_instance = - i915->engine_uabi_class_count[engine->uabi_class]++; - } - engine->uabi_instance = name_instance; + + if (engine->uabi_class == I915_NO_UABI_CLASS) + uabi_class = I915_LAST_UABI_ENGINE_CLASS + 1; + else + uabi_class = engine->uabi_class; + + GEM_BUG_ON(uabi_class >= ARRAY_SIZE(class_instance)); + engine->uabi_instance = class_instance[uabi_class]++; /* * Replace the internal name with the final user and log facing @@ -238,11 +239,15 @@ void intel_engines_driver_register(struct drm_i915_private *i915) */ engine_rename(engine, intel_engine_class_repr(engine->class), - name_instance); + engine->uabi_instance); - if (engine->uabi_class == I915_NO_UABI_CLASS) + if (uabi_class > I915_LAST_UABI_ENGINE_CLASS) continue; + GEM_BUG_ON(uabi_class >= + ARRAY_SIZE(i915->engine_uabi_class_count)); + i915->engine_uabi_class_count[uabi_class]++; + rb_link_node(&engine->uabi_node, prev, p); rb_insert_color(&engine->uabi_node, &i915->uabi_engines); From patchwork Sat Aug 17 21:00:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC616C531DF for ; Sat, 17 Aug 2024 21:01:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7319110E0EF; Sat, 17 Aug 2024 21:01:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Fvkf4Aa4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id E1BE510E0EE; Sat, 17 Aug 2024 21:01:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723928471; x=1755464471; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hRqcWxnm7QAY+HdTQwKERnrJLX4UP1nySHb1xf6tim4=; b=Fvkf4Aa4Sf6HFHVfEKw5qKDOCK4yIM90AfyE1CiqVUoYLwIHJqkDpF6n bvs27E0X7kdTiisG+6frC8UvjVdgYVy8dMjtPZMd9fCV5bmcE+h8GD1Vj ABYesZTfWFxr8JAoKO6PzWd0Ujlv0OnnaX9VbA9qyB0lcXl/QZ8Io8FIK /vFyj3Q0FlhG4RjiiQYtPiW1yvZmiS2STAxQf88vX2cQZE4D9u52rPSek k7FqQukP7fIe6bTflx/BJAVzT36YSwv9jbzMPCQS+T9SOZUr7u2AX26Mx Q/Z2MXka8KUb5o+XTh+ZDh0lHWNGyn4ICS2kESQldMS7KT0g4enNKgKqr g==; X-CSE-ConnectionGUID: Wr6jVRlTSJiogQJ/efdHMQ== X-CSE-MsgGUID: o4Qv23Z9SFWEH6JoBIFqcg== X-IronPort-AV: E=McAfee;i="6700,10204,11167"; a="44725434" X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="44725434" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:11 -0700 X-CSE-ConnectionGUID: pnVWmYnRQX23g9DOlMyoZQ== X-CSE-MsgGUID: 9OYMuBRaSxCkyGAYLaC1qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="59635998" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:08 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH v2 04/11] drm/i915/gt: Manage CCS engine creation within UABI exposure Date: Sat, 17 Aug 2024 23:00:19 +0200 Message-ID: <20240817210026.310645-5-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In commit ea315f98e5d6 ("drm/i915/gt: Do not generate the command streamer for all the CCS"), we restricted the creation of physical CCS engines to only one stream. This allowed the user to submit a single compute workload, with all CCS slices sharing the workload from that stream. This patch removes that limitation but still exposes only one stream to the user. The physical memory for each engine remains allocated but unused, however the user will only see one engine exposed. Do this by adding only one engine to the UABI list, ensuring that only one engine is visible to the user. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 23 --------------------- drivers/gpu/drm/i915/gt/intel_engine_user.c | 20 +++++++++++++++--- 2 files changed, 17 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 4d30a86016f2..def255ee0b96 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -876,29 +876,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) info->engine_mask &= ~BIT(GSC0); } - /* - * Do not create the command streamer for CCS slices beyond the first. - * All the workload submitted to the first engine will be shared among - * all the slices. - * - * Once the user will be allowed to customize the CCS mode, then this - * check needs to be removed. - */ - if (IS_DG2(gt->i915)) { - u8 first_ccs = __ffs(CCS_MASK(gt)); - - /* - * Store the number of active cslices before - * changing the CCS engine configuration - */ - gt->ccs.cslices = CCS_MASK(gt); - - /* Mask off all the CCS engine */ - info->engine_mask &= ~GENMASK(CCS3, CCS0); - /* Put back in the first CCS engine */ - info->engine_mask |= BIT(_CCS(first_ccs)); - } - return info->engine_mask; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 11cc06c0c785..c5ccb677ed15 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -207,6 +207,7 @@ void intel_engines_driver_register(struct drm_i915_private *i915) struct legacy_ring ring = {}; struct list_head *it, *next; struct rb_node **p, *prev; + u8 uabi_ccs_instance = 0; LIST_HEAD(engines); sort_engines(i915, &engines); @@ -246,6 +247,22 @@ void intel_engines_driver_register(struct drm_i915_private *i915) GEM_BUG_ON(uabi_class >= ARRAY_SIZE(i915->engine_uabi_class_count)); + + /* Fix up the mapping to match default execbuf::user_map[] */ + add_legacy_ring(&ring, engine); + + /* + * Do not create the command streamer for CCS slices beyond the + * first. All the workload submitted to the first engine will be + * shared among all the slices. + */ + if (IS_DG2(i915) && uabi_class == I915_ENGINE_CLASS_COMPUTE) { + uabi_ccs_instance++; + + if (uabi_ccs_instance > 1) + continue; + } + i915->engine_uabi_class_count[uabi_class]++; rb_link_node(&engine->uabi_node, prev, p); @@ -255,9 +272,6 @@ void intel_engines_driver_register(struct drm_i915_private *i915) engine->uabi_class, engine->uabi_instance) != engine); - /* Fix up the mapping to match default execbuf::user_map[] */ - add_legacy_ring(&ring, engine); - prev = &engine->uabi_node; p = &prev->rb_right; } From patchwork Sat Aug 17 21:00:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E7DEC5320E for ; Sat, 17 Aug 2024 21:01:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8211410E0F1; Sat, 17 Aug 2024 21:01:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="TxE+ztWY"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 15E5910E0F5; Sat, 17 Aug 2024 21:01:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723928478; x=1755464478; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ly9Fdr/iERN3yio0j4/aEZELJnKRa+GMJXVmIwYHrC4=; b=TxE+ztWYGZAdioXCiLMXf+T6oiYvmZaZRDIvSY87QrCX5XhThtGLExMF IEjPeekRm9ECnqzm1TpQdzNVoh7ni8xveycCE6DhTABOp3XB31HxOopxJ amC+hEK5IDfd+U5kr2PVV8gp43DYM8+le4zTDMruIfNVBxDeQOdMJqj7M zAdxvIEzMFuTZZtZIpgCjQ4daG9/OCO+JFaSy5fc/loafE3wOudINdIee +sYdltPFlv4GL40ketfM6jU1g7NK/zTJ+Kt7UsVo/5BBhR/lmH0MdlEX/ TmSofyTnquThWy+TckOZ0KsEGmOfOvsSKvfkhvcdDlGOn0Ti/hH1fHJou g==; X-CSE-ConnectionGUID: 6YThCiScQUWK3s/kMmTC9Q== X-CSE-MsgGUID: 2j0B5gbsQD69MyEOlgWLow== X-IronPort-AV: E=McAfee;i="6700,10204,11167"; a="44725435" X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="44725435" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:18 -0700 X-CSE-ConnectionGUID: aJsGh4/oQ1mGBUFCjOmF6Q== X-CSE-MsgGUID: eloRSpWoTdKyVysXsidmVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="59636027" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:15 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH v2 05/11] drm/i915/gt: Remove cslices mask value from the CCS structure Date: Sat, 17 Aug 2024 23:00:20 +0200 Message-ID: <20240817210026.310645-6-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Following the decision to manage CCS engine creation within UABI engines, the "cslices" variable in the "ccs" structure in the "gt" is no longer needed. Remove it is now redundant. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 ----- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 6afd44ffc358..2b6d4ee7445d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -9,7 +9,7 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode) { - unsigned long cslices_mask = gt->ccs.cslices; + unsigned long cslices_mask = CCS_MASK(gt); u32 mode_val = 0; u32 m = mode; int ccs_id; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 8df8fac066c0..a833b395237b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -218,11 +218,6 @@ struct intel_gt { * i.e. how the CCS streams are distributed amongs the slices. */ struct { - /* - * Mask of the non fused CCS slices - * to be used for the load balancing - */ - intel_engine_mask_t cslices; struct mutex mutex; u32 mode_reg_val; } ccs; From patchwork Sat Aug 17 21:00:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AEF9C5320E for ; Sat, 17 Aug 2024 21:01:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ECDEB10E0F5; Sat, 17 Aug 2024 21:01:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="M1GWlSn4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 92EEA10E0F5; Sat, 17 Aug 2024 21:01:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723928485; x=1755464485; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B9OgBmVd648VmceVYnVTJpLYOSn5iB8gtSm80epqr6k=; b=M1GWlSn4REsym+/sDkpCwvKe/LF3APedaAbz2ZtKxH/YLVppmHKzoS88 r9FETe2By1S0JhFI41xYalhrzgoGJw7KvFeoZZQ1KLGUZ/EG72YWbhJ9w g3g5944hay9sEFRyoT5EehziwP4nNeR6hnOjZ3OB+YXwaK03ptBOtWBMH Xd7wR5yAZNW48nirmsB2jQ4E1HR/53EjfGtxcn9X5Ilap3/A3V9fKjUJU t4J+fURpglwZUwpaq2+2idERr7cPk1KVsabVnht0R/d0/jG+8i3b0oGs8 V9YQ8J5QrpDYSMzZBpI5LnLMPN+eUTWC1F+Gq83jsLzrX1oLaOsgpSdvT g==; X-CSE-ConnectionGUID: WhOxCBiaSkKQ3UmdkgkLrw== X-CSE-MsgGUID: R6INVbr3TEKhId0pF6ouzw== X-IronPort-AV: E=McAfee;i="6700,10204,11167"; a="32775436" X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="32775436" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:24 -0700 X-CSE-ConnectionGUID: 3z7qy1JhSFi+5kF6BpphcA== X-CSE-MsgGUID: caZ9TyzURUGw5dBv33e1hw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="64382536" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:23 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH v2 06/11] drm/i915/gt: Expose the number of total CCS slices Date: Sat, 17 Aug 2024 23:00:21 +0200 Message-ID: <20240817210026.310645-7-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement a sysfs interface to show the number of available CCS slices. The displayed number does not take into account the CCS balancing mode. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 24 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 2 ++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 2b6d4ee7445d..49493928f714 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -5,7 +5,9 @@ #include "i915_drv.h" #include "intel_gt_ccs_mode.h" +#include "intel_gt_print.h" #include "intel_gt_regs.h" +#include "intel_gt_sysfs.h" void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode) { @@ -90,3 +92,25 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) { mutex_init(>->ccs.mutex); } + +static ssize_t num_cslices_show(struct device *dev, + struct device_attribute *attr, + char *buff) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + u32 num_slices; + + num_slices = hweight32(CCS_MASK(gt)); + + return sysfs_emit(buff, "%u\n", num_slices); +} +static DEVICE_ATTR_RO(num_cslices); + +void intel_gt_sysfs_ccs_init(struct intel_gt *gt) +{ + int err; + + err = sysfs_create_file(>->sysfs_gt, &dev_attr_num_cslices.attr); + if (err) + gt_dbg(gt, "failed to create sysfs num_cslices files\n"); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 0e1c43ea1d54..c60bfdb54e37 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -9,6 +9,7 @@ #include "intel_gt.h" void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode); +void intel_gt_sysfs_ccs_init(struct intel_gt *gt); void intel_gt_ccs_mode_init(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c index 33cba406b569..895eedc402ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c @@ -12,6 +12,7 @@ #include "i915_drv.h" #include "i915_sysfs.h" #include "intel_gt.h" +#include "intel_gt_ccs_mode.h" #include "intel_gt_print.h" #include "intel_gt_sysfs.h" #include "intel_gt_sysfs_pm.h" @@ -101,6 +102,7 @@ void intel_gt_sysfs_register(struct intel_gt *gt) goto exit_fail; intel_gt_sysfs_pm_init(gt, >->sysfs_gt); + intel_gt_sysfs_ccs_init(gt); return; From patchwork Sat Aug 17 21:00:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D24ACC5321D for ; Sat, 17 Aug 2024 21:01:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F6E510E0FD; Sat, 17 Aug 2024 21:01:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Us+cD4LV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id E375B10E0FF; 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17 Aug 2024 14:01:31 -0700 X-CSE-ConnectionGUID: j8rVicVhRW2eYaqeerbEvw== X-CSE-MsgGUID: G6o9C0gNRFebw1WXKPBuNQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="64382540" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:29 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH v2 07/11] drm/i915/gt: Store engine-related sysfs kobjects Date: Sat, 17 Aug 2024 23:00:22 +0200 Message-ID: <20240817210026.310645-8-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Upcoming commits will need to access engine-related kobjects to enable the creation and destruction of sysfs interfaces at runtime. For this, store the "engine" directory (i915->sysfs_engine), the engine files (gt->kobj), and the default data (gt->kobj_defaults). Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +++ drivers/gpu/drm/i915/gt/sysfs_engines.c | 6 ++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + 3 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index ba55c059063d..a0f2f5c08388 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -388,6 +388,9 @@ struct intel_engine_cs { u32 context_size; u32 mmio_base; + struct kobject *kobj; + struct kobject *kobj_defaults; + struct intel_engine_tlb_inv tlb_inv; /* diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c b/drivers/gpu/drm/i915/gt/sysfs_engines.c index 021f51d9b456..d0bb2aa561ed 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.c +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c @@ -479,6 +479,8 @@ static void add_defaults(struct kobj_engine *parent) if (intel_engine_has_preempt_reset(ke->engine) && sysfs_create_file(&ke->base, &preempt_timeout_def.attr)) return; + + parent->engine->kobj_defaults = &ke->base; } void intel_engines_add_sysfs(struct drm_i915_private *i915) @@ -506,6 +508,8 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) if (!dir) return; + i915->sysfs_engine = dir; + for_each_uabi_engine(engine, i915) { struct kobject *kobj; @@ -526,6 +530,8 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) add_defaults(container_of(kobj, struct kobj_engine, base)); + engine->kobj = kobj; + if (0) { err_object: kobject_put(kobj); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 94f7f6cc444c..3a8a757f5bd5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -320,6 +320,7 @@ struct drm_i915_private { struct intel_gt *gt[I915_MAX_GT]; struct kobject *sysfs_gt; + struct kobject *sysfs_engine; /* Quick lookup of media GT (current platforms only have one) */ struct intel_gt *media_gt; From patchwork Sat Aug 17 21:00:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74779C5320E for ; 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X-CSE-ConnectionGUID: AOBGPzU0QbyhfYhDKXUXZQ== X-CSE-MsgGUID: AQ8ZH+R1SD+xBm6v3KdQGA== X-IronPort-AV: E=McAfee;i="6700,10204,11167"; a="32775445" X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="32775445" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:37 -0700 X-CSE-ConnectionGUID: a//IdLayRl6SMMwgDQE4/w== X-CSE-MsgGUID: RPVlaKHoQN6EsNvilvut3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="64382559" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:36 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH v2 08/11] drm/i915/gt: Store active CCS mask Date: Sat, 17 Aug 2024 23:00:23 +0200 Message-ID: <20240817210026.310645-9-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To support upcoming patches, we need to store the current mask for active CCS engines. Active engines refer to those exposed to userspace via the UABI engine list. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 49493928f714..01ce719cf475 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -9,6 +9,23 @@ #include "intel_gt_regs.h" #include "intel_gt_sysfs.h" +static void update_ccs_mask(struct intel_gt *gt, u32 ccs_mode) +{ + unsigned long cslices_mask = CCS_MASK(gt); + int i; + + /* Mask off all the CCS engines */ + gt->ccs.ccs_mask = 0; + + for_each_set_bit(i, &cslices_mask, I915_MAX_CCS) { + gt->ccs.ccs_mask |= BIT(i); + + ccs_mode--; + if (!ccs_mode) + break; + } +} + void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode) { unsigned long cslices_mask = CCS_MASK(gt); @@ -91,6 +108,9 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode) void intel_gt_ccs_mode_init(struct intel_gt *gt) { mutex_init(>->ccs.mutex); + + /* Set CCS balance mode 1 in the ccs_mask */ + update_ccs_mask(gt, 1); } static ssize_t num_cslices_show(struct device *dev, diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index a833b395237b..235b4b81eecd 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -220,6 +220,7 @@ struct intel_gt { struct { struct mutex mutex; u32 mode_reg_val; + intel_engine_mask_t ccs_mask; } ccs; /* From patchwork Sat Aug 17 21:00:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 337A9C5321D for ; Sat, 17 Aug 2024 21:01:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C87D10E10B; Sat, 17 Aug 2024 21:01:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JleP4JL6"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id DFB4B10E10B; Sat, 17 Aug 2024 21:01:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723928505; x=1755464505; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Q5PxyC1tnw8apAtefvtXAp7XORqkFfgrpqmzyOQHLDY=; b=JleP4JL6crAqR7sB9r22ea/6Pk540dy+KzzadQzbJZ6y2r3C2WFEcNa5 2v6NQ5KcjdBEEH+Sp9peTarINnr2LVb0CwpjkxZ9/ziQftaBG0MAJIsSV yfehWvturgbKQiMkXc0uI92QNMLb/89T5MzMZTBi7hgSnAJti7oJOE8B/ ol0MxfnbkvWtZuKlU5gv1TZQb0+eA4jGUaycUqc9YvxeL+Yr1BFtJ2exN D14W39RYoFJHggtexczBvkfQ7qAiXjIPs8Ip5RTfqMmSs3h0EcPrhBGPG lWQzu4qGtqPSmtWplcv6BFF28v2lUPuGlYtbFhOXI72hgBqA475kx5lre A==; X-CSE-ConnectionGUID: LdBBZb4PRjiuk7k/RgMIkQ== X-CSE-MsgGUID: nfIuOn8TS8yAc904KHcs6w== X-IronPort-AV: E=McAfee;i="6700,10204,11167"; a="32775447" X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="32775447" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:45 -0700 X-CSE-ConnectionGUID: D2FKMOTPT8CYAmgBb1lIyQ== X-CSE-MsgGUID: LL4BF6CER+6bHr+FvUa4Gg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="64382576" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:42 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH v2 09/11] drm/i915/gt: Isolate single sysfs engine file creation Date: Sat, 17 Aug 2024 23:00:24 +0200 Message-ID: <20240817210026.310645-10-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for upcoming patches, we need the ability to create and remove individual sysfs files. To facilitate this, extract from the intel_engines_add_sysfs() function the creation of individual files. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/sysfs_engines.c | 75 ++++++++++++++++--------- drivers/gpu/drm/i915/gt/sysfs_engines.h | 2 + 2 files changed, 49 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c b/drivers/gpu/drm/i915/gt/sysfs_engines.c index d0bb2aa561ed..3356fadce327 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.c +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "intel_engine.h" #include "intel_engine_heartbeat.h" +#include "intel_gt_print.h" #include "sysfs_engines.h" struct kobj_engine { @@ -483,7 +484,7 @@ static void add_defaults(struct kobj_engine *parent) parent->engine->kobj_defaults = &ke->base; } -void intel_engines_add_sysfs(struct drm_i915_private *i915) +int intel_engine_add_single_sysfs(struct intel_engine_cs *engine) { static const struct attribute * const files[] = { &name_attr.attr, @@ -499,46 +500,64 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) #endif NULL }; + struct kobject *dir = engine->i915->sysfs_engine; + struct kobject *kobj = engine->kobj; + int err; - struct device *kdev = i915->drm.primary->kdev; - struct intel_engine_cs *engine; - struct kobject *dir; - - dir = kobject_create_and_add("engine", &kdev->kobj); - if (!dir) - return; - - i915->sysfs_engine = dir; - - for_each_uabi_engine(engine, i915) { - struct kobject *kobj; - + if (!kobj) { kobj = kobj_engine(dir, engine); if (!kobj) goto err_engine; + } - if (sysfs_create_files(kobj, files)) + err = sysfs_create_files(kobj, files); + if (err) + goto err_object; + + if (intel_engine_has_timeslices(engine)) { + err = sysfs_create_file(kobj, ×lice_duration_attr.attr); + if (err) goto err_object; + } - if (intel_engine_has_timeslices(engine) && - sysfs_create_file(kobj, ×lice_duration_attr.attr)) - goto err_engine; + if (intel_engine_has_preempt_reset(engine)) { + err = sysfs_create_file(kobj, &preempt_timeout_attr.attr); + if (err) + goto err_object; + } - if (intel_engine_has_preempt_reset(engine) && - sysfs_create_file(kobj, &preempt_timeout_attr.attr)) - goto err_engine; + add_defaults(container_of(kobj, struct kobj_engine, base)); - add_defaults(container_of(kobj, struct kobj_engine, base)); + engine->kobj = kobj; - engine->kobj = kobj; + return 0; - if (0) { err_object: - kobject_put(kobj); + kobject_put(kobj); err_engine: - dev_err(kdev, "Failed to add sysfs engine '%s'\n", - engine->name); + gt_err(engine->gt, "Failed to add sysfs engine '%s'\n", + engine->name); + + return err; +} + +void intel_engines_add_sysfs(struct drm_i915_private *i915) +{ + struct device *kdev = i915->drm.primary->kdev; + struct intel_engine_cs *engine; + struct kobject *dir; + + dir = kobject_create_and_add("engine", &kdev->kobj); + if (!dir) + return; + + i915->sysfs_engine = dir; + + for_each_uabi_engine(engine, i915) { + int err; + + err = intel_engine_add_single_sysfs(engine); + if (err) break; - } } } diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.h b/drivers/gpu/drm/i915/gt/sysfs_engines.h index 9546fffe03a7..2e3ec2df14a9 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.h +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.h @@ -7,7 +7,9 @@ #define INTEL_ENGINE_SYSFS_H struct drm_i915_private; +struct intel_engine_cs; void intel_engines_add_sysfs(struct drm_i915_private *i915); +int intel_engine_add_single_sysfs(struct intel_engine_cs *engine); #endif /* INTEL_ENGINE_SYSFS_H */ From patchwork Sat Aug 17 21:00:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 400E7C5321D for ; Sat, 17 Aug 2024 21:01:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8726710E10E; Sat, 17 Aug 2024 21:01:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; 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a="32775451" X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="32775451" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:50 -0700 X-CSE-ConnectionGUID: U//LYYSvRo+pv+muXs7zcA== X-CSE-MsgGUID: ELfCJzSRT/GNKAEV0D6O5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="64382590" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:48 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH v2 10/11] drm/i915/gt: Implement creation and removal routines for CCS engines Date: Sat, 17 Aug 2024 23:00:25 +0200 Message-ID: <20240817210026.310645-11-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for upcoming patches, we need routines to dynamically create and destroy CCS engines based on the CCS mode that the user wants to set. The process begins by calculating the engine mask for the engines that need to be added or removed. We then update the UABI list of exposed engines and create or destroy the corresponding sysfs interfaces accordingly. These functions are not yet in use, so no functional changes are intended at this stage. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 80 +++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 01ce719cf475..b1c3c9d9bb4f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -8,6 +8,7 @@ #include "intel_gt_print.h" #include "intel_gt_regs.h" #include "intel_gt_sysfs.h" +#include "sysfs_engines.h" static void update_ccs_mask(struct intel_gt *gt, u32 ccs_mode) { @@ -113,6 +114,85 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) update_ccs_mask(gt, 1); } +static void add_uabi_ccs_engines(struct intel_gt *gt, u32 ccs_mode) +{ + struct drm_i915_private *i915 = gt->i915; + intel_engine_mask_t new_ccs_mask, tmp; + struct intel_engine_cs *engine; + struct rb_node **p, *prev; + + /* Store the current ccs mask */ + new_ccs_mask = gt->ccs.ccs_mask; + update_ccs_mask(gt, ccs_mode); + + /* + * Store only the mask of the CCS engines that need to be added by + * removing from the new mask the engines that are already active + */ + new_ccs_mask = gt->ccs.ccs_mask & ~new_ccs_mask; + new_ccs_mask <<= CCS0; + + /* + * UABI are stored only on the right branch of the rb tree, making it + * de facto a double linked list. Get to the bottom of the list and + * insert there the new engines. + */ + prev = NULL; + p = &i915->uabi_engines.rb_node; + for_each_uabi_engine(engine, i915) { + prev = &engine->uabi_node; + p = &prev->rb_right; + } + + for_each_engine_masked(engine, gt, new_ccs_mask, tmp) { + int err; + + i915->engine_uabi_class_count[I915_ENGINE_CLASS_COMPUTE]++; + + rb_link_node(&engine->uabi_node, prev, p); + rb_insert_color(&engine->uabi_node, &i915->uabi_engines); + + rb_link_node(&engine->uabi_node, prev, p); + rb_insert_color(&engine->uabi_node, &i915->uabi_engines); + + prev = &engine->uabi_node; + p = &prev->rb_right; + + err = intel_engine_add_single_sysfs(engine); + if (err) + gt_warn(gt, + "Unable to create sysfs entries for %s engine", + engine->name); + } +} + +static void remove_uabi_ccs_engines(struct intel_gt *gt, u8 ccs_mode) +{ + struct drm_i915_private *i915 = gt->i915; + intel_engine_mask_t new_ccs_mask, tmp; + struct intel_engine_cs *engine; + + /* Store the current ccs mask */ + new_ccs_mask = gt->ccs.ccs_mask; + update_ccs_mask(gt, ccs_mode); + + /* + * Store only the mask of the CCS engines that need to be removed by + * unmasking them from the new mask the engines that are already active + */ + new_ccs_mask = new_ccs_mask & ~gt->ccs.ccs_mask; + new_ccs_mask <<= CCS0; + + for_each_engine_masked(engine, gt, new_ccs_mask, tmp) { + i915->engine_uabi_class_count[I915_ENGINE_CLASS_COMPUTE]--; + + rb_erase(&engine->uabi_node, &i915->uabi_engines); + /* Remove sysfs entries */ + kobject_put(engine->kobj_defaults); + kobject_put(engine->kobj); + } +} + static ssize_t num_cslices_show(struct device *dev, struct device_attribute *attr, char *buff) From patchwork Sat Aug 17 21:00:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13767237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 671E5C5320E for ; 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X-CSE-ConnectionGUID: eRGrGx45Tn2vyxOe86CY4Q== X-CSE-MsgGUID: kL2sT4u7TV+jh3yT4Q7fdw== X-IronPort-AV: E=McAfee;i="6700,10204,11167"; a="25997146" X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="25997146" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:57 -0700 X-CSE-ConnectionGUID: oG3bBlsFQRif2nubi48UFA== X-CSE-MsgGUID: JLiBBVSdRbiuegsBLiYCuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,155,1719903600"; d="scan'208";a="97489209" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.11]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2024 14:01:54 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Andi Shyti Subject: [RFC PATCH v2 11/11] drm/i915/gt: Allow the user to change the CCS mode through sysfs Date: Sat, 17 Aug 2024 23:00:26 +0200 Message-ID: <20240817210026.310645-12-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240817210026.310645-1-andi.shyti@linux.intel.com> References: <20240817210026.310645-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Create the 'ccs_mode' file under /sys/class/drm/cardX/gt/gt0/ccs_mode This file allows the user to read and set the current CCS mode. - Reading: The user can read the current CCS mode, which can be 1, 2, or 4. This value is derived from the current engine mask. - Writing: The user can set the CCS mode to 1, 2, or 4, depending on the desired number of exposed engines and the required load balancing. The interface will return -EBUSY if other clients are connected to i915, or -EINVAL if an invalid value is set. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 74 +++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index b1c3c9d9bb4f..30393009bc43 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -5,6 +5,7 @@ #include "i915_drv.h" #include "intel_gt_ccs_mode.h" +#include "intel_gt_pm.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" #include "intel_gt_sysfs.h" @@ -206,6 +207,68 @@ static ssize_t num_cslices_show(struct device *dev, } static DEVICE_ATTR_RO(num_cslices); +static ssize_t ccs_mode_show(struct device *dev, + struct device_attribute *attr, char *buff) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + u32 ccs_mode; + + ccs_mode = hweight32(gt->ccs.ccs_mask); + + return sysfs_emit(buff, "%u\n", ccs_mode); +} + +static ssize_t ccs_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buff, size_t count) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + int num_cslices = hweight32(CCS_MASK(gt)); + int ccs_mode = hweight32(gt->ccs.ccs_mask); + ssize_t ret; + u32 val; + + ret = kstrtou32(buff, 0, &val); + if (ret) + return ret; + + /* + * As of now possible values to be set are 1, 2, 4, + * up to the maximum number of available slices + */ + if ((!val) || (val > num_cslices) || (num_cslices % val)) + return -EINVAL; + + /* + * We don't want to change the CCS + * mode while someone is using the GT + */ + if (intel_gt_pm_is_awake(gt)) + return -EBUSY; + + mutex_lock(>->wakeref.mutex); + mutex_lock(>->ccs.mutex); + + /* + * Nothing to do if the requested setting + * is the same as the current one + */ + if (val == ccs_mode) + return count; + else if (val > ccs_mode) + add_uabi_ccs_engines(gt, val); + else + remove_uabi_ccs_engines(gt, val); + + intel_gt_apply_ccs_mode(gt, val); + + mutex_unlock(>->ccs.mutex); + mutex_unlock(>->wakeref.mutex); + + return count; +} +static DEVICE_ATTR_RW(ccs_mode); + void intel_gt_sysfs_ccs_init(struct intel_gt *gt) { int err; @@ -213,4 +276,15 @@ void intel_gt_sysfs_ccs_init(struct intel_gt *gt) err = sysfs_create_file(>->sysfs_gt, &dev_attr_num_cslices.attr); if (err) gt_dbg(gt, "failed to create sysfs num_cslices files\n"); + + /* + * Do not create the ccs_mode file for non DG2 platforms + * because they don't need it as they have only one CCS engine + */ + if (!IS_DG2(gt->i915)) + return; + + err = sysfs_create_file(>->sysfs_gt, &dev_attr_ccs_mode.attr); + if (err) + gt_dbg(gt, "failed to create sysfs ccs_mode files\n"); }