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Signed-off-by: Stefan Eichenberger --- drivers/pci/controller/dwc/pci-imx6.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 964d67756eb2b..fda704d82431f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -722,6 +722,17 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 1); } +static void imx6_pcie_deassert_reset_gpio(struct imx6_pcie *imx6_pcie) +{ + /* Some boards don't have PCIe reset GPIO. */ + if (imx6_pcie->reset_gpiod) { + msleep(100); + gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 0); + /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ + msleep(100); + } +} + static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; @@ -766,13 +777,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) break; 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Mon, 19 Aug 2024 02:04:34 -0700 (PDT) From: Stefan Eichenberger To: hongxing.zhu@nxp.com, l.stach@pengutronix.de, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, francesco.dolcini@toradex.com Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, Stefan Eichenberger Subject: [PATCH v1 2/3] PCI: imx6: move the wait for clock stabilization to enable ref clk Date: Mon, 19 Aug 2024 11:03:18 +0200 Message-ID: <20240819090428.17349-3-eichest@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240819090428.17349-1-eichest@gmail.com> References: <20240819090428.17349-1-eichest@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Stefan Eichenberger After enabling the ref clock, we should wait for the clock to stabilize. To eliminate the need for code duplication in the future, move the usleep to the enable_ref_clk function. Signed-off-by: Stefan Eichenberger --- drivers/pci/controller/dwc/pci-imx6.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index fda704d82431f..f17561791e35a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -632,6 +632,9 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) break; } + /* allow the clocks to stabilize */ + usleep_range(200, 500); + return ret; } @@ -672,8 +675,6 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) goto err_ref_clk; } - /* allow the clocks to stabilize */ - usleep_range(200, 500); return 0; err_ref_clk: From patchwork Mon Aug 19 09:03:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Eichenberger X-Patchwork-Id: 13768096 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1705C15E5B5 for ; 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Mon, 19 Aug 2024 02:04:36 -0700 (PDT) Received: from eichest-laptop.toradex.int ([2a02:168:af72:0:a64c:8731:e4fb:38f1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-429ded19627sm154672095e9.5.2024.08.19.02.04.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2024 02:04:35 -0700 (PDT) From: Stefan Eichenberger To: hongxing.zhu@nxp.com, l.stach@pengutronix.de, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, francesco.dolcini@toradex.com Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, Stefan Eichenberger Subject: [PATCH v1 3/3] PCI: imx6: reset link on resume Date: Mon, 19 Aug 2024 11:03:19 +0200 Message-ID: <20240819090428.17349-4-eichest@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240819090428.17349-1-eichest@gmail.com> References: <20240819090428.17349-1-eichest@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Stefan Eichenberger According to the https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf errata, the i.MX6Q PCIe controller does not support suspend/resume. So suspend and resume was omitted. However, this does not seem to work because it looks like the PCIe link is still expecting a reset. If we do not reset the link, we end up with a frozen system after resume. The last message we see is: ath10k_pci 0000:01:00.0: Unable to change power state from D3hot to D0, device inaccessible Besides resetting the link, we also need to enable msi again, otherwise DMA access will not work and we can still end up with a frozen system. With these changes we can suspend and resume the system properly with a PCIe device attached. This was tested with a Compex WLE900VX miniPCIe Wifi module. Signed-off-by: Stefan Eichenberger --- drivers/pci/controller/dwc/pci-imx6.c | 45 ++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index f17561791e35a..751243f4c519e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1213,14 +1213,57 @@ static int imx6_pcie_suspend_noirq(struct device *dev) return 0; } +static int imx6_pcie_reset_link(struct imx6_pcie *imx6_pcie) +{ + int ret; + + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); + + /* Reset the PCIe device */ + gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 1); + + ret = imx6_pcie_enable_ref_clk(imx6_pcie); + if (ret) { + dev_err(imx6_pcie->pci->dev, "unable to enable pcie ref clock\n"); + return ret; + } + + imx6_pcie_deassert_reset_gpio(imx6_pcie); + + /* + * Setup the root complex again and enable msi. Without this PCIe will + * not work in msi mode and drivers will crash if they try to access + * the device memory area + */ + dw_pcie_setup_rc(&imx6_pcie->pci->pp); + if (pci_msi_enabled()) { + u32 val; + u8 offset = dw_pcie_find_capability(imx6_pcie->pci, PCI_CAP_ID_MSI); + + val = dw_pcie_readw_dbi(imx6_pcie->pci, offset + PCI_MSI_FLAGS); + val |= PCI_MSI_FLAGS_ENABLE; + dw_pcie_writew_dbi(imx6_pcie->pci, offset + PCI_MSI_FLAGS, val); + } + + return 0; +} + static int imx6_pcie_resume_noirq(struct device *dev) { int ret; struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; + /* + * Even though the i.MX6Q does not support suspend/resume, we need to + * reset the link after resume or the memory mapped PCIe I/O space will + * be inaccessible. This will cause the system to freeze. + */ if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) - return 0; + return imx6_pcie_reset_link(imx6_pcie); ret = imx6_pcie_host_init(pp); if (ret)