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Tue, 20 Aug 2024 14:03:21 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 20 Aug 2024 07:03:16 -0700 From: Luo Jie Date: Tue, 20 Aug 2024 22:02:42 +0800 Subject: [PATCH v2 1/4] dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240820-qcom_ipq_cmnpll-v2-1-b000dd335280@quicinc.com> References: <20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@quicinc.com> In-Reply-To: <20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724162591; l=3592; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=LZQvuhQ/UXkTqYZZ41BcYN6OxgJ7mqBZwv/v3P9hSO8=; b=RCaqtMUpqZbot43gO3ilmyblvGAlkXAUDREqjKW6CQHLog27POoewY0s7qJZiCeXX+O7daTl2 ePQ2hrWcsn6BeuR4UOzy4WXyPDizZ/BfmKBpkc29/J0RCtz5szmYy01 X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8OmEvbgGup_lI34R8RYsh7s2phYwWaY- X-Proofpoint-ORIG-GUID: 8OmEvbgGup_lI34R8RYsh7s2phYwWaY- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-20_09,2024-08-19_03,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408200104 The CMN PLL controller provides clocks to networking hardware blocks on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, and produces output clocks at fixed rates. These output rates are predetermined, and are unrelated to the input clock rate. The output clocks are supplied to the Ethernet hardware such as PPE (packet process engine) and the externally connected switch or PHY device. Signed-off-by: Luo Jie Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 +++++ 2 files changed, 85 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml new file mode 100644 index 000000000000..7ad04b58a698 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm CMN PLL Clock Controller on IPQ SoC + +maintainers: + - Bjorn Andersson + - Luo Jie + +description: + The CMN PLL clock controller expects a reference input clock. + This reference clock is from the on-board Wi-Fi. The CMN PLL + supplies a number of fixed rate output clocks to the Ethernet + devices including PPE (packet process engine) and the connected + switch or PHY device. + +properties: + compatible: + enum: + - qcom,ipq9574-cmn-pll + + reg: + maxItems: 1 + + clocks: + items: + - description: The reference clock. The supported clock rates include + 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ. + - description: The AHB clock + - description: The SYS clock + description: + The reference clock is the source clock of CMN PLL, which is from the + Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL + clock registers. + + clock-names: + items: + - const: ref + - const: ahb + - const: sys + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + + clock-controller@9b000 { + compatible = "qcom,ipq9574-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h new file mode 100644 index 000000000000..64b228659389 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H + +/* The output clocks from CMN PLL of IPQ9574. */ +#define PPE_353MHZ_CLK 0 +#define ETH0_50MHZ_CLK 1 +#define ETH1_50MHZ_CLK 2 +#define ETH2_50MHZ_CLK 3 +#define ETH_25MHZ_CLK 4 +#endif From patchwork Tue Aug 20 14:02:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 13770142 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4B32190486; Tue, 20 Aug 2024 14:03:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724162618; cv=none; b=VJSyVi3igcKLf5qqh4uPUjZdUVu1oFnEItpEJKulKAXYgX4aeCpB+n3F3DxA9FDm+jPVoafqo8lrwJ4PiBp5H0Sj1IUmPQOOv/9R3NBVQxfckCcxG2THJDpuHq/bfM1OQeNxnevP1Fu774mLBJPnH728xQOcyLKsStrWhfpg8gk= ARC-Message-Signature: i=1; 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Tue, 20 Aug 2024 14:03:26 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 20 Aug 2024 07:03:21 -0700 From: Luo Jie Date: Tue, 20 Aug 2024 22:02:43 +0800 Subject: [PATCH v2 2/4] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240820-qcom_ipq_cmnpll-v2-2-b000dd335280@quicinc.com> References: <20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@quicinc.com> In-Reply-To: <20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724162592; 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The driver is initially supported for IPQ9574 SoC. The CMN PLL clock controller expects a reference input clock from the on-board Wi-Fi block acting as clock source. The input reference clock needs to be configured to one of the supported clock rates. The controller supplies a number of fixed-rate output clocks. For the IPQ9574, there is one output clock of 353 MHZ to PPE (Packet Process Engine) hardware block, three 50 MHZ output clocks and an additional 25 MHZ output clock supplied to the connected Ethernet devices. Signed-off-by: Luo Jie --- drivers/clk/qcom/Kconfig | 10 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-ipq-cmn-pll.c | 227 +++++++++++++++++++++++++++++++++++++ 3 files changed, 238 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index cf6ad908327f..05bec64bf1dd 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -190,6 +190,16 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. +config IPQ_CMN_PLL + tristate "IPQ CMN PLL Clock Controller" + depends on IPQ_GCC_9574 + help + Support for CMN PLL clock controller on IPQ platform. The + CMN PLL feeds the reference clocks to the Ethernet devices + based on IPQ SoC. + Say Y or M if you want to support CMN PLL clock on the IPQ + based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 8a6f0dabd02f..35f656146de7 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o +obj-$(CONFIG_IPQ_CMN_PLL) += clk-ipq-cmn-pll.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o diff --git a/drivers/clk/qcom/clk-ipq-cmn-pll.c b/drivers/clk/qcom/clk-ipq-cmn-pll.c new file mode 100644 index 000000000000..72030a61a131 --- /dev/null +++ b/drivers/clk/qcom/clk-ipq-cmn-pll.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* + * CMN PLL block expects the reference clock from on-board Wi-Fi block, and + * supplies fixed rate clocks as output to the Ethernet hardware blocks. + * The Ethernet related blocks include PPE (packet process engine) and the + * external connected PHY (or switch) chip receiving clocks from the CMN PLL. + * + * On the IPQ9574 SoC, There are three clocks with 50 MHZ, one clock with + * 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch), + * and one clock with 353 MHZ to PPE. + * + * +---------+ + * | GCC | + * +--+---+--+ + * AHB CLK| |SYS CLK + * V V + * +-------+---+------+ + * | +-------------> eth0-50mhz + * REF CLK | IPQ9574 | + * -------->+ +-------------> eth1-50mhz + * | CMN PLL block | + * | +-------------> eth2-50mhz + * | | + * +---------+--------+-------------> eth-25mhz + * | + * V + * ppe-353mhz + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CMN_PLL_REFCLK_SRC_SELECTION 0x28 +#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) + +#define CMN_PLL_REFCLK_CONFIG 0x784 +#define CMN_PLL_REFCLK_EXTERNAL BIT(9) +#define CMN_PLL_REFCLK_DIV GENMASK(8, 4) +#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) + +#define CMN_PLL_POWER_ON_AND_RESET 0x780 +#define CMN_ANA_EN_SW_RSTN BIT(6) + +/** + * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information + * @id: Clock specifier to be supplied + * @name: Clock name to be registered + * @rate: Clock rate + */ +struct cmn_pll_fixed_output_clk { + unsigned int id; + const char *name; + const unsigned long rate; +}; + +#define CLK_PLL_OUTPUT(_id, _name, _rate) { \ + .id = _id, \ + .name = _name, \ + .rate = _rate, \ +} + +static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { + CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), + CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), +}; + +static int ipq_cmn_pll_config(struct device *dev, unsigned long parent_rate) +{ + void __iomem *base; + u32 val; + + base = devm_of_iomap(dev, dev->of_node, 0, NULL); + if (IS_ERR(base)) + return PTR_ERR(base); + + val = readl(base + CMN_PLL_REFCLK_CONFIG); + val &= ~(CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_INDEX); + + /* + * Configure the reference input clock selection as per the given rate. + * The output clock rates are always of fixed value. + */ + switch (parent_rate) { + case 25000000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3); + break; + case 31250000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4); + break; + case 40000000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6); + break; + case 48000000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7); + break; + case 50000000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8); + break; + case 96000000: + val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7); + val &= ~CMN_PLL_REFCLK_DIV; + val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2); + break; + default: + return -EINVAL; + } + + writel(val, base + CMN_PLL_REFCLK_CONFIG); + + /* Update the source clock rate selection. Only 96 MHZ uses 0. */ + val = readl(base + CMN_PLL_REFCLK_SRC_SELECTION); + val &= ~CMN_PLL_REFCLK_SRC_DIV; + if (parent_rate != 96000000) + val |= FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 1); + + writel(val, base + CMN_PLL_REFCLK_SRC_SELECTION); + + /* + * Reset the CMN PLL block by asserting/de-asserting for 100 ms + * each, to ensure the updated configurations take effect. + */ + val = readl(base + CMN_PLL_POWER_ON_AND_RESET); + val &= ~CMN_ANA_EN_SW_RSTN; + writel(val, base); + msleep(100); + + val |= CMN_ANA_EN_SW_RSTN; + writel(val, base + CMN_PLL_POWER_ON_AND_RESET); + msleep(100); + + return 0; +} + +static int ipq_cmn_pll_clk_register(struct device *dev, const char *parent) +{ + const struct cmn_pll_fixed_output_clk *fixed_clk; + struct clk_hw_onecell_data *data; + unsigned int num_clks; + struct clk_hw *hw; + int i; + + num_clks = ARRAY_SIZE(ipq9574_output_clks); + fixed_clk = ipq9574_output_clks; + + data = devm_kzalloc(dev, struct_size(data, hws, num_clks), GFP_KERNEL); + if (!data) + return -ENOMEM; + + for (i = 0; i < num_clks; i++) { + hw = devm_clk_hw_register_fixed_rate(dev, fixed_clk[i].name, + parent, 0, + fixed_clk[i].rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + data->hws[fixed_clk[i].id] = hw; + } + data->num = num_clks; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); +} + +static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk *clk; + int ret; + + /* + * To access the CMN PLL registers, the GCC AHB & SYSY clocks + * for CMN PLL block need to be enabled. + */ + clk = devm_clk_get_enabled(dev, "ahb"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Enable AHB clock failed\n"); + + clk = devm_clk_get_enabled(dev, "sys"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Enable SYS clock failed\n"); + + clk = devm_clk_get(dev, "ref"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Get reference clock failed\n"); + + /* Configure CMN PLL to apply the reference clock. */ + ret = ipq_cmn_pll_config(dev, clk_get_rate(clk)); + if (ret) + return dev_err_probe(dev, ret, "Configure CMN PLL failed\n"); + + return ipq_cmn_pll_clk_register(dev, __clk_get_name(clk)); +} + +static const struct of_device_id ipq_cmn_pll_clk_ids[] = { + { .compatible = "qcom,ipq9574-cmn-pll", }, + { } +}; + +static struct platform_driver ipq_cmn_pll_clk_driver = { + .probe = ipq_cmn_pll_clk_probe, + .driver = { + .name = "ipq_cmn_pll", + .of_match_table = ipq_cmn_pll_clk_ids, + }, +}; + +module_platform_driver(ipq_cmn_pll_clk_driver); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. 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It provides fixed rate output clocks to Ethernet related hardware blocks such as external Ethernet PHY or switch. This driver is initially being enabled for IPQ9574. All boards based on IPQ9574 SoC will require to include this driver in the build. This CMN PLL hardware block does not provide any other specific function on the IPQ SoC other than enabling output clocks to Ethernet related devices. Signed-off-by: Luo Jie Reviewed-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 01dd286ba7ef..1bc7bd86e589 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1300,6 +1300,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y +CONFIG_IPQ_CMN_PLL=m CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y From patchwork Tue Aug 20 14:02:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 13770144 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 215C01917FE; Tue, 20 Aug 2024 14:03:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 20 Aug 2024 14:03:36 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47KE3a7C006463 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Aug 2024 14:03:36 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 20 Aug 2024 07:03:31 -0700 From: Luo Jie Date: Tue, 20 Aug 2024 22:02:45 +0800 Subject: [PATCH v2 4/4] arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240820-qcom_ipq_cmnpll-v2-4-b000dd335280@quicinc.com> References: <20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@quicinc.com> In-Reply-To: <20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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It in-turn supplies fixed rate output clocks to the hardware blocks that provide ethernet functions, such as PPE (Packet Process Engine) and connected switch or PHY. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 6 +++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 ++++++++++++++++- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..77e1e42083f3 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -3,7 +3,7 @@ * IPQ9574 RDP board common device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -164,6 +164,10 @@ &usb3 { status = "okay"; }; +&cmn_pll_ref_clk { + clock-frequency = <48000000>; +}; + &xo_board_clk { clock-frequency = <24000000>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 48dfafea46a7..1d7c863018c0 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -3,7 +3,7 @@ * IPQ9574 SoC device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -19,6 +19,11 @@ / { #size-cells = <2>; clocks { + cmn_pll_ref_clk: cmn-pll-ref-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -226,6 +231,16 @@ rpm_msg_ram: sram@60000 { reg = <0x00060000 0x6000>; }; + clock-controller@9b000 { + compatible = "qcom,ipq9574-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>;