From patchwork Wed Aug 21 08:26:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "friday.yang" X-Patchwork-Id: 13771068 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77E75C52D7C for ; Wed, 21 Aug 2024 08:40:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Wed, 21 Aug 2024 01:29:33 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 21 Aug 2024 16:28:55 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 21 Aug 2024 16:28:54 +0800 From: friday.yang To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Yong Wu , Philipp Zabel , Friday Yang , , , , , Subject: [PATCH 1/4] dt-bindings: memory: mediatek: Add mt8188 SMI reset control binding Date: Wed, 21 Aug 2024 16:26:49 +0800 Message-ID: <20240821082845.11792-2-friday.yang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240821082845.11792-1-friday.yang@mediatek.com> References: <20240821082845.11792-1-friday.yang@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.829500-8.000000 X-TMASE-MatchedRID: R3B6Edw+gpAxFdXyW/P+XcnUT+eskUQPLEOkDuO6MI8km/L/MIL+8pM5 rPAxB6p1lTJXKqh1ne1M8qdoCvOVvms/tFw6ZTQWuIwLnB3Aqp2WHGENdT+VP5uc2X2zst+xDrG 3Q1PIT6iJh4lfRksIUHAdyhB0oDzs9mia1kFQhdCQ+GmkZu94cv+UEb65dgmQ+5+93dPb6/eAzY IjHF+VJeLzNWBegCW2U9w4XVXDWCYLbigRnpKlKTpcQTtiHDgWQxitkXat1SEypeIkTB5qDJNG+ ExD2vU/Pay9KaxQKp7x9BkkBFqz7g== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.829500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: BBD090C5ECD942BC4A586DC9F9181C138D2C8BE75586C512F0FFFF14353E0B132000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240821_012938_931109_30F12C55 X-CRM114-Status: GOOD ( 15.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To support SMI clamp and reset operation in genpd callback, add SMI LARB reset register offset and mask related information in the bindings. Add index in mt8188-resets.h to query the register offset and mask in the SMI reset control driver. Signed-off-by: friday.yang --- .../bindings/reset/mediatek,smi-reset.yaml | 46 +++++++++++++++++++ include/dt-bindings/reset/mt8188-resets.h | 11 +++++ 2 files changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml new file mode 100644 index 000000000000..66ac121d2396 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2024 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mediatek,smi-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SMI Reset Controller + +maintainers: + - Friday Yang + +description: | + This reset controller node is used to perform reset management + of SMI larbs on MediaTek platform. It is used to implement various + reset functions required when SMI larbs apply clamp operation. + + For list of all valid reset indices see + for MT8188. + +properties: + compatible: + enum: + - mediatek,smi-reset-mt8188 + + "#reset-cells": + const: 1 + + mediatek,larb-rst-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle of the SMI larb's reset controller syscon. + +required: + - compatible + - "#reset-cells" + - mediatek,larb-rst-syscon + +additionalProperties: false + +examples: + - | + imgsys1_dip_top_rst: reset-controller { + compatible = "mediatek,smi-reset-mt8188"; + #reset-cells = <1>; + mediatek,larb-rst-syscon = <&imgsys1_dip_top>; + }; diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h index 5a58c54e7d20..387a4beac688 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -113,4 +113,15 @@ #define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52 #define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53 +#define MT8188_SMI_RST_LARB10 0 +#define MT8188_SMI_RST_LARB11A 1 +#define MT8188_SMI_RST_LARB11C 2 +#define MT8188_SMI_RST_LARB12 3 +#define MT8188_SMI_RST_LARB11B 4 +#define MT8188_SMI_RST_LARB15 5 +#define MT8188_SMI_RST_LARB16B 6 +#define MT8188_SMI_RST_LARB17B 7 +#define MT8188_SMI_RST_LARB16A 8 +#define MT8188_SMI_RST_LARB17A 9 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ From patchwork Wed Aug 21 08:26:50 2024 Content-Type: text/plain; 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Wed, 21 Aug 2024 16:29:02 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 21 Aug 2024 16:29:01 +0800 From: friday.yang To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Yong Wu , Philipp Zabel , Friday Yang , , , , , Subject: [PATCH 2/4] dt-bindings: memory: mediatek: Add smi-sub-common property for reset Date: Wed, 21 Aug 2024 16:26:50 +0800 Message-ID: <20240821082845.11792-3-friday.yang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240821082845.11792-1-friday.yang@mediatek.com> References: <20240821082845.11792-1-friday.yang@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240821_012939_459924_FB9E240E X-CRM114-Status: GOOD ( 11.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On the MediaTek platform, some SMI LARBs are directly linked to SMI common. While some SMI LARBs are linked to SMI sub common, then SMI sub common is linked to SMI common. Add 'mediatek,smi-sub-comm' and 'mediatek,smi-sub-comm-in-portid' properties here. The SMI reset driver could query which port of the SMI sub common the current LARB is linked to through the two properties. The hardware block diagram could be described as below. SMI Common(Smart Multimedia Interface Common) | +----------------+------- | | | | | | | | | | larb0 SMI Sub Common | | | larb1 larb2 larb3 Signed-off-by: friday.yang --- .../mediatek,smi-common.yaml | 2 ++ .../memory-controllers/mediatek,smi-larb.yaml | 22 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index 2f36ac23604c..4392d349878c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -39,6 +39,7 @@ properties: - mediatek,mt8186-smi-common - mediatek,mt8188-smi-common-vdo - mediatek,mt8188-smi-common-vpp + - mediatek,mt8188-smi-sub-common - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp @@ -107,6 +108,7 @@ allOf: compatible: contains: enum: + - mediatek,mt8188-smi-sub-common - mediatek,mt8195-smi-sub-common then: required: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 2381660b324c..5f162bb360db 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -69,6 +69,16 @@ properties: description: the hardware id of this larb. It's only required when this hardware id is not consecutive from its M4U point of view. + mediatek,smi-sub-comm: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle of smi_sub_common that the larb is linked to. + + mediatek,smi-sub-comm-in-portid: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: which port of smi_sub_common that the larb is linked to. + required: - compatible - reg @@ -125,6 +135,18 @@ allOf: required: - mediatek,larb-id + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8188-smi-larb + + then: + required: + - mediatek,smi-sub-comm + - mediatek,smi-sub-comm-in-portid + additionalProperties: false examples: From patchwork Wed Aug 21 08:26:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "friday.yang" X-Patchwork-Id: 13771067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8178AC52D7C for ; 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Wed, 21 Aug 2024 01:29:07 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 21 Aug 2024 16:29:03 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 21 Aug 2024 16:29:03 +0800 From: friday.yang To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Yong Wu , Philipp Zabel , Friday Yang , , , , , Subject: [PATCH 3/4] memory: mtk-smi: mt8188: Add SMI clamp function Date: Wed, 21 Aug 2024 16:26:51 +0800 Message-ID: <20240821082845.11792-4-friday.yang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240821082845.11792-1-friday.yang@mediatek.com> References: <20240821082845.11792-1-friday.yang@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.482200-8.000000 X-TMASE-MatchedRID: qyOEDd16wS2E9zgVMk3pXnTnOygHVQpO87QrIQgH3y1F/5XzBv3ecmb6 PphVtfZggq4Vy91HEnbNnEpSSaVatI+TOcasruGo4pdq9sdj8LVPZ8WbDkfxU1fgf8AdlMAqlwW f7/4SyDuPtZzz7myNFIHWmfha3tGBOFS6mDjLiboXrP0cYcrA27BH/AqZyGLZatnKjjjc99k5tO klY41M4eLzNWBegCW2wgn7iDBesS3CttcwYNipX/m+9AxIOjOGV/HftdBdiQBmannclipmDvTQG tuG7oobdoCwYb5UuHGw2l5oOHJT1I0Udt0diqcc5rOA98Lef1exB7i0mR6aGEKo4D0joJpIoydM lEjRcid9fBQSbWi4PMsNjEULX/uuMIFAPLUElJzAvpLE+mvX8g== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.482200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 449FE31E0D714008FC2534D99ACA70D873FDFA9471BBBD59F946CA86430E3BD92000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240821_012917_528647_A94B5302 X-CRM114-Status: GOOD ( 22.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In order to avoid handling glitch signal when MTCMOS on/off, SMI need clamp and reset operation. Parse power reset settings for LARBs which need to reset. Register genpd callback for SMI LARBs and apply reset operations in the callback. Signed-off-by: friday.yang --- drivers/memory/mtk-smi.c | 148 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 146 insertions(+), 2 deletions(-) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index fbe52ecc0eca..1ccd62a17b1d 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -10,11 +10,16 @@ #include #include #include +#include #include #include #include #include +#include #include +#include +#include +#include #include #include #include @@ -36,6 +41,13 @@ #define SMI_DCM 0x300 #define SMI_DUMMY 0x444 +#define SMI_COMMON_CLAMP_EN 0x3c0 +#define SMI_COMMON_CLAMP_EN_SET 0x3c4 +#define SMI_COMMON_CLAMP_EN_CLR 0x3c8 +#define SMI_COMMON_CLAMP_MASK(inport) BIT(inport) + +#define SMI_SUB_COMM_INPORT_NR (8) + /* SMI LARB */ #define SMI_LARB_SLP_CON 0xc #define SLP_PROT_EN BIT(0) @@ -150,6 +162,7 @@ struct mtk_smi { }; struct mtk_smi_larb { /* larb: local arbiter */ + struct device *dev; struct mtk_smi smi; void __iomem *base; struct device *smi_common_dev; /* common or sub-common dev */ @@ -157,6 +170,10 @@ struct mtk_smi_larb { /* larb: local arbiter */ int larbid; u32 *mmu; unsigned char *bank; + struct regmap *sub_comm_syscon; + int sub_comm_inport; + struct notifier_block nb; + struct reset_control *rst_con; }; static int @@ -472,6 +489,60 @@ static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb) writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); } +static int mtk_smi_larb_clamp_protect_enable(struct device *dev) +{ + struct mtk_smi_larb *larb = dev_get_drvdata(dev); + int ret; + + /* sub_comm_syscon could be NULL if larb directly linked to SMI common */ + if (!larb->sub_comm_syscon) + return -EINVAL; + + ret = regmap_write(larb->sub_comm_syscon, SMI_COMMON_CLAMP_EN_SET, + SMI_COMMON_CLAMP_MASK(larb->sub_comm_inport)); + if (ret) + dev_err(dev, "Unable to enable clamp, inport %d, ret %d\n", + larb->sub_comm_inport, ret); + + return ret; +} + +static int mtk_smi_larb_clamp_protect_disble(struct device *dev) +{ + struct mtk_smi_larb *larb = dev_get_drvdata(dev); + int ret; + + /* sub_comm_syscon could be NULL if larb directly linked to SMI common */ + if (!larb->sub_comm_syscon) + return -EINVAL; + + ret = regmap_write(larb->sub_comm_syscon, SMI_COMMON_CLAMP_EN_CLR, + SMI_COMMON_CLAMP_MASK(larb->sub_comm_inport)); + if (ret) + dev_err(dev, "Unable to disable clamp, inport %d, ret %d\n", + larb->sub_comm_inport, ret); + + return ret; +} + +static int mtk_smi_genpd_callback(struct notifier_block *nb, + unsigned long flags, void *data) +{ + struct mtk_smi_larb *larb = container_of(nb, struct mtk_smi_larb, nb); + struct device *dev = larb->dev; + + if (flags == GENPD_NOTIFY_PRE_ON || flags == GENPD_NOTIFY_PRE_OFF) { + /* disable related SMI sub-common port */ + mtk_smi_larb_clamp_protect_enable(dev); + } else if (flags == GENPD_NOTIFY_ON) { + /* enable related SMI sub-common port */ + reset_control_reset(larb->rst_con); + mtk_smi_larb_clamp_protect_disble(dev); + } + + return NOTIFY_OK; +} + static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) { struct platform_device *smi_com_pdev; @@ -528,6 +599,59 @@ static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, return ret; } +static int mtk_smi_larb_parse_clamp_info(struct mtk_smi_larb *larb) +{ + struct device *dev = larb->dev; + struct device_node *smi_node; + int ret; + + /* smi_node could be NULL if larb directly linked to SMI common */ + smi_node = of_parse_phandle(dev->of_node, "mediatek,smi-sub-comm", 0); + if (!smi_node) + return 0; + + larb->sub_comm_syscon = device_node_to_regmap(smi_node); + of_node_put(smi_node); + ret = of_property_read_u32(dev->of_node, + "mediatek,smi-sub-comm-in-portid", + &larb->sub_comm_inport); + + if (IS_ERR(larb->sub_comm_syscon) || ret || + larb->sub_comm_inport >= SMI_SUB_COMM_INPORT_NR) { + larb->sub_comm_syscon = NULL; + return -EINVAL; + } + + return 0; +} + +static int mtk_smi_larb_parse_reset_info(struct mtk_smi_larb *larb) +{ + struct device_node *reset_node; + struct device *dev = larb->dev; + int ret; + + /* only larb with "resets" need to get reset setting */ + reset_node = of_parse_phandle(dev->of_node, "resets", 0); + if (!reset_node) + return 0; + of_node_put(reset_node); + + larb->rst_con = devm_reset_control_get(dev, "larb_rst"); + if (IS_ERR(larb->rst_con)) + return dev_err_probe(dev, PTR_ERR(larb->rst_con), + "cannot get larb reset controller\n"); + + larb->nb.notifier_call = mtk_smi_genpd_callback; + ret = dev_pm_genpd_add_notifier(dev, &larb->nb); + if (ret) { + dev_err(dev, "Failed to add genpd callback %d\n", ret); + return -EINVAL; + } + + return 0; +} + static int mtk_smi_larb_probe(struct platform_device *pdev) { struct mtk_smi_larb *larb; @@ -538,6 +662,7 @@ static int mtk_smi_larb_probe(struct platform_device *pdev) if (!larb) return -ENOMEM; + larb->dev = dev; larb->larb_gen = of_device_get_match_data(dev); larb->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(larb->base)) @@ -554,15 +679,29 @@ static int mtk_smi_larb_probe(struct platform_device *pdev) if (ret < 0) return ret; - pm_runtime_enable(dev); + /* find sub common to clamp larb for ISP software reset */ + ret = mtk_smi_larb_parse_clamp_info(larb); + if (ret) { + dev_err(dev, "Failed to get clamp setting for larb\n"); + goto err_pm_disable; + } + + ret = mtk_smi_larb_parse_reset_info(larb); + if (ret) { + dev_err(dev, "Failed to get power setting for larb\n"); + goto err_pm_disable; + } + platform_set_drvdata(pdev, larb); ret = component_add(dev, &mtk_smi_larb_component_ops); if (ret) goto err_pm_disable; + + pm_runtime_enable(dev); + return 0; err_pm_disable: - pm_runtime_disable(dev); device_link_remove(dev, larb->smi_common_dev); return ret; } @@ -686,6 +825,10 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = { .init = mtk_smi_common_mt8195_init, }; +static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8188 = { + .type = MTK_SMI_GEN2_SUB_COMM, +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { .type = MTK_SMI_GEN2, .has_gals = true, @@ -729,6 +872,7 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo}, {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp}, + {.compatible = "mediatek,mt8188-smi-sub-common", .data = &mtk_smi_sub_common_mt8188}, {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, From patchwork Wed Aug 21 08:26:52 2024 Content-Type: text/plain; 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Wed, 21 Aug 2024 16:29:05 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 21 Aug 2024 16:29:05 +0800 From: friday.yang To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Yong Wu , Philipp Zabel , Friday Yang , , , , , Subject: [PATCH 4/4] reset: mediatek: Add reset control driver for SMI Date: Wed, 21 Aug 2024 16:26:52 +0800 Message-ID: <20240821082845.11792-5-friday.yang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240821082845.11792-1-friday.yang@mediatek.com> References: <20240821082845.11792-1-friday.yang@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240821_012940_763664_6FB1C761 X-CRM114-Status: GOOD ( 23.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a reset-controller driver for performing reset management of SMI LARBs on MediaTek platform. This driver uses the regmap frameworks to actually implement the various reset functions needed when SMI LARBs apply clamp operations. Signed-off-by: friday.yang --- drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-mediatek-smi.c | 152 +++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 drivers/reset/reset-mediatek-smi.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 67bce340a87e..e984a5a332f1 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -154,6 +154,15 @@ config RESET_MESON_AUDIO_ARB This enables the reset driver for Audio Memory Arbiter of Amlogic's A113 based SoCs +config RESET_MTK_SMI + bool "MediaTek SMI Reset Driver" + depends on MTK_SMI + help + This option enables the reset controller driver for MediaTek SMI. + This reset driver is responsible for managing the reset signals + for SMI larbs. Say Y if you want to control reset signals for + MediaTek SMI larbs. Otherwise, say N. + config RESET_NPCM bool "NPCM BMC Reset Driver" if COMPILE_TEST default ARCH_NPCM diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 27b0bbdfcc04..241777485b40 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o +obj-$(CONFIG_RESET_MTK_SMI) += reset-mediatek-smi.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o obj-$(CONFIG_RESET_NUVOTON_MA35D1) += reset-ma35d1.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o diff --git a/drivers/reset/reset-mediatek-smi.c b/drivers/reset/reset-mediatek-smi.c new file mode 100644 index 000000000000..ead747e80ad5 --- /dev/null +++ b/drivers/reset/reset-mediatek-smi.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Reset driver for MediaTek SMI module + * + * Copyright (C) 2024 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define to_mtk_smi_reset_data(_rcdev) \ + container_of(_rcdev, struct mtk_smi_reset_data, rcdev) + +struct mtk_smi_larb_reset { + unsigned int offset; + unsigned int value; +}; + +static const struct mtk_smi_larb_reset rst_signal_mt8188[] = { + [MT8188_SMI_RST_LARB10] = { 0xC, BIT(0) }, /* larb10 */ + [MT8188_SMI_RST_LARB11A] = { 0xC, BIT(0) }, /* larb11a */ + [MT8188_SMI_RST_LARB11C] = { 0xC, BIT(0) }, /* larb11c */ + [MT8188_SMI_RST_LARB12] = { 0xC, BIT(8) }, /* larb12 */ + [MT8188_SMI_RST_LARB11B] = { 0xC, BIT(0) }, /* larb11b */ + [MT8188_SMI_RST_LARB15] = { 0xC, BIT(0) }, /* larb15 */ + [MT8188_SMI_RST_LARB16B] = { 0xA0, BIT(4) }, /* larb16b */ + [MT8188_SMI_RST_LARB17B] = { 0xA0, BIT(4) }, /* larb17b */ + [MT8188_SMI_RST_LARB16A] = { 0xA0, BIT(4) }, /* larb16a */ + [MT8188_SMI_RST_LARB17A] = { 0xA0, BIT(4) }, /* larb17a */ +}; + +struct mtk_smi_larb_plat { + const struct mtk_smi_larb_reset *reset_signal; + const unsigned int larb_reset_nr; +}; + +struct mtk_smi_reset_data { + const struct mtk_smi_larb_plat *larb_plat; + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static const struct mtk_smi_larb_plat mtk_smi_larb_mt8188 = { + .reset_signal = rst_signal_mt8188, + .larb_reset_nr = ARRAY_SIZE(rst_signal_mt8188), +}; + +static int mtk_smi_larb_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct mtk_smi_reset_data *data = to_mtk_smi_reset_data(rcdev); + const struct mtk_smi_larb_plat *larb_plat = data->larb_plat; + const struct mtk_smi_larb_reset *larb_rst = larb_plat->reset_signal + id; + int ret; + + ret = regmap_set_bits(data->regmap, larb_rst->offset, larb_rst->value); + if (ret) + return ret; + ret = regmap_clear_bits(data->regmap, larb_rst->offset, larb_rst->value); + + return ret; +} + +static int mtk_smi_larb_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct mtk_smi_reset_data *data = to_mtk_smi_reset_data(rcdev); + const struct mtk_smi_larb_plat *larb_plat = data->larb_plat; + const struct mtk_smi_larb_reset *larb_rst = larb_plat->reset_signal + id; + int ret; + + ret = regmap_set_bits(data->regmap, larb_rst->offset, larb_rst->value); + if (ret) + dev_err(rcdev->dev, "[%s] Failed to shutdown larb %d\n", __func__, ret); + + return ret; +} + +static int mtk_smi_larb_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct mtk_smi_reset_data *data = to_mtk_smi_reset_data(rcdev); + const struct mtk_smi_larb_plat *larb_plat = data->larb_plat; + const struct mtk_smi_larb_reset *larb_rst = larb_plat->reset_signal + id; + int ret; + + ret = regmap_clear_bits(data->regmap, larb_rst->offset, larb_rst->value); + if (ret) + dev_err(rcdev->dev, "[%s] Failed to reopen larb %d\n", __func__, ret); + + return ret; +} + +static const struct reset_control_ops mtk_smi_reset_ops = { + .reset = mtk_smi_larb_reset, + .assert = mtk_smi_larb_reset_assert, + .deassert = mtk_smi_larb_reset_deassert, +}; + +static int mtk_smi_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct mtk_smi_larb_plat *larb_plat = of_device_get_match_data(dev); + struct device_node *np = dev->of_node, *reset_node; + struct mtk_smi_reset_data *data; + struct regmap *regmap; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + reset_node = of_parse_phandle(np, "mediatek,larb-rst-syscon", 0); + if (!reset_node) + return -EINVAL; + + regmap = device_node_to_regmap(reset_node); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + data->larb_plat = larb_plat; + data->regmap = regmap; + data->rcdev.owner = THIS_MODULE; + data->rcdev.ops = &mtk_smi_reset_ops; + data->rcdev.of_node = np; + data->rcdev.nr_resets = larb_plat->larb_reset_nr; + data->rcdev.dev = dev; + platform_set_drvdata(pdev, data); + + return devm_reset_controller_register(dev, &data->rcdev); +} + +static const struct of_device_id mtk_smi_larb_reset_of_match[] = { + { .compatible = "mediatek,smi-reset-mt8188", .data = &mtk_smi_larb_mt8188 }, + { }, +}; +MODULE_DEVICE_TABLE(of, mtk_smi_larb_reset_of_match); + +static struct platform_driver mtk_smi_reset_driver = { + .probe = mtk_smi_reset_probe, + .driver = { + .name = "mediatek-smi-reset", + .of_match_table = mtk_smi_larb_reset_of_match, + }, +}; +module_platform_driver(mtk_smi_reset_driver); + +MODULE_AUTHOR("Friday.Yang@mediatek.com"); +MODULE_DESCRIPTION("MediaTek SMI Reset Driver"); +MODULE_LICENSE("GPL");