From patchwork Wed Aug 21 12:43:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771364 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13300C52D6F for ; Wed, 21 Aug 2024 12:44:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EB6210E8E3; Wed, 21 Aug 2024 12:44:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ip3am3Uy"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D08610E8E3; Wed, 21 Aug 2024 12:44:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724244261; x=1755780261; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xBTBmpL924eHLaGaJlxfMEUf+QEa13q0knxeUnC7CKw=; b=ip3am3UyLOF8Bc+U59i2NZ3Po93pzRfgB56OkLMo7j2je8MVKlCsXvPu N2wkKKp6ehXpp4ADi33yCUnssju807J0471YKRHBQyLbDzrpj/lyqo8et 4+Cil6p5WPothqb6//6NjFElTPtLuNlwOW8KXtagH0abT/iaPlJToE35B IM+7nnfC9m8BkCzoH+Nh//+ls9XByfDCP5IhAVyLom6gJqJ4J9yo5gTBk Lzi3N/Vwqs+G+JE9T4SOfv4t0NoDkNpNHb8IJ6tmyOmM+cXNHkRHz2vLI m8eybXonmG6GA/w52+6JTZegQRVdIPIbBEshnwdyj52zunCnnUP6YlRrH w==; X-CSE-ConnectionGUID: hiVxoH59QPyh9o3jWDkvMg== X-CSE-MsgGUID: 405AoY1MQw2pq1uGDw5e0w== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="33754095" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="33754095" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:21 -0700 X-CSE-ConnectionGUID: ygyWBnM9RNaQYWZIj2LzRQ== X-CSE-MsgGUID: tIuPv35nRGuwjBKIvWvGqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="98554596" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:18 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 01/14] drm/i915/gt: Avoid using masked workaround for CCS_MODE setting Date: Wed, 21 Aug 2024 14:43:36 +0200 Message-ID: <20240821124349.295259-2-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" When setting the CCS mode, we mistakenly used wa_masked_en() to apply the workaround, which reads from the register and masks the existing value with the new one. Our intention was to write the value directly, without masking it. So far, this hasn't caused issues because we've been using a register value that only enables a single CCS engine, typically with an ID of '0'. However, in upcoming patches, we will be utilizing multiple engines, and it's crucial that we write the new value directly without any masking. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index bfe6d8fc820f..f3082fad3f45 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2745,7 +2745,7 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li * assign all slices to a single CCS. We will call it CCS mode 1 */ mode = intel_gt_apply_ccs_mode(gt); - wa_masked_en(wal, XEHP_CCS_MODE, mode); + wa_add(wal, XEHP_CCS_MODE, 0, mode, mode, false); } /* From patchwork Wed Aug 21 12:43:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CA83C52D7C for ; Wed, 21 Aug 2024 12:44:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 983EA10E8EB; Wed, 21 Aug 2024 12:44:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="N7FRJ9fr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2049010E8E9; Wed, 21 Aug 2024 12:44:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724244266; x=1755780266; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FQO02+IaMgU5e/1DOI4Cdpxg4Wv0yNleSCLQLCvWwsE=; b=N7FRJ9frWVTG72xZioEdZuSvgpEt2EjODgppTYT2Ju1ac3nEcAobgjnH 9ASaGYDPy0uiH+jxtxQi56JuMTs4/P4ZgJVWmgBdnkWvei33fNWF516De KmUzq+6E92JhwA3PsfBbxq38spW660ZTAVNVsKvcplprd6UvNVNtGkfSO 2e80/TJsHonmkIH92RFVt5sZY4PTr8eKVbkEThRptQRO9G85Oc8ueuguM Hhr3xl81h044mHKpy8citFs/JApO8d5Ng3/HZ/0k+MkxmYg+GNpxMVp82 y2XuOwmAEwR4nNIulixXe5dzlIX8rd+DQ280BAwJ1xqDJogN9yLOyw49Y Q==; X-CSE-ConnectionGUID: oByRm9Q4S7q7/E7bBpI9FQ== X-CSE-MsgGUID: Ul2Elu0mTyOC7P5AXuOvsg== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="33754107" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="33754107" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:26 -0700 X-CSE-ConnectionGUID: F+dDxM3sRYCoXRvJfPRsoQ== X-CSE-MsgGUID: wYVknkITQJCkdAmuT/qv1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="98554625" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:24 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 02/14] drm/i915/gt: Move the CCS mode variable to a global position Date: Wed, 21 Aug 2024 14:43:37 +0200 Message-ID: <20240821124349.295259-3-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Store the CCS mode value in the intel_gt->ccs structure to make it available for future instances that may need to change its value. Name it mode_reg_val because it holds the value that will be written into the CCS_MODE register, determining the CCS balancing and, consequently, the number of engines generated. No functional changes intended. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++ drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 16 +++++++++++----- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++-- 5 files changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index a6c69a706fd7..5af0527d822d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -18,6 +18,7 @@ #include "intel_ggtt_gmch.h" #include "intel_gt.h" #include "intel_gt_buffer_pool.h" +#include "intel_gt_ccs_mode.h" #include "intel_gt_clock_utils.h" #include "intel_gt_debugfs.h" #include "intel_gt_mcr.h" @@ -136,6 +137,8 @@ int intel_gt_init_mmio(struct intel_gt *gt) intel_sseu_info_init(gt); intel_gt_mcr_init(gt); + intel_gt_ccs_mode_init(gt); + return intel_engines_init_mmio(gt); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 3c62a44e9106..fcd07eb4728b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -8,15 +8,12 @@ #include "intel_gt_ccs_mode.h" #include "intel_gt_regs.h" -unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) +static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { int cslice; u32 mode = 0; int first_ccs = __ffs(CCS_MASK(gt)); - if (!IS_DG2(gt->i915)) - return 0; - /* Build the value for the fixed CCS load balancing */ for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { if (gt->ccs.cslices & BIT(cslice)) @@ -35,5 +32,14 @@ unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) XEHP_CCS_MODE_CSLICE_MASK); } - return mode; + gt->ccs.mode_reg_val = mode; +} + +void intel_gt_ccs_mode_init(struct intel_gt *gt) +{ + if (!IS_DG2(gt->i915)) + return; + + /* Initialize the CCS mode setting */ + intel_gt_apply_ccs_mode(gt); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 55547f2ff426..0f2506586a41 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -8,6 +8,6 @@ struct intel_gt; -unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); +void intel_gt_ccs_mode_init(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index bcee084b1f27..9e257f34d05b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -207,12 +207,23 @@ struct intel_gt { [MAX_ENGINE_INSTANCE + 1]; enum intel_submission_method submission_method; + /* + * Track fixed mapping between CCS engines and compute slices. + * + * In order to w/a HW that has the inability to dynamically load + * balance between CCS engines and EU in the compute slices, we have to + * reconfigure a static mapping on the fly. + * + * The mode variable is set by the user and sets the balancing mode, + * i.e. how the CCS streams are distributed amongs the slices. + */ struct { /* * Mask of the non fused CCS slices * to be used for the load balancing */ intel_engine_mask_t cslices; + u32 mode_reg_val; } ccs; /* diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index f3082fad3f45..f6135be3cd86 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2727,7 +2727,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt, static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct intel_gt *gt = engine->gt; - u32 mode; + u32 mode = gt->ccs.mode_reg_val; if (!IS_DG2(gt->i915)) return; @@ -2743,8 +2743,10 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li /* * After having disabled automatic load balancing we need to * assign all slices to a single CCS. We will call it CCS mode 1 + * + * The gt->ccs.mode_reg_val has already been set previously during + * initialization. */ - mode = intel_gt_apply_ccs_mode(gt); wa_add(wal, XEHP_CCS_MODE, 0, mode, mode, false); } From patchwork Wed Aug 21 12:43:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771366 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 57846C5320E for ; Wed, 21 Aug 2024 12:44:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCFD610E8EE; Wed, 21 Aug 2024 12:44:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LuFzLY4V"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6130310E8EC; Wed, 21 Aug 2024 12:44:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724244273; x=1755780273; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YrKtZxB3WtJA+8EOP8lPzPl2frauHQX7GdEMywmof5g=; b=LuFzLY4VHGxz7Vw/l2mtQZIewqJuFsxH8XIIY2mMNjEsgVGbzHv75CEF pFGFih1ImcHOJAzH6xgJdmuZAfqB8xC/0tdi/mTQ52DfyGv7VWNJw6tX4 UGVtU/8IOzeCvV4QdgDiuYngMpkxoH3rHPiAvkBoESX9CJtEsNQwErFU/ ThouU4yKK42qKGmu58gkeAEqOe9aY4wcnuQ2FquyEkZI7aR4u1fCLnn7T FJy9NlCTFagqg9hD+BPJFnCpUlcIu13Ym1ezp74XjLfeRdBj9f0WAV5Pi W9nHxrQuZfLPaTfaBz6oKjgLEnifpM//eu+pHLBmmeNzeeVcHkYiA97B7 w==; X-CSE-ConnectionGUID: kiR17oMTT8yYTvYY9OAS9A== X-CSE-MsgGUID: Uurrise6TDeWpxWSstLaSQ== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="33754110" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="33754110" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:33 -0700 X-CSE-ConnectionGUID: ZECz76lkRHe24fz4TwBaow== X-CSE-MsgGUID: A0tX2KSCSWKkpchCBg36oQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="98554672" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:30 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 03/14] drm/i915/gt: Allow the creation of multi-mode CCS masks Date: Wed, 21 Aug 2024 14:43:38 +0200 Message-ID: <20240821124349.295259-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Until now, we have only set CCS mode balancing to 1, which means that only one compute engine is exposed to the user. The stream of compute commands submitted to that engine is then shared among all the dedicated execution units. This is done by calling the 'intel_gt_apply_ccs_mode(); function. With this change, the aforementioned function takes an additional parameter called 'mode' that specifies the desired mode to be set for the CCS engines balancing. The mode parameter can have the following values: - mode = 0: CCS load balancing mode 1 (1 CCS engine exposed) - mode = 1: CCS load balancing mode 2 (2 CCS engines exposed) - mode = 3: CCS load balancing mode 4 (4 CCS engines exposed) This allows us to generate the appropriate register value to be written to CCS_MODE, configuring how the exposed engine streams will be submitted to the execution units. No functional changes are intended yet, as no mode higher than '0' is currently being set. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 80 +++++++++++++++++---- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- 2 files changed, 67 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index fcd07eb4728b..5ca36985bdd7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -4,35 +4,87 @@ */ #include "i915_drv.h" -#include "intel_gt.h" #include "intel_gt_ccs_mode.h" #include "intel_gt_regs.h" static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { + unsigned long cslices_mask = gt->ccs.cslices; + u32 mode_val = 0; + /* CCS mode, i.e. number of CCS engines to be enabled */ + u32 width = 1; + /* CCS engine id, i.e. the engines position in the engine's bitmask */ + int engine; int cslice; - u32 mode = 0; - int first_ccs = __ffs(CCS_MASK(gt)); - /* Build the value for the fixed CCS load balancing */ + /* + * The mode has two bit dedicated for each engine + * that will be used for the CCS balancing algorithm: + * + * BIT | CCS slice + * ------------------ + * 0 | CCS slice + * 1 | 0 + * ------------------ + * 2 | CCS slice + * 3 | 1 + * ------------------ + * 4 | CCS slice + * 5 | 2 + * ------------------ + * 6 | CCS slice + * 7 | 3 + * ------------------ + * + * When a CCS slice is not available, then we will write 0x7, + * oterwise we will write the user engine id which load will + * be forwarded to that slice. + * + * The possible configurations are: + * + * 1 engine (ccs0): + * slice 0, 1, 2, 3: ccs0 + * + * 2 engines (ccs0, ccs1): + * slice 0, 2: ccs0 + * slice 1, 3: ccs1 + * + * 4 engines (ccs0, ccs1, ccs2, ccs3): + * slice 0: ccs0 + * slice 1: ccs1 + * slice 2: ccs2 + * slice 3: ccs3 + */ + engine = __ffs(cslices_mask); + for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { - if (gt->ccs.cslices & BIT(cslice)) + if (!(cslices_mask & BIT(cslice))) { /* - * If available, assign the cslice - * to the first available engine... + * If not available, mark the slice as unavailable + * and no task will be dispatched here. */ - mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs); + mode_val |= XEHP_CCS_MODE_CSLICE(cslice, + XEHP_CCS_MODE_CSLICE_MASK); + continue; + } + + mode_val |= XEHP_CCS_MODE_CSLICE(cslice, engine); - else + if (!width) { /* - * ... otherwise, mark the cslice as - * unavailable if no CCS dispatches here + * CCS mode, will be used later to + * reset to a flexible value */ - mode |= XEHP_CCS_MODE_CSLICE(cslice, - XEHP_CCS_MODE_CSLICE_MASK); + width = 1; + engine = __ffs(cslices_mask); + continue; + } + + width--; + engine = find_next_bit(&cslices_mask, I915_MAX_CCS, engine + 1); } - gt->ccs.mode_reg_val = mode; + gt->ccs.mode_reg_val = mode_val; } void intel_gt_ccs_mode_init(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 0f2506586a41..4a6763b95a78 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -6,7 +6,7 @@ #ifndef __INTEL_GT_CCS_MODE_H__ #define __INTEL_GT_CCS_MODE_H__ -struct intel_gt; +#include "intel_gt.h" void intel_gt_ccs_mode_init(struct intel_gt *gt); From patchwork Wed Aug 21 12:43:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EF2EC52D6F for ; Wed, 21 Aug 2024 12:44:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 171D610E8E9; Wed, 21 Aug 2024 12:44:40 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bR4MWiBG"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id D838610E8E9; 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21 Aug 2024 05:44:39 -0700 X-CSE-ConnectionGUID: 0DWny4H+TSeh/nvLMIKkzg== X-CSE-MsgGUID: GZLH86ncTni2fBlvT6bkjQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="98554709" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:36 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 04/14] drm/i915/gt: Refactor uabi engine class/instance list creation Date: Wed, 21 Aug 2024 14:43:39 +0200 Message-ID: <20240821124349.295259-5-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For the upcoming changes we need a cleaner way to build the list of uabi engines. Suggested-by: Tvrtko Ursulin Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 ++++++++++++--------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 833987015b8b..11cc06c0c785 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -203,7 +203,7 @@ static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 void intel_engines_driver_register(struct drm_i915_private *i915) { - u16 name_instance, other_instance = 0; + u16 class_instance[I915_LAST_UABI_ENGINE_CLASS + 2] = { }; struct legacy_ring ring = {}; struct list_head *it, *next; struct rb_node **p, *prev; @@ -214,6 +214,8 @@ void intel_engines_driver_register(struct drm_i915_private *i915) prev = NULL; p = &i915->uabi_engines.rb_node; list_for_each_safe(it, next, &engines) { + u16 uabi_class; + struct intel_engine_cs *engine = container_of(it, typeof(*engine), uabi_list); @@ -222,15 +224,14 @@ void intel_engines_driver_register(struct drm_i915_private *i915) GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes)); engine->uabi_class = uabi_classes[engine->class]; - if (engine->uabi_class == I915_NO_UABI_CLASS) { - name_instance = other_instance++; - } else { - GEM_BUG_ON(engine->uabi_class >= - ARRAY_SIZE(i915->engine_uabi_class_count)); - name_instance = - i915->engine_uabi_class_count[engine->uabi_class]++; - } - engine->uabi_instance = name_instance; + + if (engine->uabi_class == I915_NO_UABI_CLASS) + uabi_class = I915_LAST_UABI_ENGINE_CLASS + 1; + else + uabi_class = engine->uabi_class; + + GEM_BUG_ON(uabi_class >= ARRAY_SIZE(class_instance)); + engine->uabi_instance = class_instance[uabi_class]++; /* * Replace the internal name with the final user and log facing @@ -238,11 +239,15 @@ void intel_engines_driver_register(struct drm_i915_private *i915) */ engine_rename(engine, intel_engine_class_repr(engine->class), - name_instance); + engine->uabi_instance); - if (engine->uabi_class == I915_NO_UABI_CLASS) + if (uabi_class > I915_LAST_UABI_ENGINE_CLASS) continue; + GEM_BUG_ON(uabi_class >= + ARRAY_SIZE(i915->engine_uabi_class_count)); + i915->engine_uabi_class_count[uabi_class]++; + rb_link_node(&engine->uabi_node, prev, p); rb_insert_color(&engine->uabi_node, &i915->uabi_engines); From patchwork Wed Aug 21 12:43:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771368 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A87FC52D7C for ; Wed, 21 Aug 2024 12:44:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 94EFA10E8EF; Wed, 21 Aug 2024 12:44:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nwK53u43"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id A046A10E8EF; Wed, 21 Aug 2024 12:44:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724244286; x=1755780286; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yuoaLHogE4J+aURd0F0ixJHZ0d7OeyV5+5WmcIZgjYY=; b=nwK53u43nFUcgouz6uEAbM+FGXdByGdqbeWDBAkUvCOerqjHdhoFtIUm qYJJtKo9JswDmP74ALjeGPcYrgpuThDV8c0gvCSDN/mlkQnQ/TNhJ3ga6 uFi8F0rSXEp1APNoK+mbSUDWEro9aaRV9a4ep8klMpI8riYqDr47HEvh+ UeshT0XJLvj3gAO00f9l0JnOT5zoD66H+YaLZxVau02IcBJJq31izMp/6 i4g3/ZIpZ3tFRqBdAVhEIhoBimWuP7+dQsoQTANLEk5lcNXZBobFw8O1F bKrOqDswzB9kF/e7YgnpGZjQUs1oAfYPZT/sYSrUn4oKJ1GHu9FrBRBJQ g==; X-CSE-ConnectionGUID: 2yGNibGkSRu7dkwS/R5d1Q== X-CSE-MsgGUID: b1Wk43kIR12dK+o0sWe16A== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="26395338" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="26395338" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:46 -0700 X-CSE-ConnectionGUID: or2kBA4BQ1O7QRYVllLatQ== X-CSE-MsgGUID: ZX15gCu/RHCQH0qbKdQS8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="66038640" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:43 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 05/14] drm/i915/gem: Mark and verify UABI engine validity Date: Wed, 21 Aug 2024 14:43:40 +0200 Message-ID: <20240821124349.295259-6-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Mark engines as invalid when they are not added to the UABI list to prevent accidental assignment of batch buffers. Currently, this change is mostly precautionary with minimal impact. However, in the future, when CCS engines will be dynamically added and removed by the user, this mechanism will be used for determining engine validity. Signed-off-by: Andi Shyti --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 28 +++++++++++++++++-- drivers/gpu/drm/i915/gt/intel_engine_user.c | 9 ++++-- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c58290274f97..770875e72056 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2682,6 +2682,22 @@ eb_select_legacy_ring(struct i915_execbuffer *eb) return user_ring_map[user_ring_id]; } +static bool engine_valid(struct intel_context *ce) +{ + if (!intel_engine_is_virtual(ce->engine)) + return !RB_EMPTY_NODE(&ce->engine->uabi_node); + + /* + * TODO: check virtual sibilings; we need to walk through all the + * virtual engines and ask whether the physical engine where it is based + * is still valid. For each of them we need to check with + * RB_EMPTY_NODE(...) + * + * This can be a placed in a new ce_ops. + */ + return true; +} + static int eb_select_engine(struct i915_execbuffer *eb) { @@ -2712,8 +2728,6 @@ eb_select_engine(struct i915_execbuffer *eb) eb->num_batches = ce->parallel.number_children + 1; gt = ce->engine->gt; - for_each_child(ce, child) - intel_context_get(child); eb->wakeref = intel_gt_pm_get(ce->engine->gt); /* * Keep GT0 active on MTL so that i915_vma_parked() doesn't @@ -2722,6 +2736,16 @@ eb_select_engine(struct i915_execbuffer *eb) if (gt->info.id) eb->wakeref_gt0 = intel_gt_pm_get(to_gt(gt->i915)); + /* We need to hold the wakeref to stabilize i915->uabi_engines */ + if (!engine_valid(ce)) { + intel_context_put(ce); + err = -ENODEV; + goto err; + } + + for_each_child(ce, child) + intel_context_get(child); + if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { err = intel_context_alloc_state(ce); if (err) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 11cc06c0c785..cd7662b1ad59 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -220,7 +220,7 @@ void intel_engines_driver_register(struct drm_i915_private *i915) container_of(it, typeof(*engine), uabi_list); if (intel_gt_has_unrecoverable_error(engine->gt)) - continue; /* ignore incomplete engines */ + goto clear_node_continue; /* ignore incomplete engines */ GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes)); engine->uabi_class = uabi_classes[engine->class]; @@ -242,7 +242,7 @@ void intel_engines_driver_register(struct drm_i915_private *i915) engine->uabi_instance); if (uabi_class > I915_LAST_UABI_ENGINE_CLASS) - continue; + goto clear_node_continue; GEM_BUG_ON(uabi_class >= ARRAY_SIZE(i915->engine_uabi_class_count)); @@ -260,6 +260,11 @@ void intel_engines_driver_register(struct drm_i915_private *i915) prev = &engine->uabi_node; p = &prev->rb_right; + + continue; + +clear_node_continue: + RB_CLEAR_NODE(&engine->uabi_node); } if (IS_ENABLED(CONFIG_DRM_I915_SELFTESTS) && From patchwork Wed Aug 21 12:43:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 896F9C52D7C for ; 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X-CSE-ConnectionGUID: Gh8sSniBRiG8k01jjzmtYw== X-CSE-MsgGUID: 8ygUQWgVQmyDKLeukQ+KhA== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="26395350" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="26395350" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:53 -0700 X-CSE-ConnectionGUID: mNk4AO97TSCmBPw8bxFFVw== X-CSE-MsgGUID: lFL1a1Z0Q9eJPplXD6M7Zg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="66038676" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:49 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 06/14] drm/i915/gt: Introduce for_each_enabled_engine() and apply it in selftests Date: Wed, 21 Aug 2024 14:43:41 +0200 Message-ID: <20240821124349.295259-7-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Selftests should run only on enabled engines, as disabled engines are not intended for use. A practical example is when, on DG2 machines, the user chooses to utilize only one CCS stream instead of all four. To address this, introduce the for_each_enabled_engine() loop, which will skip engines when they are marked as RB_EMPTY. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt.h | 12 +++++ drivers/gpu/drm/i915/gt/selftest_context.c | 6 +-- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 4 +- .../drm/i915/gt/selftest_engine_heartbeat.c | 6 +-- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 6 +-- drivers/gpu/drm/i915/gt/selftest_execlists.c | 52 +++++++++---------- drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 22 ++++---- drivers/gpu/drm/i915/gt/selftest_lrc.c | 18 +++---- drivers/gpu/drm/i915/gt/selftest_mocs.c | 6 +-- drivers/gpu/drm/i915/gt/selftest_rc6.c | 4 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 8 +-- .../drm/i915/gt/selftest_ring_submission.c | 2 +- drivers/gpu/drm/i915/gt/selftest_rps.c | 14 ++--- drivers/gpu/drm/i915/gt/selftest_timeline.c | 14 ++--- drivers/gpu/drm/i915/gt/selftest_tlb.c | 2 +- .../gpu/drm/i915/gt/selftest_workarounds.c | 14 ++--- 17 files changed, 102 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 998ca029b73a..1c52db1b5e25 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -188,6 +188,18 @@ int intel_gt_tiles_init(struct drm_i915_private *i915); (id__)++) \ for_each_if ((engine__) = (gt__)->engine[(id__)]) +/* + * Iterator over all initialized and enabled engines. Some engines, like CCS, + * may be "disabled" (i.e., not exposed to the user). Disabling is indicated + * by marking the rb_node as empty. + */ +#define for_each_enabled_engine(engine__, gt__, id__) \ + for ((id__) = 0; \ + (id__) < I915_NUM_ENGINES; \ + (id__)++) \ + for_each_if ( ((engine__) = (gt__)->engine[(id__)]) && \ + (!RB_EMPTY_NODE(&(engine__)->uabi_node)) ) + /* Iterator over subset of engines selected by mask */ #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c index 5eb46700dc4e..9976e231248d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_context.c +++ b/drivers/gpu/drm/i915/gt/selftest_context.c @@ -157,7 +157,7 @@ static int live_context_size(void *arg) * HW tries to write past the end of one. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct file *saved; if (!engine->context_size) @@ -311,7 +311,7 @@ static int live_active_context(void *arg) enum intel_engine_id id; int err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = __live_active_context(engine); if (err) break; @@ -424,7 +424,7 @@ static int live_remote_context(void *arg) enum intel_engine_id id; int err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = __live_remote_context(engine); if (err) break; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c index 5ffa5e30f419..038723a401df 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c @@ -142,7 +142,7 @@ static int perf_mi_bb_start(void *arg) return 0; wakeref = perf_begin(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce = engine->kernel_context; struct i915_vma *batch; u32 cycles[COUNT]; @@ -270,7 +270,7 @@ static int perf_mi_noop(void *arg) return 0; wakeref = perf_begin(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce = engine->kernel_context; struct i915_vma *base, *nop; u32 cycles[COUNT]; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c index 9e4f0e417b3b..74d4c2dc69cf 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c @@ -160,7 +160,7 @@ static int live_idle_flush(void *arg) /* Check that we can flush the idle barriers */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { st_engine_heartbeat_disable(engine); err = __live_idle_pulse(engine, intel_engine_flush_barriers); st_engine_heartbeat_enable(engine); @@ -180,7 +180,7 @@ static int live_idle_pulse(void *arg) /* Check that heartbeat pulses flush the idle barriers */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { st_engine_heartbeat_disable(engine); err = __live_idle_pulse(engine, intel_engine_pulse); st_engine_heartbeat_enable(engine); @@ -246,7 +246,7 @@ static int live_heartbeat_off(void *arg) if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (!intel_engine_has_preemption(engine)) continue; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index 10e556a7eac4..1da3bddbf02e 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -203,7 +203,7 @@ static int live_engine_timestamps(void *arg) if (GRAPHICS_VER(gt->i915) < 8) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { int err; st_engine_heartbeat_disable(engine); @@ -257,7 +257,7 @@ static int live_engine_busy_stats(void *arg) return -ENOMEM; GEM_BUG_ON(intel_gt_pm_is_awake(gt)); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; ktime_t busyness, dummy; ktime_t de, dt; @@ -363,7 +363,7 @@ static int live_engine_pm(void *arg) } GEM_BUG_ON(intel_gt_pm_is_awake(gt)); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { const typeof(*igt_atomic_phases) *p; for (p = igt_atomic_phases; p->name; p++) { diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c index 4202df5b8c12..4179f9c0d650 100644 --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c @@ -120,7 +120,7 @@ static int live_sanitycheck(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; struct i915_request *rq; @@ -177,7 +177,7 @@ static int live_unlite_restore(struct intel_gt *gt, int prio) return err; err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce[2] = {}; struct i915_request *rq[2]; struct igt_live_test t; @@ -339,7 +339,7 @@ static int live_unlite_ring(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce[2] = {}; struct i915_request *rq; struct igt_live_test t; @@ -488,7 +488,7 @@ static int live_pin_rewind(void *arg) * To simulate this, let's apply a bit of deliberate sabotague. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; struct i915_request *rq; struct intel_ring *ring; @@ -596,7 +596,7 @@ static int live_hold_reset(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; struct i915_request *rq; @@ -703,7 +703,7 @@ static int live_error_interrupt(void *arg) if (!intel_has_reset_engine(gt)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { const struct error_phase *p; int err = 0; @@ -938,7 +938,7 @@ slice_semaphore_queue(struct intel_engine_cs *outer, if (IS_ERR(head)) return PTR_ERR(head); - for_each_engine(engine, outer->gt, id) { + for_each_enabled_engine(engine, outer->gt, id) { if (!intel_engine_has_preemption(engine)) continue; @@ -1018,7 +1018,7 @@ static int live_timeslice_preempt(void *arg) if (err) goto err_pin; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (!intel_engine_has_preemption(engine)) continue; @@ -1124,7 +1124,7 @@ static int live_timeslice_rewind(void *arg) if (!CONFIG_DRM_I915_TIMESLICE_DURATION) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { enum { A1, A2, B1 }; enum { X = 1, Z, Y }; struct i915_request *rq[3] = {}; @@ -1325,7 +1325,7 @@ static int live_timeslice_queue(void *arg) if (err) goto err_pin; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct i915_request *rq, *nop; @@ -1425,7 +1425,7 @@ static int live_timeslice_nopreempt(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; struct i915_request *rq; unsigned long timeslice; @@ -1578,7 +1578,7 @@ static int live_busywait_preempt(void *arg) if (err) goto err_vma; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *lo, *hi; struct igt_live_test t; u32 *cs; @@ -1754,7 +1754,7 @@ static int live_preempt(void *arg) if (igt_spinner_init(&spin_lo, gt)) goto err_spin_hi; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct igt_live_test t; struct i915_request *rq; @@ -1847,7 +1847,7 @@ static int live_late_preempt(void *arg) /* Make sure ctx_lo stays before ctx_hi until we trigger preemption. */ ctx_lo->sched.priority = 1; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct igt_live_test t; struct i915_request *rq; @@ -1969,7 +1969,7 @@ static int live_nopreempt(void *arg) goto err_client_a; b.ctx->sched.priority = I915_PRIORITY_MAX; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq_a, *rq_b; if (!intel_engine_has_preemption(engine)) @@ -2396,7 +2396,7 @@ static int live_preempt_cancel(void *arg) if (preempt_client_init(gt, &data.b)) goto err_client_a; - for_each_engine(data.engine, gt, id) { + for_each_enabled_engine(data.engine, gt, id) { if (!intel_engine_has_preemption(data.engine)) continue; @@ -2463,7 +2463,7 @@ static int live_suppress_self_preempt(void *arg) if (preempt_client_init(gt, &b)) goto err_client_a; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq_a, *rq_b; int depth; @@ -2570,7 +2570,7 @@ static int live_chain_preempt(void *arg) if (preempt_client_init(gt, &lo)) goto err_client_hi; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct igt_live_test t; struct i915_request *rq; @@ -2928,7 +2928,7 @@ static int live_preempt_ring(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { int n; if (!intel_engine_has_preemption(engine)) @@ -2971,7 +2971,7 @@ static int live_preempt_gang(void *arg) * high priority levels into execution order. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq = NULL; struct igt_live_test t; IGT_TIMEOUT(end_time); @@ -3277,7 +3277,7 @@ static int live_preempt_user(void *arg) return PTR_ERR(result); } - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *client[3] = {}; struct igt_live_test t; int i; @@ -3393,7 +3393,7 @@ static int live_preempt_timeout(void *arg) if (igt_spinner_init(&spin_lo, gt)) goto err_ctx_lo; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { unsigned long saved_timeout; struct i915_request *rq; @@ -3567,7 +3567,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) memset(arg, 0, I915_NUM_ENGINES * sizeof(*arg)); - for_each_engine(engine, smoke->gt, id) { + for_each_enabled_engine(engine, smoke->gt, id) { arg[id] = *smoke; arg[id].engine = engine; if (!(flags & BATCH)) @@ -3585,7 +3585,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) } count = 0; - for_each_engine(engine, smoke->gt, id) { + for_each_enabled_engine(engine, smoke->gt, id) { if (IS_ERR_OR_NULL(worker[id])) continue; @@ -3613,7 +3613,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags) count = 0; do { - for_each_engine(smoke->engine, smoke->gt, id) { + for_each_enabled_engine(smoke->engine, smoke->gt, id) { struct i915_gem_context *ctx = smoke_context(smoke); int err; @@ -3876,7 +3876,7 @@ static int live_virtual_engine(void *arg) if (intel_uc_uses_guc_submission(>->uc)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = nop_virtual_engine(gt, &engine, 1, 1, 0); if (err) { pr_err("Failed to wrap engine %s: err=%d\n", diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c index 33351deeea4f..ddc4b5623f19 100644 --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c @@ -95,7 +95,7 @@ static int live_gt_clocks(void *arg) wakeref = intel_gt_pm_get(gt); intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { u32 cycles; u32 expected; u64 time; diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 9ce8ff1c04fe..1bfdb7a80334 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -296,7 +296,7 @@ static int igt_hang_sanitycheck(void *arg) if (err) return err; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_wedge_me w; long timeout; @@ -360,7 +360,7 @@ static int igt_reset_nop(void *arg) reset_count = i915_reset_count(global); count = 0; do { - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; int i; @@ -433,7 +433,7 @@ static int igt_reset_nop_engine(void *arg) if (!intel_has_reset_engine(gt)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { unsigned int reset_count, reset_engine_count, count; struct intel_context *ce; IGT_TIMEOUT(end_time); @@ -553,7 +553,7 @@ static int igt_reset_fail_engine(void *arg) if (!intel_has_reset_engine(gt)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { unsigned int count; struct intel_context *ce; IGT_TIMEOUT(end_time); @@ -700,7 +700,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) return err; } - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { unsigned int reset_count, reset_engine_count; unsigned long count; bool using_guc = intel_engine_uses_guc(engine); @@ -990,7 +990,7 @@ static int __igt_reset_engines(struct intel_gt *gt, if (!threads) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { unsigned long device = i915_reset_count(global); unsigned long count = 0, reported; bool using_guc = intel_engine_uses_guc(engine); @@ -1010,7 +1010,7 @@ static int __igt_reset_engines(struct intel_gt *gt, } memset(threads, 0, sizeof(*threads) * I915_NUM_ENGINES); - for_each_engine(other, gt, tmp) { + for_each_enabled_engine(other, gt, tmp) { struct kthread_worker *worker; threads[tmp].resets = @@ -1185,7 +1185,7 @@ static int __igt_reset_engines(struct intel_gt *gt, } unwind: - for_each_engine(other, gt, tmp) { + for_each_enabled_engine(other, gt, tmp) { int ret; if (!threads[tmp].worker) @@ -1621,7 +1621,7 @@ static int wait_for_others(struct intel_gt *gt, struct intel_engine_cs *engine; enum intel_engine_id id; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (engine == exclude) continue; @@ -1649,7 +1649,7 @@ static int igt_reset_queue(void *arg) if (err) goto unlock; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_selftest_saved_policy saved; struct i915_request *prev; IGT_TIMEOUT(end_time); @@ -1982,7 +1982,7 @@ static int igt_reset_engines_atomic(void *arg) struct intel_engine_cs *engine; enum intel_engine_id id; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = igt_atomic_reset_engine(engine, p); if (err) goto out; diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index e17b8777d21d..fa786b9eab8d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -171,7 +171,7 @@ static int live_lrc_layout(void *arg) GEM_BUG_ON(offset_in_page(lrc)); err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { u32 *hw; int dw; @@ -294,7 +294,7 @@ static int live_lrc_fixed(void *arg) * the context image. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { const struct { u32 reg; u32 offset; @@ -516,7 +516,7 @@ static int live_lrc_state(void *arg) if (IS_ERR(scratch)) return PTR_ERR(scratch); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = __live_lrc_state(engine, scratch); if (err) break; @@ -710,7 +710,7 @@ static int live_lrc_gpr(void *arg) if (IS_ERR(scratch)) return PTR_ERR(scratch); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { st_engine_heartbeat_disable(engine); err = __live_lrc_gpr(engine, scratch, false); @@ -867,7 +867,7 @@ static int live_lrc_timestamp(void *arg) * with a second request (carrying more poison into the timestamp). */ - for_each_engine(data.engine, gt, id) { + for_each_enabled_engine(data.engine, gt, id) { int i, err = 0; st_engine_heartbeat_disable(data.engine); @@ -1525,7 +1525,7 @@ static int live_lrc_isolation(void *arg) * context image and attempt to modify that list from a remote context. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { int i; /* Just don't even ask */ @@ -1713,7 +1713,7 @@ static int lrc_wabb_ctx(void *arg, bool per_ctx) enum intel_engine_id id; int err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { intel_engine_pm_get(engine); err = __lrc_wabb_ctx(engine, per_ctx); intel_engine_pm_put(engine); @@ -1849,7 +1849,7 @@ static int live_lrc_garbage(void *arg) if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { I915_RND_STATE(prng); int err = 0, i; @@ -1951,7 +1951,7 @@ static int live_pphwsp_runtime(void *arg) * is monotonic. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = __live_pphwsp_runtime(engine); if (err) break; diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index d73e438fb85f..6fd9fb0cd9f6 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -271,7 +271,7 @@ static int live_mocs_kernel(void *arg) if (err) return err; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { intel_engine_pm_get(engine); err = check_mocs_engine(&mocs, engine->kernel_context); intel_engine_pm_put(engine); @@ -297,7 +297,7 @@ static int live_mocs_clean(void *arg) if (err) return err; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; ce = mocs_context_create(engine); @@ -400,7 +400,7 @@ static int live_mocs_reset(void *arg) return err; igt_global_reset_lock(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { bool using_guc = intel_engine_uses_guc(engine); struct intel_selftest_saved_policy saved; struct intel_context *ce; diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c index 1aa1446c8fb0..ad60103c90a2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -165,7 +165,7 @@ randomised_engines(struct intel_gt *gt, int n; n = 0; - for_each_engine(engine, gt, id) + for_each_enabled_engine(engine, gt, id) n++; if (!n) return NULL; @@ -175,7 +175,7 @@ randomised_engines(struct intel_gt *gt, return NULL; n = 0; - for_each_engine(engine, gt, id) + for_each_enabled_engine(engine, gt, id) engines[n++] = engine; i915_prandom_shuffle(engines, sizeof(*engines), n, prng); diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c index 2cfc23c58e90..548e00ec47bd 100644 --- a/drivers/gpu/drm/i915/gt/selftest_reset.c +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c @@ -55,7 +55,7 @@ __igt_reset_stolen(struct intel_gt *gt, if (err) goto err_lock; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; struct i915_request *rq; @@ -113,7 +113,7 @@ __igt_reset_stolen(struct intel_gt *gt, if (mask == ALL_ENGINES) { intel_gt_reset(gt, mask, NULL); } else { - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (mask & engine->mask) intel_engine_reset(engine, NULL); } @@ -197,7 +197,7 @@ static int igt_reset_engines_stolen(void *arg) if (!intel_has_reset_engine(gt)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = __igt_reset_stolen(gt, engine->mask, engine->name); if (err) return err; @@ -326,7 +326,7 @@ static int igt_atomic_engine_reset(void *arg) if (!igt_force_reset(gt)) goto out_unlock; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct tasklet_struct *t = &engine->sched_engine->tasklet; if (t->func) diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c index 87ceb0f374b6..a447fec027e1 100644 --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c @@ -259,7 +259,7 @@ static int live_ctx_switch_wa(void *arg) * and equally important it was wasn't run when we don't! */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_vma *saved_wa; int err; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index dcef8d498919..49f23d19bd70 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -242,7 +242,7 @@ int live_rps_clock_interval(void *arg) intel_gt_check_clock_frequency(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; u32 cycles; u64 dt; @@ -401,7 +401,7 @@ int live_rps_control(void *arg) rps->work.func = dummy_rps_work; wakeref = intel_gt_pm_get(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; ktime_t min_dt, max_dt; int f, limit; @@ -629,7 +629,7 @@ int live_rps_frequency_cs(void *arg) saved_work = rps->work.func; rps->work.func = dummy_rps_work; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; struct i915_vma *vma; u32 *cancel, *cntr; @@ -768,7 +768,7 @@ int live_rps_frequency_srm(void *arg) saved_work = rps->work.func; rps->work.func = dummy_rps_work; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; struct i915_vma *vma; u32 *cancel, *cntr; @@ -1051,7 +1051,7 @@ int live_rps_interrupt(void *arg) saved_work = rps->work.func; rps->work.func = dummy_rps_work; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { /* Keep the engine busy with a spinner; expect an UP! */ if (pm_events & GEN6_PM_RP_UP_THRESHOLD) { intel_gt_pm_wait_for_idle(engine->gt); @@ -1157,7 +1157,7 @@ int live_rps_power(void *arg) saved_work = rps->work.func; rps->work.func = dummy_rps_work; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; struct { u64 power; @@ -1259,7 +1259,7 @@ int live_rps_dynamic(void *arg) if (intel_rps_uses_timer(rps)) pr_info("RPS has timer support\n"); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; struct { ktime_t dt; diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c index fa36cf920bde..47d6f02808ba 100644 --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c @@ -543,7 +543,7 @@ static int live_hwsp_engine(void *arg) return -ENOMEM; count = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (!intel_engine_can_store_dword(engine)) continue; @@ -619,7 +619,7 @@ static int live_hwsp_alternate(void *arg) count = 0; for (n = 0; n < NUM_TIMELINES; n++) { - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_timeline *tl; struct i915_request *rq; @@ -691,7 +691,7 @@ static int live_hwsp_wrap(void *arg) if (err) goto out_free; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { const u32 *hwsp_seqno[2]; struct i915_request *rq; u32 seqno[2]; @@ -1016,7 +1016,7 @@ static int live_hwsp_read(void *arg) goto out; } - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; unsigned long count = 0; IGT_TIMEOUT(end_time); @@ -1188,7 +1188,7 @@ static int live_hwsp_rollover_kernel(void *arg) * see a seqno rollover. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce = engine->kernel_context; struct intel_timeline *tl = ce->timeline; struct i915_request *rq[3] = {}; @@ -1266,7 +1266,7 @@ static int live_hwsp_rollover_user(void *arg) * on the user's timeline. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq[3] = {}; struct intel_timeline *tl; struct intel_context *ce; @@ -1357,7 +1357,7 @@ static int live_hwsp_recycle(void *arg) */ count = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { IGT_TIMEOUT(end_time); if (!intel_engine_can_store_dword(engine)) diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c b/drivers/gpu/drm/i915/gt/selftest_tlb.c index 3941f2d6fa47..ea52fe24901f 100644 --- a/drivers/gpu/drm/i915/gt/selftest_tlb.c +++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c @@ -293,7 +293,7 @@ mem_tlbinv(struct intel_gt *gt, } err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_gem_ww_ctx ww; struct intel_context *ce; int bit; diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 14a8b25b6204..55f9f5c556c3 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -70,7 +70,7 @@ reference_lists_init(struct intel_gt *gt, struct wa_lists *lists) gt_init_workarounds(gt, &lists->gt_wa_list); wa_init_finish(&lists->gt_wa_list); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_wa_list *wal = &lists->engine[id].wa_list; wa_init_start(wal, gt, "REF", engine->name); @@ -89,7 +89,7 @@ reference_lists_fini(struct intel_gt *gt, struct wa_lists *lists) struct intel_engine_cs *engine; enum intel_engine_id id; - for_each_engine(engine, gt, id) + for_each_enabled_engine(engine, gt, id) intel_wa_list_free(&lists->engine[id].wa_list); intel_wa_list_free(&lists->gt_wa_list); @@ -764,7 +764,7 @@ static int live_dirty_whitelist(void *arg) if (GRAPHICS_VER(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */ return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; int err; @@ -794,7 +794,7 @@ static int live_reset_whitelist(void *arg) /* If we reset the gpu, we should not lose the RING_NONPRIV */ igt_global_reset_lock(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (engine->whitelist.count == 0) continue; @@ -1089,7 +1089,7 @@ static int live_isolated_whitelist(void *arg) } } - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce[2]; if (!engine->kernel_context->vm) @@ -1172,7 +1172,7 @@ verify_wa_lists(struct intel_gt *gt, struct wa_lists *lists, ok &= wa_list_verify(gt, &lists->gt_wa_list, str); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; ce = intel_context_create(engine); @@ -1257,7 +1257,7 @@ live_engine_reset_workarounds(void *arg) reference_lists_init(gt, lists); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_selftest_saved_policy saved; bool using_guc = intel_engine_uses_guc(engine); bool ok; From patchwork Wed Aug 21 12:43:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BB21C52D6F for ; Wed, 21 Aug 2024 12:44:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CAC6510E8F4; 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X-CSE-ConnectionGUID: jbar3ig0SFSdDl0oqPE7nA== X-CSE-MsgGUID: RwdARdQRQnGIpVsAYSrG5Q== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="26395379" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="26395379" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:58 -0700 X-CSE-ConnectionGUID: rmL5mFkyT3mjDaqTS/V93g== X-CSE-MsgGUID: JfkFkOsWRr6ACO5283TKig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="66038720" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:44:56 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 07/14] drm/i915/gt: Manage CCS engine creation within UABI exposure Date: Wed, 21 Aug 2024 14:43:42 +0200 Message-ID: <20240821124349.295259-8-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In commit ea315f98e5d6 ("drm/i915/gt: Do not generate the command streamer for all the CCS"), we restricted the creation of physical CCS engines to only one stream. This allowed the user to submit a single compute workload, with all CCS slices sharing the workload from that stream. This patch removes that limitation but still exposes only one stream to the user. The physical memory for each engine remains allocated but unused, however the user will only see one engine exposed. Do this by adding only one engine to the UABI list, ensuring that only one engine is visible to the user. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 23 --------------------- drivers/gpu/drm/i915/gt/intel_engine_user.c | 17 ++++++++++++--- 2 files changed, 14 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 4d30a86016f2..def255ee0b96 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -876,29 +876,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) info->engine_mask &= ~BIT(GSC0); } - /* - * Do not create the command streamer for CCS slices beyond the first. - * All the workload submitted to the first engine will be shared among - * all the slices. - * - * Once the user will be allowed to customize the CCS mode, then this - * check needs to be removed. - */ - if (IS_DG2(gt->i915)) { - u8 first_ccs = __ffs(CCS_MASK(gt)); - - /* - * Store the number of active cslices before - * changing the CCS engine configuration - */ - gt->ccs.cslices = CCS_MASK(gt); - - /* Mask off all the CCS engine */ - info->engine_mask &= ~GENMASK(CCS3, CCS0); - /* Put back in the first CCS engine */ - info->engine_mask |= BIT(_CCS(first_ccs)); - } - return info->engine_mask; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index cd7662b1ad59..8e5284af8335 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -246,6 +246,20 @@ void intel_engines_driver_register(struct drm_i915_private *i915) GEM_BUG_ON(uabi_class >= ARRAY_SIZE(i915->engine_uabi_class_count)); + + /* Fix up the mapping to match default execbuf::user_map[] */ + add_legacy_ring(&ring, engine); + + /* + * Do not create the command streamer for CCS slices beyond the + * first. All the workload submitted to the first engine will be + * shared among all the slices. + */ + if (IS_DG2(i915) && + uabi_class == I915_ENGINE_CLASS_COMPUTE && + engine->uabi_instance) + goto clear_node_continue; + i915->engine_uabi_class_count[uabi_class]++; rb_link_node(&engine->uabi_node, prev, p); @@ -255,9 +269,6 @@ void intel_engines_driver_register(struct drm_i915_private *i915) engine->uabi_class, engine->uabi_instance) != engine); - /* Fix up the mapping to match default execbuf::user_map[] */ - add_legacy_ring(&ring, engine); - prev = &engine->uabi_node; p = &prev->rb_right; From patchwork Wed Aug 21 12:43:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F5DEC52D7C for ; Wed, 21 Aug 2024 12:45:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E1AB10E8F7; Wed, 21 Aug 2024 12:45:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ei32HDCJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0D68010E8F7; Wed, 21 Aug 2024 12:45:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724244304; x=1755780304; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XyCJzqHtg3tGBXRJlP1qWgUsdEQ7bma10824ECpUiLw=; b=Ei32HDCJwaYbxzduJGSKh6yuGzYVJMSKuWm47okwAPF1aQc+6Qz2Kzbe 7/WZI3kshkawX2ryXYUWEc4120Gah2EQu4Wj474qrjNhUnA1sQeaPaeua 6ocr7AFsmJO3MjW3EGCtv2UQZ/2VrI4SXG1YGzeBLz30jUqYxFBHWL/fG /YaDU9Y5TfB2DZwD0BMaDtmBZNlVPycBO/0DOV5YmTq0qWbRoNJguIw8B KP9DOLVFO8d1NlJklfgYFaE33xgzI8TO1RrUv6CoJY57hYkq7EsknRgUv Vj/vabxc7ObIfP5xcctwJTHxQnLk4C93MVo4ZegDBfcLb/XLUFp7fqw3V Q==; X-CSE-ConnectionGUID: qMNjuT/fTVqtvm1eKqVdpA== X-CSE-MsgGUID: +vBBNzpZQ/ycI4UfZaduxg== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="26395395" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="26395395" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:04 -0700 X-CSE-ConnectionGUID: SzfOM2bIQP2SrocvTm8ccg== X-CSE-MsgGUID: G7r7oqzzRfqJX4AXIBG0Rw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="66038723" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:01 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 08/14] drm/i915/gt: Remove cslices mask value from the CCS structure Date: Wed, 21 Aug 2024 14:43:43 +0200 Message-ID: <20240821124349.295259-9-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Following the decision to manage CCS engine creation within UABI engines, the "cslices" variable in the "ccs" structure in the "gt" is no longer needed. Remove it is now redundant. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 ----- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 5ca36985bdd7..f0319278a5fc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -9,7 +9,7 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { - unsigned long cslices_mask = gt->ccs.cslices; + unsigned long cslices_mask = CCS_MASK(gt); u32 mode_val = 0; /* CCS mode, i.e. number of CCS engines to be enabled */ u32 width = 1; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 9e257f34d05b..71e43071da0b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -218,11 +218,6 @@ struct intel_gt { * i.e. how the CCS streams are distributed amongs the slices. */ struct { - /* - * Mask of the non fused CCS slices - * to be used for the load balancing - */ - intel_engine_mask_t cslices; u32 mode_reg_val; } ccs; From patchwork Wed Aug 21 12:43:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 57DB1C52D6F for ; Wed, 21 Aug 2024 12:45:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C785410E8F9; Wed, 21 Aug 2024 12:45:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XA4OiTBS"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5F4AD10E8F9; Wed, 21 Aug 2024 12:45:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724244311; x=1755780311; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PP7eZ/Fk5eBZbLx6RVVsYVsWOwNVNlT3GGifE/xIu48=; b=XA4OiTBS0VtKZevc9VD7dxJZtjxFh61LLeF09/g8eEiTSAW0NH2a2AEc 4vyY0MYZXMAXTv9WIJvmn3naUEQcgIdQ1yVrsaQboGILQrfgh7V2JVt5t /+STxZM9GC1bQR0JadFLjCCzdXbzjlkzRDPVBWSvvoiOqVYvAxOYiTmjz zEzhlTy7T5JBpq+ijlLC3UJ1kz4aBhVZ0RU4zt9KrWBejeqPZzWRJHcd1 +juPst9njHrJ2YoBOc6Bvvy3t5wGcOHF7ybUGlHZ8urZR2mh1H4xswil+ /I1FTpaZjBUK3IwLaRsMKf37GiarsWN/0SAsYMnfcOTN0XEtQpK12kPjN g==; X-CSE-ConnectionGUID: KeRqssgLRU2L379EAOi1JQ== X-CSE-MsgGUID: kVnJJt9sQqW+BOdtoQ9zpQ== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="26395415" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="26395415" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:11 -0700 X-CSE-ConnectionGUID: u4G2rCa1Tp6WdCngNIaEVQ== X-CSE-MsgGUID: r9ddAbhJTOmrpGsdf9ADmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="66038744" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:07 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 09/14] drm/i915/gt: Expose the number of total CCS slices Date: Wed, 21 Aug 2024 14:43:44 +0200 Message-ID: <20240821124349.295259-10-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement a sysfs interface to show the number of available CCS slices. The displayed number does not take into account the CCS balancing mode. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 2 ++ 3 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index f0319278a5fc..ed3ad881a89d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -5,7 +5,9 @@ #include "i915_drv.h" #include "intel_gt_ccs_mode.h" +#include "intel_gt_print.h" #include "intel_gt_regs.h" +#include "intel_gt_sysfs.h" static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { @@ -95,3 +97,22 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) /* Initialize the CCS mode setting */ intel_gt_apply_ccs_mode(gt); } + +static ssize_t num_cslices_show(struct device *dev, + struct device_attribute *attr, + char *buff) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + u32 num_slices; + + num_slices = hweight32(CCS_MASK(gt)); + + return sysfs_emit(buff, "%u\n", num_slices); +} +static DEVICE_ATTR_RO(num_cslices); + +void intel_gt_sysfs_ccs_init(struct intel_gt *gt) +{ + if (sysfs_create_file(>->sysfs_gt, &dev_attr_num_cslices.attr)) + gt_warn(gt, "Failed to create sysfs num_cslices files\n"); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 4a6763b95a78..9696cc9017f6 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -9,5 +9,6 @@ #include "intel_gt.h" void intel_gt_ccs_mode_init(struct intel_gt *gt); +void intel_gt_sysfs_ccs_init(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c index 33cba406b569..895eedc402ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c @@ -12,6 +12,7 @@ #include "i915_drv.h" #include "i915_sysfs.h" #include "intel_gt.h" +#include "intel_gt_ccs_mode.h" #include "intel_gt_print.h" #include "intel_gt_sysfs.h" #include "intel_gt_sysfs_pm.h" @@ -101,6 +102,7 @@ void intel_gt_sysfs_register(struct intel_gt *gt) goto exit_fail; intel_gt_sysfs_pm_init(gt, >->sysfs_gt); + intel_gt_sysfs_ccs_init(gt); return; From patchwork Wed Aug 21 12:43:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 436E6C52D7C for ; Wed, 21 Aug 2024 12:45:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AD62F10E8FA; Wed, 21 Aug 2024 12:45:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="oBpqMuph"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id EDB0010E8FA; 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21 Aug 2024 05:45:15 -0700 X-CSE-ConnectionGUID: TLU1CkbtShO6DOUr/u6tcA== X-CSE-MsgGUID: ajmHN2vvSOe0FKbyDoE03w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="61052227" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:14 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 10/14] drm/i915/gt: Store engine-related sysfs kobjects Date: Wed, 21 Aug 2024 14:43:45 +0200 Message-ID: <20240821124349.295259-11-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Upcoming commits will need to access engine-related kobjects to enable the creation and destruction of sysfs interfaces at runtime. For this, store the "engine" directory (i915->sysfs_engine), the engine files (gt->kobj), and the default data (gt->kobj_defaults). Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 ++ drivers/gpu/drm/i915/gt/sysfs_engines.c | 4 ++++ drivers/gpu/drm/i915/i915_drv.h | 1 + 3 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index ba55c059063d..cdc695fda918 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -388,6 +388,8 @@ struct intel_engine_cs { u32 context_size; u32 mmio_base; + struct kobject *kobj; + struct intel_engine_tlb_inv tlb_inv; /* diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c b/drivers/gpu/drm/i915/gt/sysfs_engines.c index 021f51d9b456..f67f76df1cfe 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.c +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c @@ -506,6 +506,8 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) if (!dir) return; + i915->sysfs_engine = dir; + for_each_uabi_engine(engine, i915) { struct kobject *kobj; @@ -526,6 +528,8 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) add_defaults(container_of(kobj, struct kobj_engine, base)); + engine->kobj = kobj; + if (0) { err_object: kobject_put(kobj); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 94f7f6cc444c..3a8a757f5bd5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -320,6 +320,7 @@ struct drm_i915_private { struct intel_gt *gt[I915_MAX_GT]; struct kobject *sysfs_gt; + struct kobject *sysfs_engine; /* Quick lookup of media GT (current platforms only have one) */ struct intel_gt *media_gt; From patchwork Wed Aug 21 12:43:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F1696C52D6F for ; Wed, 21 Aug 2024 12:45:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 61AA810E8FE; Wed, 21 Aug 2024 12:45:24 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EooVOQZw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 183D310E8FD; Wed, 21 Aug 2024 12:45:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724244322; x=1755780322; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/2usmeWbKV9aExLWLCxw0zFs13mUPJc13Zpybup+IUs=; b=EooVOQZwtuDY9ZxwRrrDBcBfnmG/gowkakwUH0DdEfRap3llM5lC/47h ww+LIvrCOXrG/dHa4QuD1dfvbKbOZB2U7sysxNm/p7lELTWEUtMpfAGpL wDTFZxnkla5JyGMzCerOs2pKRmLPBlG7imxc5YsvOqNVGycjKQTzO2fnS tcWEEyYonduJw14wh+25U5bTtwqHrXWhGs8VhxpJwz8aataShs6rCMvWH Ss1j4XmWHswBrv+CBh27kGMT2a5KsWr1AskH3QVxpQZSV+sXPMo7pnss0 yMpuwMETIRhH9iC0tyfMP90YTic8NkANJzjIRW7rxly5DB2DuXyvuMCMG g==; X-CSE-ConnectionGUID: apcP1y9zSyiHBXAEkzxYhA== X-CSE-MsgGUID: RzXb5EqSTJCNfSZ+nd64oQ== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="40059740" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="40059740" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:21 -0700 X-CSE-ConnectionGUID: oViT/0jUSDaHc6CLeCCe5A== X-CSE-MsgGUID: vcUo7FBkQsK8FQhtdg4Cyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="61052260" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:20 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 11/14] drm/i915/gt: Store active CCS mask Date: Wed, 21 Aug 2024 14:43:46 +0200 Message-ID: <20240821124349.295259-12-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To support upcoming patches, we need to store the current mask for active CCS engines. Active engines refer to those exposed to userspace via the UABI engine list. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 54 ++++++++++++++++----- drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +++ 2 files changed, 49 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index ed3ad881a89d..45e9280f9bac 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -12,9 +12,10 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { unsigned long cslices_mask = CCS_MASK(gt); - u32 mode_val = 0; + unsigned long ccs_mask = gt->ccs.id_mask; /* CCS mode, i.e. number of CCS engines to be enabled */ - u32 width = 1; + u32 width = hweight32(ccs_mask); + u32 mode_val = 0; /* CCS engine id, i.e. the engines position in the engine's bitmask */ int engine; int cslice; @@ -57,7 +58,7 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) * slice 2: ccs2 * slice 3: ccs3 */ - engine = __ffs(cslices_mask); + engine = __ffs(ccs_mask); for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { if (!(cslices_mask & BIT(cslice))) { @@ -73,29 +74,58 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) mode_val |= XEHP_CCS_MODE_CSLICE(cslice, engine); if (!width) { - /* - * CCS mode, will be used later to - * reset to a flexible value - */ - width = 1; - engine = __ffs(cslices_mask); + /* CCS mode, reset to the initial mode */ + width = hweight32(ccs_mask); + engine = __ffs(ccs_mask); continue; } width--; - engine = find_next_bit(&cslices_mask, I915_MAX_CCS, engine + 1); + engine = find_next_bit(&ccs_mask, I915_MAX_CCS, engine + 1); } gt->ccs.mode_reg_val = mode_val; } +static void __update_ccs_mask(struct intel_gt *gt, u32 ccs_mode) +{ + unsigned long cslices_mask = CCS_MASK(gt); + int i; + + /* Mask off all the CCS engines */ + gt->ccs.id_mask = 0; + + for_each_set_bit(i, &cslices_mask, I915_MAX_CCS) { + gt->ccs.id_mask |= BIT(i); + + ccs_mode--; + if (!ccs_mode) + break; + } + + /* + * It's impossible for 'ccs_mode' to be zero at this point. + * This scenario would only occur if the 'ccs_mode' provided by + * the caller exceeded the total number of CCS engines, a condition + * we check before calling the 'update_ccs_mask()' function. + */ + GEM_BUG_ON(ccs_mode); + + /* Initialize the CCS mode setting */ + intel_gt_apply_ccs_mode(gt); +} + void intel_gt_ccs_mode_init(struct intel_gt *gt) { if (!IS_DG2(gt->i915)) return; - /* Initialize the CCS mode setting */ - intel_gt_apply_ccs_mode(gt); + /* + * Set CCS balance mode 1 in the ccs_mask. + * + * During init the workaround are not set up yet. + */ + __update_ccs_mask(gt, 1); } static ssize_t num_cslices_show(struct device *dev, diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 71e43071da0b..641be69016e1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -219,6 +219,13 @@ struct intel_gt { */ struct { u32 mode_reg_val; + + /* + * CCS id_mask is the command streamer instance + * exposed to the user. While the CCS_MASK(gt) + * is the available unfused compute slices. + */ + intel_engine_mask_t id_mask; } ccs; /* From patchwork Wed Aug 21 12:43:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73553C5320E for ; Wed, 21 Aug 2024 12:45:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DC12710E8FF; Wed, 21 Aug 2024 12:45:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="HWAU/a0D"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 156D310E8FF; Wed, 21 Aug 2024 12:45:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724244328; x=1755780328; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=avMTXjpHBEsLWS+hqfPrimZ0qbyak1ZnLZqsVuT/rJE=; b=HWAU/a0D7Hw7QIq2hi7sO1zMRMFEzWYsIF1CwpJGuMsa21/sawfpXmxq O7T6Kip7AuCdJJ0C9puOJMrF+jPjcYp2qNiKkfCMMW2uClfV7YOejCrQI o6VUnoq4ngVYsA7DgHqWZf1BtqjrqPxD2sVr04n/gvlb5e6KHvwz/DmQk QdUDFBZssr+rPC8sw0YQMSWUFsaEb/C9t3/HTnAtNHpKcUKPbrhJZqedw whP+SevN62f4zkLp1kN8WlAhq+SDKVVVZIgm6Eds0TlyuEjFeLKera1kO aomsZzuTkUc0ehNmQ9gEQJlK3qAbuGraClcPQSwtFhlUXvMu9dGm5sroy A==; X-CSE-ConnectionGUID: RTaeU6cTQhyuiJ/uiiqWKA== X-CSE-MsgGUID: I436D8ZnQheEE125oMHIZQ== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="40059762" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="40059762" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:27 -0700 X-CSE-ConnectionGUID: JezM4A/7SYKIpHXyZ/2ZZQ== X-CSE-MsgGUID: QwTZ2GVyShKsHnsix5l8oA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="61052295" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:27 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 12/14] drm/i915/gt: Isolate single sysfs engine file creation Date: Wed, 21 Aug 2024 14:43:47 +0200 Message-ID: <20240821124349.295259-13-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for upcoming patches, we need the ability to create and remove individual sysfs files. To facilitate this, extract from the intel_engines_add_sysfs() function the creation of individual files. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/sysfs_engines.c | 76 ++++++++++++++++--------- drivers/gpu/drm/i915/gt/sysfs_engines.h | 2 + 2 files changed, 50 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c b/drivers/gpu/drm/i915/gt/sysfs_engines.c index f67f76df1cfe..fd1685f81505 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.c +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "intel_engine.h" #include "intel_engine_heartbeat.h" +#include "intel_gt_print.h" #include "sysfs_engines.h" struct kobj_engine { @@ -481,7 +482,7 @@ static void add_defaults(struct kobj_engine *parent) return; } -void intel_engines_add_sysfs(struct drm_i915_private *i915) +int intel_engine_add_single_sysfs(struct intel_engine_cs *engine) { static const struct attribute * const files[] = { &name_attr.attr, @@ -497,7 +498,50 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) #endif NULL }; + struct kobject *dir = engine->i915->sysfs_engine; + struct kobject *kobj = engine->kobj; + int err; + + if (!kobj) { + kobj = kobj_engine(dir, engine); + if (!kobj) { + err = -EFAULT; + goto err_engine; + } + } + + err = sysfs_create_files(kobj, files); + if (err) + goto err_object; + + if (intel_engine_has_timeslices(engine)) { + err = sysfs_create_file(kobj, ×lice_duration_attr.attr); + if (err) + goto err_object; + } + + if (intel_engine_has_preempt_reset(engine)) { + err = sysfs_create_file(kobj, &preempt_timeout_attr.attr); + if (err) + goto err_object; + } + add_defaults(container_of(kobj, struct kobj_engine, base)); + + engine->kobj = kobj; + + return 0; + +err_object: + kobject_put(kobj); +err_engine: + gt_warn(engine->gt, "Failed to add sysfs engine '%s'\n", engine->name); + + return err; +} + +void intel_engines_add_sysfs(struct drm_i915_private *i915) +{ struct device *kdev = i915->drm.primary->kdev; struct intel_engine_cs *engine; struct kobject *dir; @@ -509,34 +553,10 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) i915->sysfs_engine = dir; for_each_uabi_engine(engine, i915) { - struct kobject *kobj; - - kobj = kobj_engine(dir, engine); - if (!kobj) - goto err_engine; - - if (sysfs_create_files(kobj, files)) - goto err_object; + int err; - if (intel_engine_has_timeslices(engine) && - sysfs_create_file(kobj, ×lice_duration_attr.attr)) - goto err_engine; - - if (intel_engine_has_preempt_reset(engine) && - sysfs_create_file(kobj, &preempt_timeout_attr.attr)) - goto err_engine; - - add_defaults(container_of(kobj, struct kobj_engine, base)); - - engine->kobj = kobj; - - if (0) { -err_object: - kobject_put(kobj); -err_engine: - dev_err(kdev, "Failed to add sysfs engine '%s'\n", - engine->name); + err = intel_engine_add_single_sysfs(engine); + if (err) break; - } } } diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.h b/drivers/gpu/drm/i915/gt/sysfs_engines.h index 9546fffe03a7..2e3ec2df14a9 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.h +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.h @@ -7,7 +7,9 @@ #define INTEL_ENGINE_SYSFS_H struct drm_i915_private; +struct intel_engine_cs; void intel_engines_add_sysfs(struct drm_i915_private *i915); +int intel_engine_add_single_sysfs(struct intel_engine_cs *engine); #endif /* INTEL_ENGINE_SYSFS_H */ From patchwork Wed Aug 21 12:43:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C9B6C52D7C for ; Wed, 21 Aug 2024 12:45:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ABD8110E904; Wed, 21 Aug 2024 12:45:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; 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a="40059773" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="40059773" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:33 -0700 X-CSE-ConnectionGUID: bT7+PR8hRiCsJGTdM2/D0Q== X-CSE-MsgGUID: HXATBpA2SJmOAmX28+yD6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="61052305" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:32 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 13/14] drm/i915/gt: Implement creation and removal routines for CCS engines Date: Wed, 21 Aug 2024 14:43:48 +0200 Message-ID: <20240821124349.295259-14-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for upcoming patches, we need routines to dynamically create and destroy CCS engines based on the CCS mode that the user wants to set. The process begins by calculating the engine mask for the engines that need to be added or removed. We then update the UABI list of exposed engines and create or destroy the corresponding sysfs interfaces accordingly. These functions are not yet in use, so no functional changes are intended at this stage. Mark the functions 'add_uabi_ccs_engines()' and 'remove_uabi_ccs_engines()' as '__maybe_unused' to ensure successful compilation and maintain bisectability. This annotation will be removed in subsequent commits. Use a mutex to control the changes to the uabi engine. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 + drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 + drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 99 ++++++++++++++++++++ 3 files changed, 106 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index cdc695fda918..28a81e33dbe1 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -413,6 +413,11 @@ struct intel_engine_cs { struct list_head uabi_list; struct rb_node uabi_node; }; + /* + * Serialize changes if the engine status, validity (through + * RB_CLEAR_NODE) and insertion and removal from uabi list + */ + struct mutex uabi_mutex; struct intel_sseu sseu; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 8e5284af8335..c50060133336 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -219,6 +219,8 @@ void intel_engines_driver_register(struct drm_i915_private *i915) struct intel_engine_cs *engine = container_of(it, typeof(*engine), uabi_list); + mutex_init(&engine->uabi_mutex); + if (intel_gt_has_unrecoverable_error(engine->gt)) goto clear_node_continue; /* ignore incomplete engines */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 45e9280f9bac..82de29eb4dd7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -8,6 +8,7 @@ #include "intel_gt_print.h" #include "intel_gt_regs.h" #include "intel_gt_sysfs.h" +#include "sysfs_engines.h" static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { @@ -115,6 +116,29 @@ static void __update_ccs_mask(struct intel_gt *gt, u32 ccs_mode) intel_gt_apply_ccs_mode(gt); } +static void update_ccs_mask(struct intel_gt *gt, u32 ccs_mode) +{ + struct intel_engine_cs *engine; + intel_engine_mask_t tmp; + + __update_ccs_mask(gt, ccs_mode); + + /* Update workaround values */ + for_each_engine_masked(engine, gt, gt->ccs.id_mask, tmp) { + struct i915_wa_list *wal = &engine->wa_list; + struct i915_wa *wa; + int i; + + for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { + if (!i915_mmio_reg_equal(wa->reg, XEHP_CCS_MODE)) + continue; + + wa->set = gt->ccs.mode_reg_val; + wa->read = gt->ccs.mode_reg_val; + } + } +} + void intel_gt_ccs_mode_init(struct intel_gt *gt) { if (!IS_DG2(gt->i915)) @@ -128,6 +152,81 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) __update_ccs_mask(gt, 1); } +static int rb_engine_cmp(struct rb_node *rb_new, const struct rb_node *rb_old) +{ + struct intel_engine_cs *new = rb_to_uabi_engine(rb_new); + struct intel_engine_cs *old = rb_to_uabi_engine(rb_old); + + return new->uabi_instance - old->uabi_instance; +} + +static void __maybe_unused add_uabi_ccs_engines(struct intel_gt *gt, u32 ccs_mode) +{ + struct drm_i915_private *i915 = gt->i915; + intel_engine_mask_t new_ccs_mask, tmp; + struct intel_engine_cs *e; + + /* Store the current ccs mask */ + new_ccs_mask = gt->ccs.id_mask; + update_ccs_mask(gt, ccs_mode); + + /* + * Store only the mask of the CCS engines that need to be added by + * removing from the new mask the engines that are already active + */ + new_ccs_mask = gt->ccs.id_mask & ~new_ccs_mask; + new_ccs_mask <<= CCS0; + + for_each_engine_masked(e, gt, new_ccs_mask, tmp) { + mutex_lock(&e->uabi_mutex); + + i915->engine_uabi_class_count[I915_ENGINE_CLASS_COMPUTE]++; + + /* The engine is now inserted and marked as valid */ + rb_find_add(&e->uabi_node, &i915->uabi_engines, rb_engine_cmp); + + if (intel_engine_add_single_sysfs(e)) + gt_warn(gt, + "Unable to create sysfs entries for %s engine", + e->name); + + mutex_unlock(&e->uabi_mutex); + } +} + +static void __maybe_unused remove_uabi_ccs_engines(struct intel_gt *gt, u8 ccs_mode) +{ + struct drm_i915_private *i915 = gt->i915; + intel_engine_mask_t new_ccs_mask, tmp; + struct intel_engine_cs *e; + + /* Store the current ccs mask */ + new_ccs_mask = gt->ccs.id_mask; + update_ccs_mask(gt, ccs_mode); + + /* + * Store only the mask of the CCS engines that need to be removed by + * unmasking them from the new mask the engines that are already active + */ + new_ccs_mask = new_ccs_mask & ~gt->ccs.id_mask; + new_ccs_mask <<= CCS0; + + for_each_engine_masked(e, gt, new_ccs_mask, tmp) { + mutex_lock(&e->uabi_mutex); + + i915->engine_uabi_class_count[I915_ENGINE_CLASS_COMPUTE]--; + + rb_erase(&e->uabi_node, &i915->uabi_engines); + RB_CLEAR_NODE(&e->uabi_node); + + /* Remove sysfs entries */ + kobject_del(e->kobj); + e->kobj = NULL; + + mutex_unlock(&e->uabi_mutex); + } +} + static ssize_t num_cslices_show(struct device *dev, struct device_attribute *attr, char *buff) From patchwork Wed Aug 21 12:43:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13771391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88F10C52D6F for ; Wed, 21 Aug 2024 12:45:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E951C10E901; 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X-CSE-ConnectionGUID: eSKsigPIS7WtdmoVBmbKxQ== X-CSE-MsgGUID: ItqSWTE6QXCtk/eHKX6Cyw== X-IronPort-AV: E=McAfee;i="6700,10204,11171"; a="40059790" X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="40059790" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:39 -0700 X-CSE-ConnectionGUID: ovQTO5/RSs+Mh7sWWGGlMw== X-CSE-MsgGUID: RLlIARBPRzW1vw9NZde2pQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="61052311" Received: from bergbenj-mobl1.ger.corp.intel.com (HELO intel.com) ([10.245.246.24]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2024 05:45:38 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v1 14/14] drm/i915/gt: Allow the user to change the CCS mode through sysfs Date: Wed, 21 Aug 2024 14:43:49 +0200 Message-ID: <20240821124349.295259-15-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240821124349.295259-1-andi.shyti@linux.intel.com> References: <20240821124349.295259-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Create the 'ccs_mode' file under /sys/class/drm/cardX/gt/gt0/ccs_mode This file allows the user to read and set the current CCS mode. - Reading: The user can read the current CCS mode, which can be 1, 2, or 4. This value is derived from the current engine mask. - Writing: The user can set the CCS mode to 1, 2, or 4, depending on the desired number of exposed engines and the required load balancing. The interface will return -EBUSY if other clients are connected to i915, or -EINVAL if an invalid value is set. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 82 ++++++++++++++++++++- 1 file changed, 80 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 82de29eb4dd7..ffdcc98b0802 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -5,6 +5,7 @@ #include "i915_drv.h" #include "intel_gt_ccs_mode.h" +#include "intel_gt_pm.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" #include "intel_gt_sysfs.h" @@ -160,7 +161,7 @@ static int rb_engine_cmp(struct rb_node *rb_new, const struct rb_node *rb_old) return new->uabi_instance - old->uabi_instance; } -static void __maybe_unused add_uabi_ccs_engines(struct intel_gt *gt, u32 ccs_mode) +static void add_uabi_ccs_engines(struct intel_gt *gt, u32 ccs_mode) { struct drm_i915_private *i915 = gt->i915; intel_engine_mask_t new_ccs_mask, tmp; @@ -194,7 +195,7 @@ static void __maybe_unused add_uabi_ccs_engines(struct intel_gt *gt, u32 ccs_mod } } -static void __maybe_unused remove_uabi_ccs_engines(struct intel_gt *gt, u8 ccs_mode) +static void remove_uabi_ccs_engines(struct intel_gt *gt, u8 ccs_mode) { struct drm_i915_private *i915 = gt->i915; intel_engine_mask_t new_ccs_mask, tmp; @@ -240,8 +241,85 @@ static ssize_t num_cslices_show(struct device *dev, } static DEVICE_ATTR_RO(num_cslices); +static ssize_t ccs_mode_show(struct device *dev, + struct device_attribute *attr, char *buff) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + u32 ccs_mode; + + ccs_mode = hweight32(gt->ccs.id_mask); + + return sysfs_emit(buff, "%u\n", ccs_mode); +} + +static ssize_t ccs_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buff, size_t count) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + int num_cslices = hweight32(CCS_MASK(gt)); + int ccs_mode = hweight32(gt->ccs.id_mask); + ssize_t ret; + u32 val; + + ret = kstrtou32(buff, 0, &val); + if (ret) + return ret; + + /* + * As of now possible values to be set are 1, 2, 4, + * up to the maximum number of available slices + */ + if (!val || val > num_cslices || (num_cslices % val)) + return -EINVAL; + + /* Let's wait until the GT is no longer in use */ + ret = intel_gt_pm_wait_for_idle(gt); + if (ret) + return ret; + + mutex_lock(>->wakeref.mutex); + + /* + * Let's check again that the GT is idle, + * we don't want to change the CCS mode + * while someone is using the GT + */ + if (intel_gt_pm_is_awake(gt)) { + ret = -EBUSY; + goto out; + } + + /* + * Nothing to do if the requested setting + * is the same as the current one + */ + if (val == ccs_mode) + goto out; + else if (val > ccs_mode) + add_uabi_ccs_engines(gt, val); + else + remove_uabi_ccs_engines(gt, val); + +out: + mutex_unlock(>->wakeref.mutex); + + return ret ?: count; +} +static DEVICE_ATTR_RW(ccs_mode); + void intel_gt_sysfs_ccs_init(struct intel_gt *gt) { if (sysfs_create_file(>->sysfs_gt, &dev_attr_num_cslices.attr)) gt_warn(gt, "Failed to create sysfs num_cslices files\n"); + + /* + * Do not create the ccs_mode file for non DG2 platforms + * because they don't need it as they have only one CCS engine + */ + if (!IS_DG2(gt->i915)) + return; + + if (sysfs_create_file(>->sysfs_gt, &dev_attr_ccs_mode.attr)) + gt_warn(gt, "Failed to create sysfs ccs_mode files\n"); }