From patchwork Wed Aug 21 13:40:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sagar, Vishal" X-Patchwork-Id: 13771648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76958C52D6F for ; Wed, 21 Aug 2024 13:42:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=pkq60Vswh5YghXxNNO/NyBf/0xieb+q0DRK6whcAT/Y=; b=eI9L2KoIhyfVhTQWCJYFIB+4f3 bYZngHyG+h83vyGVzNYlMi+lRNbd333nn1usM09XHuESvljB3n0p/AKojoXQtM13LgaW/r7B/05MD Hr5hC5m7xwAczfVXNmkWyH8KeLc90KJ8SYMlm5CWYR8FbuPraJnmT0i8ysdsP2/jgNxZPhd0yY+Ry qt2A27v3fGkqSAK7fxHeSZJpPkzCBLWYvO5ell5sHWGv5W+8pOOAPL8vWpSdALY1IUf13NlThEnYX 6aY+sunbnSZ26tZJ4asasu7inbgjkKEpiA2m87D7eh5KuxoJUlx2t2GLZVVrnx2OfbWRX5LYhCRRf +w/LBpzw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sglau-00000009AMa-2OPH; Wed, 21 Aug 2024 13:41:48 +0000 Received: from mail-dm3nam02on20613.outbound.protection.outlook.com ([2a01:111:f403:2405::613] helo=NAM02-DM3-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sglaA-00000009AC6-34jq for linux-arm-kernel@lists.infradead.org; Wed, 21 Aug 2024 13:41:04 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=y3zhpCiUGBY3lxMbeHMhiynLJyvbQk70CyM6O4bR3iFpzxu0gnfSNIKCHQY9nDy++yW9qAs1ptLmqg032YzV0NBbMfxePzURIxkXatlwLhk5rluuDbt11R5UZuX5wkHMNpH1RWBj5+EUWvroxxdByGpjomioU50y5T74lvwNDpCfcinXhv/wufHUiA2kw0epzx2S1gN+bDqM85rs9GkOl4LaXRMqmGx6rVZHQU+yTTrhQIy9iIHldS/FDNVHIWGOCVjqmv0JHk3NGsR+UEa8U1J8dr2sw0KAWV7uGfVJovFMwa26t9qDUK7JGSivX4v8rKsct9nmwU3C2pmKLP0QIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pkq60Vswh5YghXxNNO/NyBf/0xieb+q0DRK6whcAT/Y=; b=xNYFLr2cBMIUyiCTo3ei+awSfl3B7XK3cEFJvtAgHt1kvT8rVOiomiUsw6yeLzCiAE/VYLB0LnwvB3TQhXrYcy1jPeWB9z25aT22KW4kzw0z5nz15RI6KTSdRXaxB0bs7Jb80rusPxMIlBm2Ns5eKtWJG7kPpnyr6MgbC7BmHtNkbZpGLmTJPmTrkjYGNtJBfE/mfgkmCwGDsgyfULi5gk/kIsyTTxqfQ9K4dqx5ZZTT8Ev8UKiin5StzQSnefzHVBOuSPO+h27xvV4knugIJ4IHevdWDulvEEa03vM9CoXKy4xwx0b1+K8OPDu42QisLErBLGDBKvcsnGh7jxuzcQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=ideasonboard.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pkq60Vswh5YghXxNNO/NyBf/0xieb+q0DRK6whcAT/Y=; b=mAeZURDQOtwlC1TeFe3DJPrvc2jWFPyjH9P3vgtok5MHOa2u0xACcEMrkcX9Jnj7UQx66yEKno0pJYeNggMr92FFCDv07MBTEyAc5t3aikXihqrhheHYJ2nvj0yyjMuwZM3X5Lhr05/+QI7Orj9UPsOCksEfY+awWmcWtjQ0WqQ= Received: from SJ0PR13CA0239.namprd13.prod.outlook.com (2603:10b6:a03:2c1::34) by PH7PR12MB9204.namprd12.prod.outlook.com (2603:10b6:510:2e7::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7897.19; Wed, 21 Aug 2024 13:40:49 +0000 Received: from SJ5PEPF000001EC.namprd05.prod.outlook.com (2603:10b6:a03:2c1:cafe::88) by SJ0PR13CA0239.outlook.office365.com (2603:10b6:a03:2c1::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7897.13 via Frontend Transport; Wed, 21 Aug 2024 13:40:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001EC.mail.protection.outlook.com (10.167.242.200) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7897.11 via Frontend Transport; Wed, 21 Aug 2024 13:40:49 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 21 Aug 2024 08:40:45 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 21 Aug 2024 08:40:44 -0500 Received: from xsjssw-mmedia3.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Wed, 21 Aug 2024 08:40:44 -0500 From: Vishal Sagar To: , , CC: , , , , Subject: [PATCH v3] dmaengine: xilinx: dpdma: Add support for cyclic dma mode Date: Wed, 21 Aug 2024 06:40:43 -0700 Message-ID: <20240821134043.2885506-1-vishal.sagar@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EC:EE_|PH7PR12MB9204:EE_ X-MS-Office365-Filtering-Correlation-Id: 45aaf7d0-6fe3-4e7d-849f-08dcc1e6de2d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: CFqOStvKSWU8WOw0mWYRaAzLdNB8k66+CEhbpY+3T/rSSIPjLOjP2fGy/pRPPDg3TAvMV4CI0uGYwOPsJQgdtH8TL2OEL1CYFsLscJXTn25iyxlKPUQ6Y8JQVRQ7xW5J/14IgE+xxTbF42haamyLFhek5C9LfpG27Iiby68oqZdnoNA8C+TkCpNxuGKS39nWwaKDunWiUUxdxOpkGaQWUO9BCqmBlYNRUokgATKbYdunTNAEyIw6bLLDCFjBlW/PgyHmgukgf4PTltuLdyPRpqOh6LCvxItN8khXdM1JwS20tDinCUVynptPUivpFZhFPC6x+vt/2IBm9nu9socgBOy4dmVLZwVXsVQcb190c4FMO2aDNk/EANaFiq4paL2gXfdfmwPomG24icFVnJkkQKA1EqxshDYJZiYfHI35ictqMZRHUjxn/NJiTvF9wKXeVj2fy9jyUsEj1CMNf08JcXiTDLz0wcUwjMejP+U4OCfmkxcZ0AsalUPsN1E1pV45mxi/bQtuz1bg0RP+7OLbBHwtA2rMB25WbG4BgSWgWYxSlSOk4w8OXfT7UbnhIJ1I5NOVoIvX+fdXi5gJLBXwtVQa5tnV+m3Jad0zRxgPiqaELnVIEtIuDi/2yx2fcJWIl+m6SPpuyOaXHZKlu9i9epIogfpFap5gzuFsg/wtYvvk6xMky2xQ2l1HQRW/bmqdil1n3D6zp3+IvAWcRaZV9hbXFRub7i5y6Dq+t/JOLvcBBYi/AOxr3YVt5ZIyNs5PHX2ec6xsR9Lu69Ffy8cgSI7teY8dBUOa/iBD833igvM8n/noJAD0u0spgg5R1xNVCtkQMukyafSH+wO0zcY2Bv3/sDyoJMAGix6xPqYJ26WmSUlRJq0UkHHlGuFbdNrn6i+2Ri0pBwqoU9TA/HJCzx4sdx6ruaKP1bp2f713pUA86FCom/TBaTnjVK+LoixDo23NvUqu60f/oWzMOGIYmjk+1ZPTFH8WI5x06wFFSiYi4KkBAXOi2plhivtjnzQuQAflW95Af0sKhM3UR9zEn7Ow2wwLLKOjws38pD6QDZwP1hDa8Zp7tT1uUq3PYZ5QyfcdvjzWhsbdUY9zQkrBP64S8WtFixaNeQOVfjaZml8JbMVG+xQubnv4FwpatujdSwkro2+bqmaevN2eAAsreCbcJRzqaqFlyPJaZu1hqxd/j6auUkYy518xRPx/G3BqtrBf5y/ZCkfUImHGTmBPx0HeFNz+feuTkTKY2OpC2S3REp6rmy3iOhCi5YlIkIIcMC6aIz/0cwQK6nSW8cGeoUO8JW4S37APbjaTeqSOJQJ98Xv2I3c5SUoa+80H3rNVRfQEXdRnSMxhj7Do5urV6XrszcsCe7j1fRLPdYlj+iM7ATHcqc2ZO79U4OR9PIMLbw4iidIW3nnhR12sCVvG1Y0wv/vghEEAEws7tfjfNsM9aAJt2ChnizH2aigB8yJq X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2024 13:40:49.2525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 45aaf7d0-6fe3-4e7d-849f-08dcc1e6de2d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9204 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240821_064102_787261_AC2A4C1B X-CRM114-Status: GOOD ( 17.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rohit Visavalia This patch adds support for DPDMA cyclic dma mode, DMA cyclic transfers are required by audio streaming. Signed-off-by: Rohit Visavalia Signed-off-by: Radhey Shyam Pandey Signed-off-by: Vishal Sagar Reviewed-by: Tomi Valkeinen --- Change in [v3] - Fixed cosmetic changes as suggested by Tomi - Added Reviewed-by Tomi Previous version is 2/2 https://lore.kernel.org/linux-kernel/20240228042124.3074044-3-vishal.sagar@amd.com/ drivers/dma/xilinx/xilinx_dpdma.c | 97 +++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/dma/xilinx/xilinx_dpdma.c b/drivers/dma/xilinx/xilinx_dpdma.c index 36bd4825d389..77b5f7da7f1d 100644 --- a/drivers/dma/xilinx/xilinx_dpdma.c +++ b/drivers/dma/xilinx/xilinx_dpdma.c @@ -670,6 +670,84 @@ static void xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc *vdesc) kfree(desc); } +/** + * xilinx_dpdma_chan_prep_cyclic - Prepare a cyclic dma descriptor + * @chan: DPDMA channel + * @buf_addr: buffer address + * @buf_len: buffer length + * @period_len: number of periods + * @flags: tx flags argument passed in to prepare function + * + * Prepare a tx descriptor incudling internal software/hardware descriptors + * for the given cyclic transaction. + * + * Return: A dma async tx descriptor on success, or NULL. + */ +static struct dma_async_tx_descriptor * +xilinx_dpdma_chan_prep_cyclic(struct xilinx_dpdma_chan *chan, + dma_addr_t buf_addr, size_t buf_len, + size_t period_len, unsigned long flags) +{ + struct xilinx_dpdma_tx_desc *tx_desc; + struct xilinx_dpdma_sw_desc *sw_desc, *last = NULL; + unsigned int periods = buf_len / period_len; + unsigned int i; + + tx_desc = xilinx_dpdma_chan_alloc_tx_desc(chan); + if (!tx_desc) + return NULL; + + for (i = 0; i < periods; i++) { + struct xilinx_dpdma_hw_desc *hw_desc; + + if (!IS_ALIGNED(buf_addr, XILINX_DPDMA_ALIGN_BYTES)) { + dev_err(chan->xdev->dev, + "buffer should be aligned at %d B\n", + XILINX_DPDMA_ALIGN_BYTES); + goto error; + } + + sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan); + if (!sw_desc) + goto error; + + xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, last, + &buf_addr, 1); + hw_desc = &sw_desc->hw; + hw_desc->xfer_size = period_len; + hw_desc->hsize_stride = + FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK, + period_len) | + FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK, + period_len); + hw_desc->control = XILINX_DPDMA_DESC_CONTROL_PREEMBLE | + XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE | + XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR; + + list_add_tail(&sw_desc->node, &tx_desc->descriptors); + + buf_addr += period_len; + last = sw_desc; + } + + sw_desc = list_first_entry(&tx_desc->descriptors, + struct xilinx_dpdma_sw_desc, node); + last->hw.next_desc = lower_32_bits(sw_desc->dma_addr); + if (chan->xdev->ext_addr) + last->hw.addr_ext |= + FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK, + upper_32_bits(sw_desc->dma_addr)); + + last->hw.control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME; + + return vchan_tx_prep(&chan->vchan, &tx_desc->vdesc, flags); + +error: + xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc); + + return NULL; +} + /** * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma * descriptor @@ -1189,6 +1267,23 @@ static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan) /* ----------------------------------------------------------------------------- * DMA Engine Operations */ +static struct dma_async_tx_descriptor * +xilinx_dpdma_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction direction, + unsigned long flags) +{ + struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); + + if (direction != DMA_MEM_TO_DEV) + return NULL; + + if (buf_len % period_len) + return NULL; + + return xilinx_dpdma_chan_prep_cyclic(chan, buf_addr, buf_len, + period_len, flags); +} static struct dma_async_tx_descriptor * xilinx_dpdma_prep_interleaved_dma(struct dma_chan *dchan, @@ -1672,6 +1767,7 @@ static int xilinx_dpdma_probe(struct platform_device *pdev) dma_cap_set(DMA_SLAVE, ddev->cap_mask); dma_cap_set(DMA_PRIVATE, ddev->cap_mask); + dma_cap_set(DMA_CYCLIC, ddev->cap_mask); dma_cap_set(DMA_INTERLEAVE, ddev->cap_mask); dma_cap_set(DMA_REPEAT, ddev->cap_mask); dma_cap_set(DMA_LOAD_EOT, ddev->cap_mask); @@ -1679,6 +1775,7 @@ static int xilinx_dpdma_probe(struct platform_device *pdev) ddev->device_alloc_chan_resources = xilinx_dpdma_alloc_chan_resources; ddev->device_free_chan_resources = xilinx_dpdma_free_chan_resources; + ddev->device_prep_dma_cyclic = xilinx_dpdma_prep_dma_cyclic; ddev->device_prep_interleaved_dma = xilinx_dpdma_prep_interleaved_dma; /* TODO: Can we achieve better granularity ? */ ddev->device_tx_status = dma_cookie_status;