From patchwork Thu Aug 22 09:14:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13773043 Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [195.130.132.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC09917A588 for ; Thu, 22 Aug 2024 09:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724318055; cv=none; b=hJqT0Bhaz1ho0OIAZeA/1UmG0hpwhJVPdyqhAWUzlUBIgj9JonZPnZAag6S0+VYr8yy8OPq32dU25Dm1hEclsZ1WBqDjV3VzIjwuyPNWERr+OOwXpqnAxdq/t9CZrz/J2+0n8OcKE/XGwD5D5Wcx64OHEB2pi5iqqXShk0yUouo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724318055; c=relaxed/simple; bh=ZEn582CeTz1VVi0VgC29FzZH4xdaCnRULOwrh5+x7t4=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=D+Cj7jsiCVSbjs5QD9ohmaSNq8trIF7uBhe9K0/qkV8QMPOJin6QQAvGMYcTAxsDVDyAAXRMjJ8zzZgbKCMunfKdlrppDBuVNGWa8SIj0YvT/AIWvDZhDBHzctW8vsWCnN3/FcC2mdRXE3/vJ27Asxc6dH+P5nrQf01eJQWhlzo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:410c:b78a:c35b:cd3e]) by baptiste.telenet-ops.be with bizsmtp id 2xEA2D00X22R5AR01xEAHc; Thu, 22 Aug 2024 11:14:10 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1sh3tQ-000VYO-8J; Thu, 22 Aug 2024 11:14:10 +0200 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1sh3tS-002LKm-Fy; Thu, 22 Aug 2024 11:14:10 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [GIT PULL] clk: renesas: Updates for v6.12 Date: Thu, 22 Aug 2024 11:14:09 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Mike, Stephen, The following changes since commit 8400291e289ee6b2bf9779ff1c83a291501f017b: Linux 6.11-rc1 (2024-07-28 14:19:55 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.12-tag1 for you to fetch changes up to 120c2833b72f4bdbd67ea2cf70b9d96d1c235717: clk: renesas: r8a779h0: Add CANFD clock (2024-08-20 09:48:24 +0200) ---------------------------------------------------------------- clk: renesas: Updates for v6.12 - Add PCIe, PWM, and CAN-FD clocks on R-Car V4M, - Add LCD controller clocks and resets on RZ/G2UL, - Add DMA clocks and resets on RZ/G3S, - Add fractional multiplication PLL support on R-Car Gen4, - Document support for the Renesas RZ/G2M v3.0 (r8a774a3) SoC, - Add support for the RZ/V2H(P) (R9A09G057) SoC, - Miscellaneous fixes and improvements. Thanks for pulling! ---------------------------------------------------------------- Biju Das (1): clk: renesas: r9a07g043: Add LCDC clock and reset entries Claudiu Beznea (1): clk: renesas: r9a08g045: Add DMA clocks and resets Cong Dang (2): clk: renesas: r8a779h0: Add PWM clock clk: renesas: r8a779h0: Add CANFD clock Geert Uytterhoeven (19): clk: renesas: r8a779a0: cpg_pll_configs should be __initconst clk: renesas: r8a779f0: cpg_pll_configs should be __initconst clk: renesas: r8a779g0: cpg_pll_configs should be __initconst clk: renesas: r8a779h0: Initial clock descriptions should be __initconst clk: renesas: rcar-gen4: Removed unused SSMODE_* definitions clk: renesas: rcar-gen4: Clarify custom PLL clock support clk: renesas: rcar-gen4: Use FIELD_GET() clk: renesas: rcar-gen4: Use defines for common CPG registers clk: renesas: rcar-gen4: Add support for fractional multiplication clk: renesas: rcar-gen4: Add support for variable fractional PLLs clk: renesas: rcar-gen4: Add support for fixed variable PLLs clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs clk: renesas: r8a779a0: Use defines for PLL control registers clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type clk: renesas: rcar-gen4: Remove unused fixed PLL clock types clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs Lad Prabhakar (5): clk: renesas: rzg2l-cpg: Use devres API to register clocks clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock register functions dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG clk: renesas: Add family-specific clock driver for RZ/V2H(P) clk: renesas: Add RZ/V2H(P) CPG driver Oliver Rhodes (1): dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock Yoshihiro Shimoda (1): clk: renesas: r8a779h0: Add PCIe clock .../bindings/clock/renesas,cpg-mssr.yaml | 1 + .../bindings/clock/renesas,rzv2h-cpg.yaml | 80 +++ drivers/clk/renesas/Kconfig | 9 + drivers/clk/renesas/Makefile | 2 + drivers/clk/renesas/r8a779a0-cpg-mssr.c | 37 +- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 30 +- drivers/clk/renesas/r8a779g0-cpg-mssr.c | 38 +- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 41 +- drivers/clk/renesas/r9a07g043-cpg.c | 12 + drivers/clk/renesas/r9a08g045-cpg.c | 3 + drivers/clk/renesas/r9a09g057-cpg.c | 80 +++ drivers/clk/renesas/rcar-gen4-cpg.c | 210 ++++--- drivers/clk/renesas/rcar-gen4-cpg.h | 36 +- drivers/clk/renesas/rzg2l-cpg.c | 71 ++- drivers/clk/renesas/rzv2h-cpg.c | 690 +++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 151 +++++ include/dt-bindings/clock/renesas,r9a09g057-cpg.h | 21 + 17 files changed, 1325 insertions(+), 187 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml create mode 100644 drivers/clk/renesas/r9a09g057-cpg.c create mode 100644 drivers/clk/renesas/rzv2h-cpg.c create mode 100644 drivers/clk/renesas/rzv2h-cpg.h create mode 100644 include/dt-bindings/clock/renesas,r9a09g057-cpg.h Gr{oetje,eeting}s, Geert --- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds