From patchwork Thu Aug 22 10:14:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13773225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 170F0C52D7C for ; Thu, 22 Aug 2024 11:16:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Z2YruM5YdxZLehQGogIQE9s5P532/c0varr05R8kQo4=; b=QhGuhVdgsKCkOkiF4d0qW1oNeB 29DBIZilpUj/wDUsT1Frg3aKzpCENvQUMO3ebIiGmruM3xHFs4+a4RWHFBZhHC/5lrnNpqgf4bqWb K0VM32zLSYO6g32XTGXleda+QJ7B7tZgN0wNARU35eeffhv0mmxzNPN9/OzPDjfB2VrUv5IAwhMnt nJ7pd+zruAq2zwNz2yBqv/WR3TrOc152sHZKgNBPSMAu3+6aWfkm6xcP9CdYUUfKG1Amc4bRwnuQe NcVT9Jh/J9UfhMaUw4RrMERl6QvKnspxcwaGAK3cToBOOtwsZ1bVNtom56/UU3i8HLYNO0rwoCq3E M3XX37Mw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh5nH-0000000CXY2-0lz3; Thu, 22 Aug 2024 11:15:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4qM-0000000COGf-3YRN for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2024 10:15:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7F89AFEC; Thu, 22 Aug 2024 03:15:28 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0440B3F66E; Thu, 22 Aug 2024 03:15:00 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER v3 01/10] aarch64: Remove redundant EL1 entry logic Date: Thu, 22 Aug 2024 11:14:32 +0100 Message-Id: <20240822101441.251184-2-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240822101441.251184-1-mark.rutland@arm.com> References: <20240822101441.251184-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_031502_960644_5D078AFA X-CRM114-Status: UNSURE ( 9.63 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org For historical reasons the boot-wrapper has code to handle being entered at Non-secure EL1, but currently this is unsupported and cannot be used to boot a kernel as jump_kernel() unconditionally writes to SCTLR_EL2, which will UNDEF. Remove the logic for handling Non-secure EL1. Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Reviewed-by: Andre Przywara Cc: Akos Denke Cc: Luca Fancellu --- arch/aarch64/boot.S | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index da5fa65..73ddcd0 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -31,10 +31,8 @@ ASM_FUNC(_start) b.eq reset_at_el3 cmp x0, #CURRENTEL_EL2 b.eq reset_at_el2 - cmp x0, #CURRENTEL_EL1 - b.eq reset_at_el1 - /* Booting at EL0 is not supported */ + /* Booting at EL1 or EL0 is not supported */ b . /* @@ -72,19 +70,6 @@ reset_at_el2: msr sctlr_el2, x0 isb - b reset_no_el3 - - /* - * EL1 initialization - */ -reset_at_el1: - mov_64 x0, SCTLR_EL1_RESET - msr sctlr_el1, x0 - isb - - b reset_no_el3 - -reset_no_el3: cpuid x0, x1 bl find_logical_id cmp x0, #MPIDR_INVALID From patchwork Thu Aug 22 10:14:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13773190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72457C3DA4A for ; Thu, 22 Aug 2024 10:24:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ZHTzLYlBJczSbNiy1c+40UCXKgmbK/xe01koCbzWIXI=; b=Xwuo7lvzXcsH9FfgKpaHIA+rDY cX8C7HIWdYCOGXP/SpXjh7MmkDBbe6ZNcqGqn/ZSDYFyiVfWJMOFkFtEbYCnfmb+pQJDEg/Ex+XVu BMM1ediEe5EHucSxlIWjKBUDKUHyhotT6XlvyYjWU8GnHA7S0z1859ltHdq8Yfkei9Y2vZHRFV2kh EIkhJ/bl9ZXwfZ6CjQcn9D6uJCCW5CP4n++h+WqJ8Ue6Q5T3cglmgkjY8EaeDxf5t5dhhDOmrkgh6 HOQvwWDo6xe4H/jI5rdl734gLeFcKl9MXX3VJUG+El6o73s5mryEWt4l7B3NdcsCeXFZf4rsGlHz4 o3SkZIcw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4z0-0000000CPzh-2zsc; Thu, 22 Aug 2024 10:23:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4r7-0000000COHS-0HyK for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2024 10:15:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9DF4B152B; Thu, 22 Aug 2024 03:15:30 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 30EA23F66E; Thu, 22 Aug 2024 03:15:03 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER v3 02/10] aarch64: Implement cpu_init_arch() Date: Thu, 22 Aug 2024 11:14:33 +0100 Message-Id: <20240822101441.251184-3-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240822101441.251184-1-mark.rutland@arm.com> References: <20240822101441.251184-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_031549_224447_771F8F3A X-CRM114-Status: GOOD ( 12.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When the boot-wrapper is entered at EL2 it does not initialise CNTFRQ_EL0, and in future it may need to initialize other CPU state regardless of the exeption level it was entered at. Use a common cpu_init_arch() function to initialize CPU state regardless of the exception level the boot-wrapper was entered at. This change means that the boot-wrapper can only be used when enetered at the highest implemented exception level, as accesses to CNTFRQ_EL0 will be UNDEFINED at lower exception levels. However, the boot-wrapper only supports being booted at the highest implemented exception level, as the comment at the top of boot.S describes: | The boot-wrapper must be entered from the reset vector at the | highest implemented exception level. ... so this should not adversely affect any supported configuration. Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Reviewed-by: Andre Przywara Cc: Akos Denke Cc: Luca Fancellu --- arch/aarch64/boot.S | 4 +++- arch/aarch64/init.c | 12 +++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 73ddcd0..52c617d 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -51,7 +51,7 @@ reset_at_el3: bl cpu_init_bootwrapper - bl cpu_init_el3 + bl cpu_init_arch bl gic_secure_init @@ -82,6 +82,8 @@ reset_at_el2: bl cpu_init_bootwrapper + bl cpu_init_arch + b start_bootmethod err_invalid_id: diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index c9fc7f1..49abdf7 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -52,7 +52,7 @@ static inline bool cpu_has_permission_indirection(void) return mrs(ID_AA64MMFR3_EL1) & mask; } -void cpu_init_el3(void) +static void cpu_init_el3(void) { unsigned long scr = SCR_EL3_RES1 | SCR_EL3_NS | SCR_EL3_HCE; unsigned long mdcr = 0; @@ -153,8 +153,6 @@ void cpu_init_el3(void) msr(SMCR_EL3, smcr); } - - msr(CNTFRQ_EL0, COUNTER_FREQ); } #ifdef PSCI @@ -171,3 +169,11 @@ bool cpu_init_psci_arch(void) return true; } #endif + +void cpu_init_arch(void) +{ + if (mrs(CurrentEL) == CURRENTEL_EL3) + cpu_init_el3(); + + msr(CNTFRQ_EL0, COUNTER_FREQ); +} From patchwork Thu Aug 22 10:14:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13773188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C68F0C3DA4A for ; Thu, 22 Aug 2024 10:21:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BRGYZGWAsRKxoVBkorcLy2yS8clJHeICcoQgGAYJGoA=; b=XVjZsewLfA4JPDpAyVhOERKOlM Iros70xgA8y11RJbIN4bwQxoXUp8vsvD/Xx8j0sZmCQC++PwvlBJN23akJTHFjWPMazMftW0aUuIj SUsiAS907XMhRcUFJWrAZu2IE/QG/g6f9JwlM3C3RO5D+/UGf5W5K6HqcBwYU4qdYSfMDnWfyjSHi vCgR+K49mkz4QY9578N7fg8Xv/3hcgKSa7aV4giF3+9oOQ0Vs26RYuiUQV7VOF4gqRUTtBwYUX+At ehHXuqN6AYV24ZoJI8aPsABRqVfWZ5g5p5i488d2S+KRz5v+R1xhwXhsU7Hxiw2aLEpChclRBb3UC Qb0sF4Ig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4wq-0000000CPUZ-3sW3; Thu, 22 Aug 2024 10:21:44 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4r7-0000000COHg-0ISV for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2024 10:15:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C6C6CDA7; Thu, 22 Aug 2024 03:15:32 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 58C063F66E; Thu, 22 Aug 2024 03:15:05 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER v3 03/10] aarch64: Always enter kernel via exception return Date: Thu, 22 Aug 2024 11:14:34 +0100 Message-Id: <20240822101441.251184-4-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240822101441.251184-1-mark.rutland@arm.com> References: <20240822101441.251184-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_031549_201903_26E5B9D4 X-CRM114-Status: GOOD ( 10.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When the boot-wrapper is entered at EL3 it will enter the kernel via ERET, and when entered at EL2 it will branch to the kernel directly. This is an artifact of the way the boot-wrapper was originally written in assembly, and it would be preferable to always enter the kernel via ERET so that PSTATE is always initialized to a known-good value. Rework jump_kernel() to always enter the kernel via ERET. Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Reviewed-by: Andre Przywara Cc: Akos Denke Cc: Luca Fancellu --- arch/aarch64/boot.S | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 52c617d..7449015 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -76,10 +76,6 @@ reset_at_el2: b.eq err_invalid_id bl setup_stack - mov w0, #1 - ldr x1, =flag_no_el3 - str w0, [x1] - bl cpu_init_bootwrapper bl cpu_init_arch @@ -111,18 +107,11 @@ ASM_FUNC(jump_kernel) bl find_logical_id bl setup_stack // Reset stack pointer - ldr w0, flag_no_el3 - cmp w0, #0 // Prepare Z flag - mov x0, x20 mov x1, x21 mov x2, x22 mov x3, x23 - - b.eq 1f - br x19 // No EL3 - -1: mov x4, #SPSR_KERNEL + mov x4, #SPSR_KERNEL /* * If bit 0 of the kernel address is set, we're entering in AArch32 @@ -130,13 +119,18 @@ ASM_FUNC(jump_kernel) */ bfi x4, x19, #5, #1 + mrs x5, CurrentEL + cmp x5, #CURRENTEL_EL3 + b.eq eret_at_el3 + cmp x5, #CURRENTEL_EL2 + b.eq eret_at_el2 + b . // Not possible + +eret_at_el3: msr elr_el3, x19 msr spsr_el3, x4 eret - - .ltorg - - .data - .align 3 -flag_no_el3: - .long 0 +eret_at_el2: + msr elr_el2, x19 + msr spsr_el2, x4 + eret From patchwork Thu Aug 22 10:14:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13773191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF1CBC5320E for ; Thu, 22 Aug 2024 10:24:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2etk2514+/wLVw/rhkQl69zp97omESjtvg5qtdW2/JA=; b=p8WBJkvfQ1UoS4JKh7TNoZ5zcI BmvdBFUXU86uj8w5c/+3KXT8AS32qmBbYlkf47glFcDp8hTfJ41IwfO8KY3ooEXN5+5qoT2Rh6Ffo 9JOWXUs8BH7eJpnya+KtmdBO44M81pxWmQIwWiCCl/8N6h5AxbsKFyA143+EsPHpEB/qn83lybkys bsr0nPsc+AJ+gfBL1lYBJ0lyMxacc56tV/OwWe7VHRWOmxDhXGJGaB3IWiC2gzvtc9AxvZeelJOsX Es0Z4PKqhsRGuScwAckiLLd5sVzv8r36PVE7AspIr2WIT9yGwPrRp/yrZqXpIVQ3jXjrTUEQdwCh1 qNjGko3A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4zj-0000000CQC0-0k0U; Thu, 22 Aug 2024 10:24:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4r7-0000000COHo-0ImZ for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2024 10:15:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8DFE2FEC; Thu, 22 Aug 2024 03:15:34 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 285793F66E; Thu, 22 Aug 2024 03:15:07 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER v3 04/10] aarch32: Refactor inital entry Date: Thu, 22 Aug 2024 11:14:35 +0100 Message-Id: <20240822101441.251184-5-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240822101441.251184-1-mark.rutland@arm.com> References: <20240822101441.251184-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_031549_222328_DB843941 X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org For historical reasons the early AArch32 code is structured differently from the early AArch64 code, with some common code (including stack setup) performed before we identify the mode we were entered in. Align the structure of the early AArch32 code with that of the early AArch64 code. This will make subsequent refactoring easier. Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Reviewed-by: Andre Przywara Cc: Akos Denke Cc: Luca Fancellu --- arch/aarch32/boot.S | 55 ++++++++++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 21 deletions(-) diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index 4d16c9c..cf83e55 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -31,7 +31,28 @@ * PSCI is not supported when entered in this mode. */ ASM_FUNC(_start) - /* Stack initialisation */ + mrs r0, cpsr + and r0, #PSR_MODE_MASK + cmp r0, #PSR_SVC + beq reset_at_svc + cmp r0, #PSR_HYP + beq reset_at_hyp + + /* Booting at other modes is not supported */ + b . + +reset_at_svc: + /* + * When entered in Secure SVC mode we must switch to monitor mode to + * configure SCR.NS. Switch to monitor mode ASAP to simplify later + * code. + */ + adr lr, reset_at_mon + ldr r0, =(PSR_A | PSR_I | PSR_F | PSR_MON) + msr spsr, r0 + movs pc, lr + +reset_at_mon: cpuid r0, r1 bl find_logical_id cmp r0, #MPIDR_INVALID @@ -39,36 +60,28 @@ ASM_FUNC(_start) bl setup_stack - mrs r0, cpsr - and r0, #PSR_MODE_MASK - - cmp r0, #PSR_HYP - bne _switch_monitor + bl cpu_init_bootwrapper - mov r0, #1 - ldr r1, =flag_no_el3 - str r0, [r1] + bl cpu_init_secure_pl1 - bl cpu_init_bootwrapper + bl gic_secure_init b start_bootmethod -_switch_monitor: - adr lr, _monitor - ldr r0, =(PSR_A | PSR_I | PSR_F | PSR_MON) - msr spsr, r0 - movs pc, lr +reset_at_hyp: + cpuid r0, r1 + bl find_logical_id + cmp r0, #MPIDR_INVALID + beq err_invalid_id -_monitor: - /* Move the stack to Monitor mode*/ - mrs sp, sp_svc + bl setup_stack - bl cpu_init_secure_pl1 + mov r0, #1 + ldr r1, =flag_no_el3 + str r0, [r1] bl cpu_init_bootwrapper - bl gic_secure_init - b start_bootmethod err_invalid_id: From patchwork Thu Aug 22 10:14:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13773189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E710C3DA4A for ; Thu, 22 Aug 2024 10:23:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=iZf1jVAP/2gbwCHTlLOc19t4J1AHTvpDvP6oOGWXHn8=; b=wBdnz8x61vRuIzpDClRxc9szdb uCH0GWFh2QpDpTvs882/xHCCQzfI3SDF9gw4FOnfjs+kO4qg8Huvwv0nNYqliUsXHftvt/ia6pQZT 7Qou+qv5gct2iwEFYndF7TWyfZug8/ozRUjVwDCzrqkFriLCq3FmZ1cJKatMux+NtMcXsMH1VeVCy XKS3yezMfxmLRgaa7A4H/aCElwzIst/afxCXc0GgF1lqwh0z397GMW25f9J9aIOYj62jRRDdEQXTK NE5suR8W3oVYODZKzNJpIdZzFKBfmW7UnaFOw1xfCm0s416JnCNLo0V8MqeAF4CeNzvBqPkfD2DSi XCTiBXPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4yI-0000000CPqh-2GB0; Thu, 22 Aug 2024 10:23:14 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4r7-0000000COI6-0JIG for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2024 10:15:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AFDDE153B; Thu, 22 Aug 2024 03:15:36 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 42B953F66E; Thu, 22 Aug 2024 03:15:09 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER v3 05/10] aarch32: Implement cpu_init_arch() Date: Thu, 22 Aug 2024 11:14:36 +0100 Message-Id: <20240822101441.251184-6-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240822101441.251184-1-mark.rutland@arm.com> References: <20240822101441.251184-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_031549_209443_48952363 X-CRM114-Status: GOOD ( 10.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When the boot-wrapper is entered at EL2/Hyp it does not initialise CNTFRQ, and in future it may need to initialize other CPU state regardless of the exeption level it was entered at. Use a common cpu_init_arch() function to initialize CPU state regardless of the exception level the boot-wrapper was entered at. For clarity cpu_init_secure_pl1() is renamed to cpu_init_monitor(), which better matches PSR_MON and will allow for the addition of cppu_init_hyp() and cpu_init_svc() in future. Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Reviewed-by: Andre Przywara Cc: Akos Denke Cc: Luca Fancellu --- arch/aarch32/boot.S | 4 +++- arch/aarch32/init.c | 12 +++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index cf83e55..f21f89a 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -62,7 +62,7 @@ reset_at_mon: bl cpu_init_bootwrapper - bl cpu_init_secure_pl1 + bl cpu_init_arch bl gic_secure_init @@ -82,6 +82,8 @@ reset_at_hyp: bl cpu_init_bootwrapper + bl cpu_init_arch + b start_bootmethod err_invalid_id: diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c index e25f0c7..35da37c 100644 --- a/arch/aarch32/init.c +++ b/arch/aarch32/init.c @@ -29,7 +29,7 @@ void announce_arch(void) print_string("\r\n"); } -void cpu_init_secure_pl1(void) +static void cpu_init_monitor(void) { unsigned long scr = SCR_NS | SCR_HCE; unsigned long nsacr = NSACR_CP10 | NSACR_CP11; @@ -37,8 +37,6 @@ void cpu_init_secure_pl1(void) mcr(SCR, scr); mcr(NSACR, nsacr); - - mcr(CNTFRQ, COUNTER_FREQ); } #ifdef PSCI @@ -55,3 +53,11 @@ bool cpu_init_psci_arch(void) return true; } #endif + +void cpu_init_arch(void) +{ + if (read_cpsr_mode() == PSR_MON) + cpu_init_monitor(); + + mcr(CNTFRQ, COUNTER_FREQ); +} From patchwork Thu Aug 22 10:14:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13773182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BB71C3DA4A for ; Thu, 22 Aug 2024 10:17:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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This is an artifact of the way the boot-wrapper was originally written in assembly, and it would be preferable to always enter the kernel via an exception return so that PSTATE is always initialized to a known-good value. Rework jump_kernel() to always enter the kernel via an exception return, matching the style of the AArch64 version of jump_kernel() Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Cc: Akos Denke Cc: Andre Przywara Cc: Luca Fancellu Reviewed-by: Andre Przywara --- arch/aarch32/boot.S | 48 +++++++++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index f21f89a..e79aa06 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -76,10 +76,6 @@ reset_at_hyp: bl setup_stack - mov r0, #1 - ldr r1, =flag_no_el3 - str r0, [r1] - bl cpu_init_bootwrapper bl cpu_init_arch @@ -96,9 +92,10 @@ err_invalid_id: * r1-r3, sp[0]: kernel arguments */ ASM_FUNC(jump_kernel) - sub sp, #4 @ Ignore fourth argument - push {r0 - r3} - mov r5, sp + mov r4, r0 + mov r5, r1 + mov r6, r2 + mov r7, r3 ldr r0, =HSCTLR_KERNEL mcr p15, 4, r0, c1, c0, 0 @ HSCTLR @@ -111,23 +108,28 @@ ASM_FUNC(jump_kernel) bl find_logical_id bl setup_stack - ldr lr, [r5], #4 - ldm r5, {r0 - r2} - - ldr r4, =flag_no_el3 - ldr r4, [r4] - cmp r4, #1 - bxeq lr @ no EL3 + mov r0, r5 + mov r1, r6 + mov r2, r7 + ldr r3, =SPSR_KERNEL - ldr r4, =SPSR_KERNEL /* Return in thumb2 mode when bit 0 of address is 1 */ - tst lr, #1 - orrne r4, #PSR_T + tst r4, #1 + orrne r3, #PSR_T + + mrs r5, cpsr + and r5, #PSR_MODE_MASK + cmp r5, #PSR_MON + beq eret_at_mon + cmp r5, #PSR_HYP + beq eret_at_hyp + b . - msr spsr_cxf, r4 +eret_at_mon: + mov lr, r4 + msr spsr_mon, r3 movs pc, lr - - .section .data - .align 2 -flag_no_el3: - .long 0 +eret_at_hyp: + msr elr_hyp, r4 + msr spsr_hyp, r3 + eret From patchwork Thu Aug 22 10:14:38 2024 Content-Type: text/plain; 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bh=DO3qBJM4rt45sow05iHFAeM/vMHHCTmKouIjFc9JpsE=; b=TvlIwrw68O15pSb2L2rMCPRyM7 aUs6Fuvb848RmhxZ1mRF84zEWyul+oboNwQ9x3LUSQoEtJ4cLECmDolL7glXLWtr5dRJjqILIKJWm lDiaJxe1s8cCnOVn0yTW27qu6QCt08wmPia4z0zAJm1dx5JJ4FUJ+N13zHKAZLxa7eh6sUO7Mtrjn clh9xFnDgS8cuHQWwvx6hVT0QxqC8d9fOiNkW/blq/g4N81o124SvPRcfKPZeSYdZUGisa7Sn+MHe oWrgbWZWj2BRzozkK8oBtJ2wTFGn6/GthCF7RL04Eiu3FN+cUmXOFymAOR2atWuINGGG72V7SdEzH WjxqNkCg==; Received: from foss.arm.com ([217.140.110.172]) by desiato.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4qb-00000009u5m-0mt4 for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2024 10:15:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2BC151576; Thu, 22 Aug 2024 03:15:41 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B79993F66E; Thu, 22 Aug 2024 03:15:13 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER v3 07/10] Unify assembly setup paths Date: Thu, 22 Aug 2024 11:14:38 +0100 Message-Id: <20240822101441.251184-8-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240822101441.251184-1-mark.rutland@arm.com> References: <20240822101441.251184-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_111518_125270_DE72C0BC X-CRM114-Status: GOOD ( 17.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The early assembly paths for EL3/Secure-PL1 and EL2/Hyp are almost identical aside from the EL3/Secure-PL1 paths calling gic_secure_init(). Simplify the early assembly paths by conditionally calling gic_secure_init() from cpu_init_arch(), allowing the EL3/Secure-PL1 and EL2/Hyp paths to be unified. In order to call gic_secure_init() from C code we need to expose a prototype for gic_secure_init(), requiring a new header. For clarity the existing headers are renamed to and are included through the common header. Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Reviewed-by: Andre Przywara Cc: Akos Denke Cc: Luca Fancellu --- arch/aarch32/boot.S | 20 ++++++-------------- arch/aarch32/include/asm/{gic-v3.h => gic.h} | 2 +- arch/aarch32/init.c | 5 ++++- arch/aarch64/boot.S | 17 ++++------------- arch/aarch64/include/asm/{gic-v3.h => gic.h} | 2 +- arch/aarch64/init.c | 5 ++++- common/gic-v3.c | 2 +- common/gic.c | 2 +- include/gic.h | 16 ++++++++++++++++ 9 files changed, 38 insertions(+), 33 deletions(-) rename arch/aarch32/include/asm/{gic-v3.h => gic.h} (91%) rename arch/aarch64/include/asm/{gic-v3.h => gic.h} (92%) create mode 100644 include/gic.h diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index e79aa06..cff8291 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -53,22 +53,14 @@ reset_at_svc: movs pc, lr reset_at_mon: - cpuid r0, r1 - bl find_logical_id - cmp r0, #MPIDR_INVALID - beq err_invalid_id - - bl setup_stack - - bl cpu_init_bootwrapper - - bl cpu_init_arch - - bl gic_secure_init - - b start_bootmethod + // TODO initialise monitor state + b reset_common reset_at_hyp: + // TODO initialise hyp state + b reset_common + +reset_common: cpuid r0, r1 bl find_logical_id cmp r0, #MPIDR_INVALID diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic.h similarity index 91% rename from arch/aarch32/include/asm/gic-v3.h rename to arch/aarch32/include/asm/gic.h index b28136a..0b9425d 100644 --- a/arch/aarch32/include/asm/gic-v3.h +++ b/arch/aarch32/include/asm/gic.h @@ -1,5 +1,5 @@ /* - * arch/aarch32/include/asm/gic-v3.h + * arch/aarch32/include/asm/gic.h * * Copyright (C) 2015 ARM Limited. All rights reserved. * diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c index 35da37c..cb67bf6 100644 --- a/arch/aarch32/init.c +++ b/arch/aarch32/init.c @@ -7,6 +7,7 @@ * found in the LICENSE.txt file. */ #include +#include #include #include @@ -56,8 +57,10 @@ bool cpu_init_psci_arch(void) void cpu_init_arch(void) { - if (read_cpsr_mode() == PSR_MON) + if (read_cpsr_mode() == PSR_MON) { cpu_init_monitor(); + gic_secure_init(); + } mcr(CNTFRQ, COUNTER_FREQ); } diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 7449015..5b9634f 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -43,19 +43,7 @@ reset_at_el3: msr sctlr_el3, x0 isb - cpuid x0, x1 - bl find_logical_id - cmp x0, #MPIDR_INVALID - b.eq err_invalid_id - bl setup_stack - - bl cpu_init_bootwrapper - - bl cpu_init_arch - - bl gic_secure_init - - b start_bootmethod + b reset_common /* * EL2 initialization @@ -70,6 +58,9 @@ reset_at_el2: msr sctlr_el2, x0 isb + b reset_common + +reset_common: cpuid x0, x1 bl find_logical_id cmp x0, #MPIDR_INVALID diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic.h similarity index 92% rename from arch/aarch64/include/asm/gic-v3.h rename to arch/aarch64/include/asm/gic.h index 2447480..9d716f6 100644 --- a/arch/aarch64/include/asm/gic-v3.h +++ b/arch/aarch64/include/asm/gic.h @@ -1,5 +1,5 @@ /* - * arch/aarch64/include/asm/gic-v3.h + * arch/aarch64/include/asm/gic.h * * Copyright (C) 2015 ARM Limited. All rights reserved. * diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 49abdf7..68c220b 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -7,6 +7,7 @@ * found in the LICENSE.txt file. */ #include +#include #include #include @@ -172,8 +173,10 @@ bool cpu_init_psci_arch(void) void cpu_init_arch(void) { - if (mrs(CurrentEL) == CURRENTEL_EL3) + if (mrs(CurrentEL) == CURRENTEL_EL3) { cpu_init_el3(); + gic_secure_init(); + } msr(CNTFRQ_EL0, COUNTER_FREQ); } diff --git a/common/gic-v3.c b/common/gic-v3.c index 6207007..4d8e620 100644 --- a/common/gic-v3.c +++ b/common/gic-v3.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include #define GICD_CTLR 0x0 diff --git a/common/gic.c b/common/gic.c index 04d4289..15a3410 100644 --- a/common/gic.c +++ b/common/gic.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include #define GICD_CTLR 0x0 diff --git a/include/gic.h b/include/gic.h new file mode 100644 index 0000000..127f82b --- /dev/null +++ b/include/gic.h @@ -0,0 +1,16 @@ +/* + * include/gic.h + * + * Copyright (C) 2024 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ +#ifndef __GIC_H +#define __GIC_H + +#include + +void gic_secure_init(void); + +#endif From patchwork Thu Aug 22 10:14:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13773184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D52F3C3DA4A for ; Thu, 22 Aug 2024 10:18:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5yJWjHy3h+j3jWPB9kwv/t9wg4XGBgFpVIth36p0MlE=; b=wjV6Rlo2rW3iybu5d5WwFPjrl1 GIOmWi0B91uC2H18jJspqhSkpDui0DiDC6WOCosOTXWNQ3hxcpDqR+ed5IUUFIsPk+x8zQDXbnO0C vfpYh3mg7E7actiupKwsfn+WovpDsI+AP6lzOq3CBOXLGt3c2RuHBED6ViWlIMeKwl3elec+8lQ34 qfpGD3hZQ0EfTyeLqRHsRdEUm5Zin1vGQ1FpaXnK4Zb+aVz9vlLyoUZMLVajX2lFqxtp+8yEUz4+f IzgkusQsdu2z7mSn8o2Ut2jzLCMmH3RucqYSNCYoR50OeH6OCGIDaQeAG1nuu5lbJGnX0EsB1+vQ/ 9ltRttXQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4tv-0000000COkH-1e6s; Thu, 22 Aug 2024 10:18:43 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4qi-0000000COJl-0dQv for linux-arm-kernel@bombadil.infradead.org; Thu, 22 Aug 2024 10:15:24 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=5yJWjHy3h+j3jWPB9kwv/t9wg4XGBgFpVIth36p0MlE=; b=Un2HBoqkmOtsw5h18C1YRa4Ef7 AFkf6ncRSvjfnlu7QMAHU3Ef0dA0Q7qsyNlLvOW2SZGeuBEKDOihoc6DCPlENLd8OB2KKLTUcwRr2 GRTonQS2rQmj+o/ideZ4IGjmnuiVHgCU7jinHOlMCYAdJAMqumzceDB73jo789mb/ztkAfmz6z2t5 GBdNr8e8We9pb8AY1+mQcqZOY5GK7c0IPppcESMyNZ5kyD5CC7sXQuAD5wAhnlncIkPeaa2KAwAH9 8QQZvQjAktAau+fvrgMN7pwBzFsGyiYkHYskP4O9wPImkEM3Mlwktxh6FVrKjnSxFUJlMTGsWXLAY JtJZ9wGA==; Received: from foss.arm.com ([217.140.110.172]) by desiato.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4qe-00000009u6r-1m9P for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2024 10:15:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3FC4F1595; Thu, 22 Aug 2024 03:15:44 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C399F3F66E; Thu, 22 Aug 2024 03:15:16 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER v3 08/10] Simplify spin logic Date: Thu, 22 Aug 2024 11:14:39 +0100 Message-Id: <20240822101441.251184-9-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240822101441.251184-1-mark.rutland@arm.com> References: <20240822101441.251184-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_111520_882436_D6FB59AD X-CRM114-Status: GOOD ( 14.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The logic for initial boot is more complicated than it needs to be, with both first_spin() having a special case for CPU0 that requires an additional argument to be passed to spin(). Simplify this by moving the special-case logic for CPU0 into first_spin(). This removes the need to provide a dummy mailbox for CPU0 to spin on, simplfiies callers of first_spin() and spin(), which no longer need to pass a dummy mailbox or 'is_entry' for CPU0. Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Reviewed-by: Andre Przywara Cc: Akos Denke Cc: Luca Fancellu --- arch/aarch64/spin.S | 16 +--------------- common/boot.c | 20 ++++++++------------ common/psci.c | 2 +- include/boot.h | 2 +- 4 files changed, 11 insertions(+), 29 deletions(-) diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S index 375f732..6597ca1 100644 --- a/arch/aarch64/spin.S +++ b/arch/aarch64/spin.S @@ -18,20 +18,6 @@ ASM_FUNC(cpu_init_bootmethod) ASM_FUNC(start_bootmethod) cpuid x0, x1 bl find_logical_id - - /* - * Primary CPU (x0 = 0) jumps to kernel, the other ones wait for an - * address to appear in mbox - */ - adr x3, mbox - adr x4, kernel_address - cmp x0, #0 - csel x1, x3, x4, ne + adr x1, mbox mov x2, #0 bl first_spin - - .align 3 -kernel_address: - .long 0 - - .ltorg diff --git a/common/boot.c b/common/boot.c index 29d53a4..4417649 100644 --- a/common/boot.c +++ b/common/boot.c @@ -27,7 +27,7 @@ const unsigned long id_table[] = { CPU_IDS }; * @invalid: value of an invalid address, 0 or -1 depending on the boot method * @is_entry: when true, pass boot parameters to the kernel, instead of 0 */ -void __noreturn spin(unsigned long *mbox, unsigned long invalid, int is_entry) +void __noreturn spin(unsigned long *mbox, unsigned long invalid) { unsigned long addr = invalid; @@ -36,13 +36,6 @@ void __noreturn spin(unsigned long *mbox, unsigned long invalid, int is_entry) addr = *mbox; } - if (is_entry) -#ifdef KERNEL_32 - jump_kernel(addr, 0, ~0, (unsigned long)&dtb, 0); -#else - jump_kernel(addr, (unsigned long)&dtb, 0, 0, 0); -#endif - jump_kernel(addr, 0, 0, 0, 0); unreachable(); @@ -60,12 +53,15 @@ void __noreturn first_spin(unsigned int cpu, unsigned long *mbox, unsigned long invalid) { if (cpu == 0) { - *mbox = (unsigned long)&entrypoint; - sevl(); - spin(mbox, invalid, 1); + unsigned long addr = (unsigned long)&entrypoint; +#ifdef KERNEL_32 + jump_kernel(addr, 0, ~0, (unsigned long)&dtb, 0); +#else + jump_kernel(addr, (unsigned long)&dtb, 0, 0, 0); +#endif } else { *mbox = invalid; - spin(mbox, invalid, 0); + spin(mbox, invalid); } unreachable(); diff --git a/common/psci.c b/common/psci.c index 5ae4255..19cc315 100644 --- a/common/psci.c +++ b/common/psci.c @@ -57,7 +57,7 @@ static int psci_cpu_off(void) branch_table[cpu] = PSCI_ADDR_INVALID; - spin(branch_table + cpu, PSCI_ADDR_INVALID, 0); + spin(branch_table + cpu, PSCI_ADDR_INVALID); unreachable(); } diff --git a/include/boot.h b/include/boot.h index 459d1d5..18b805d 100644 --- a/include/boot.h +++ b/include/boot.h @@ -12,7 +12,7 @@ #include #include -void __noreturn spin(unsigned long *mbox, unsigned long invalid, int is_entry); +void __noreturn spin(unsigned long *mbox, unsigned long invalid); void __noreturn first_spin(unsigned int cpu, unsigned long *mbox, unsigned long invalid_addr); From patchwork Thu Aug 22 10:14:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13773185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1082AC3DA4A for ; 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Thu, 22 Aug 2024 10:15:24 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8BA7F1596; Thu, 22 Aug 2024 03:15:46 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2356A3F66E; Thu, 22 Aug 2024 03:15:18 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER v3 09/10] Add printing functions Date: Thu, 22 Aug 2024 11:14:40 +0100 Message-Id: <20240822101441.251184-10-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240822101441.251184-1-mark.rutland@arm.com> References: <20240822101441.251184-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_111522_472278_F54CC595 X-CRM114-Status: UNSURE ( 9.86 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In subsequent patches we'll want to log messages from specific CPUs. Add helpers to make this simpler. Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Reviewed-by: Andre Przywara Cc: Akos Denke Cc: Luca Fancellu --- common/platform.c | 35 +++++++++++++++++++++++++++++++++++ include/platform.h | 4 ++++ 2 files changed, 39 insertions(+) diff --git a/common/platform.c b/common/platform.c index 1607ee6..4e390e1 100644 --- a/common/platform.c +++ b/common/platform.c @@ -65,6 +65,41 @@ void print_ulong_hex(unsigned long val) } } +// 2^32 is 4,294,967,296 +#define DEC_CHARS_PER_UINT 10 + +void print_uint_dec(unsigned int val) +{ + char digits[DEC_CHARS_PER_UINT]; + int d = 0; + + do { + digits[d] = val % 10; + val /= 10; + d++; + } while (val); + + while (d--) { + print_char('0' + digits[d]); + } +} + +void print_cpu_warn(unsigned int cpu, const char *str) +{ + print_string("CPU"); + print_uint_dec(cpu); + print_string(" WARNING: "); + print_string(str); +} + +void print_cpu_msg(unsigned int cpu, const char *str) +{ + print_string("CPU"); + print_uint_dec(cpu); + print_string(": "); + print_string(str); +} + void init_uart(void) { /* diff --git a/include/platform.h b/include/platform.h index c88e124..09712b1 100644 --- a/include/platform.h +++ b/include/platform.h @@ -12,6 +12,10 @@ void print_char(char c); void print_string(const char *str); void print_ulong_hex(unsigned long val); +void print_uint_dec(unsigned int val); + +void print_cpu_warn(unsigned int cpu, const char *str); +void print_cpu_msg(unsigned int cpu, const char *str); void init_uart(void); From patchwork Thu Aug 22 10:14:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13773186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CFDD3C5320E for ; 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Thu, 22 Aug 2024 10:15:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D0D011570; Thu, 22 Aug 2024 03:15:48 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5FF583F66E; Thu, 22 Aug 2024 03:15:21 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER v3 10/10] Boot CPUs sequentially Date: Thu, 22 Aug 2024 11:14:41 +0100 Message-Id: <20240822101441.251184-11-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240822101441.251184-1-mark.rutland@arm.com> References: <20240822101441.251184-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_111523_511401_304E396D X-CRM114-Status: GOOD ( 16.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently the boot-wrapper initializes all CPUs in parallel. This means that we cannot log errors as they happen, as this would mean multiple CPUs concurrently writing to the UART, producing garbled output. To produce meaningful output we have to special-case errors on the boot CPU and hope CPUs have been configured consistently. To make it easier to handle errors, boot CPUs sequentially so that errors can be logged as they happen. With this change it's pretty clear that the cpu_init_bootmethod() abstraction isn't helpful, and so this is removed with cpu_init_arch() directly initializing PSCI where necessary. When things go well this looks like: | Boot-wrapper v0.2 | Entered at EL3 | Memory layout: | [0000000080000000..0000000080001f90] => boot-wrapper | [000000008000fff8..0000000080010000] => mbox | [0000000080200000..0000000082cbaa00] => kernel | [0000000088000000..0000000088002df1] => dtb | CPU0: (MPIDR 0000000000000000) initializing... | CPU1: (MPIDR 0000000000000100) initializing... | CPU2: (MPIDR 0000000000000200) initializing... | CPU3: (MPIDR 0000000000000300) initializing... | CPU4: (MPIDR 0000000000010000) initializing... | CPU5: (MPIDR 0000000000010100) initializing... | CPU6: (MPIDR 0000000000010200) initializing... | CPU7: (MPIDR 0000000000010300) initializing... | All CPUs initialized. Entering kernel... | | [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd0f0] Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Cc: Akos Denke Cc: Andre Przywara Cc: Luca Fancellu Reviewed-by: Andre Przywara --- arch/aarch32/boot.S | 2 -- arch/aarch32/init.c | 17 ++++++++++------ arch/aarch64/boot.S | 2 -- arch/aarch64/init.c | 17 ++++++++++------ arch/aarch64/spin.S | 3 --- common/init.c | 48 ++++++++++++++++++++++++++++++++++++--------- common/psci.c | 14 ------------- include/boot.h | 6 +----- 8 files changed, 62 insertions(+), 47 deletions(-) diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index cff8291..0d9cdc2 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -70,8 +70,6 @@ reset_common: bl cpu_init_bootwrapper - bl cpu_init_arch - b start_bootmethod err_invalid_id: diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c index cb67bf6..d08ac83 100644 --- a/arch/aarch32/init.c +++ b/arch/aarch32/init.c @@ -6,6 +6,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE.txt file. */ +#include #include #include #include @@ -43,24 +44,28 @@ static void cpu_init_monitor(void) #ifdef PSCI extern char psci_vectors[]; -bool cpu_init_psci_arch(void) +static void cpu_init_psci_arch(unsigned int cpu) { - if (read_cpsr_mode() != PSR_MON) - return false; + if (read_cpsr_mode() != PSR_MON) { + print_cpu_warn(cpu, "PSCI could not be initialized (not booted at PL1).\r\n"); + return; + } mcr(MVBAR, (unsigned long)psci_vectors); isb(); - - return true; } +#else +static static void cpu_init_psci_arch(unsigned int cpu) { } #endif -void cpu_init_arch(void) +void cpu_init_arch(unsigned int cpu) { if (read_cpsr_mode() == PSR_MON) { cpu_init_monitor(); gic_secure_init(); } + cpu_init_psci_arch(cpu); + mcr(CNTFRQ, COUNTER_FREQ); } diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 5b9634f..5060a6d 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -69,8 +69,6 @@ reset_common: bl cpu_init_bootwrapper - bl cpu_init_arch - b start_bootmethod err_invalid_id: diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 68c220b..63fa949 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -6,6 +6,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE.txt file. */ +#include #include #include #include @@ -159,24 +160,28 @@ static void cpu_init_el3(void) #ifdef PSCI extern char psci_vectors[]; -bool cpu_init_psci_arch(void) +static void cpu_init_psci_arch(unsigned int cpu) { - if (mrs(CurrentEL) != CURRENTEL_EL3) - return false; + if (mrs(CurrentEL) != CURRENTEL_EL3) { + print_cpu_warn(cpu, "PSCI could not be initialized (not booted at EL3).\r\n"); + return; + } msr(VBAR_EL3, (unsigned long)psci_vectors); isb(); - - return true; } +#else +static void cpu_init_psci_arch(unsigned int cpu) { } #endif -void cpu_init_arch(void) +void cpu_init_arch(unsigned int cpu) { if (mrs(CurrentEL) == CURRENTEL_EL3) { cpu_init_el3(); gic_secure_init(); } + cpu_init_psci_arch(cpu); + msr(CNTFRQ_EL0, COUNTER_FREQ); } diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S index 6597ca1..8089cf9 100644 --- a/arch/aarch64/spin.S +++ b/arch/aarch64/spin.S @@ -12,9 +12,6 @@ .text -ASM_FUNC(cpu_init_bootmethod) - ret - ASM_FUNC(start_bootmethod) cpuid x0, x1 bl find_logical_id diff --git a/common/init.c b/common/init.c index 3c05ac3..5ebccd4 100644 --- a/common/init.c +++ b/common/init.c @@ -43,18 +43,48 @@ static void announce_objects(void) void announce_arch(void); +static void init_bootwrapper(void) +{ + init_uart(); + announce_bootwrapper(); + announce_arch(); + announce_objects(); + init_platform(); +} + +static void cpu_init_self(unsigned int cpu) +{ + print_string("CPU"); + print_uint_dec(cpu); + print_string(": (MPIDR "); + print_ulong_hex(read_mpidr()); + print_string(") initializing...\r\n"); + + cpu_init_arch(cpu); +} + void cpu_init_bootwrapper(void) { + static volatile unsigned int cpu_next = 0; unsigned int cpu = this_cpu_logical_id(); - if (cpu == 0) { - init_uart(); - announce_bootwrapper(); - announce_arch(); - announce_objects(); - print_string("\r\n"); - init_platform(); - } + if (cpu == 0) + init_bootwrapper(); + + while (cpu_next != cpu) + wfe(); + + cpu_init_self(cpu); + + cpu_next = cpu + 1; + dsb(sy); + sev(); + + if (cpu != 0) + return; + + while (cpu_next != NR_CPUS) + wfe(); - cpu_init_bootmethod(cpu); + print_string("All CPUs initialized. Entering kernel...\r\n\r\n"); } diff --git a/common/psci.c b/common/psci.c index 19cc315..5fe8999 100644 --- a/common/psci.c +++ b/common/psci.c @@ -87,17 +87,3 @@ void __noreturn psci_first_spin(void) unreachable(); } - -void cpu_init_bootmethod(unsigned int cpu) -{ - if (cpu_init_psci_arch()) - return; - - if (cpu == 0) { - print_string("WARNING: PSCI could not be initialized. Boot may fail\r\n\r\n"); - return; - } - - while (1) - wfe(); -} diff --git a/include/boot.h b/include/boot.h index 18b805d..12c9c5c 100644 --- a/include/boot.h +++ b/include/boot.h @@ -17,10 +17,6 @@ void __noreturn spin(unsigned long *mbox, unsigned long invalid); void __noreturn first_spin(unsigned int cpu, unsigned long *mbox, unsigned long invalid_addr); -void cpu_init_bootmethod(unsigned int cpu); - -#ifdef PSCI -bool cpu_init_psci_arch(void); -#endif +void cpu_init_arch(unsigned int cpu); #endif