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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:17 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 01/16] clk: renesas: r9a08g045: Add clocks, resets and power domains for USB Date: Thu, 22 Aug 2024 18:27:46 +0300 Message-Id: <20240822152801.602318-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add clocks, resets and power domains for USB modules available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a08g045-cpg.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index a891bfc3ab5a..6e9529678307 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -207,6 +207,10 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9), DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10), DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11), + DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0), + DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1), + DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2), + DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3), DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0), DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0), DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8), @@ -230,6 +234,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), + DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0), + DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1), + DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2), + DEF_RST(R9A08G045_USB_PRESETN, 0x878, 3), DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0), DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1), DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0), @@ -277,6 +285,15 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { DEF_PD("sdhi2", R9A08G045_PD_SDHI2, DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), RZG2L_PD_F_NONE), + DEF_PD("usb0", R9A08G045_PD_USB0, + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), + RZG2L_PD_F_NONE), + DEF_PD("usb1", R9A08G045_PD_USB1, + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)), + RZG2L_PD_F_NONE), + DEF_PD("usb-phy", R9A08G045_PD_USB_PHY, + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)), + RZG2L_PD_F_NONE), DEF_PD("eth0", R9A08G045_PD_ETHER0, DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), RZG2L_PD_F_NONE), From patchwork Thu Aug 22 15:27:47 2024 Content-Type: text/plain; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:19 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 02/16] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Add #reset-cells for RZ/G3S Date: Thu, 22 Aug 2024 18:27:47 +0300 Message-Id: <20240822152801.602318-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ/G3S System controller has registers to control signals that need to be de-asserted/asserted before/after different SoC areas are power on/off. This signals are implemented as reset signals. For this document the #reset-cells property. Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- .../bindings/soc/renesas/renesas,rzg2l-sysc.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml index 4386b2c3fa4d..6b0bb34485d9 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml @@ -42,12 +42,28 @@ properties: - const: cm33stbyr_int - const: ca55_deny + "#reset-cells": + const: 1 + required: - compatible - reg additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a08g045-sysc + then: + required: + - "#reset-cells" + else: + properties: + "#reset-cells": false + examples: - | #include From patchwork Thu Aug 22 15:27:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13773768 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D61191CCEE1 for ; Thu, 22 Aug 2024 15:28:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340506; cv=none; b=gt/GwalNSB59DRPe2CsyTNRGLqUARSn+ajirbjrRDtMSSeK54Rm3xotzAuHTAnHJ+8bmHdg6B5YgCVxW7C18QeEz68Ry4nd0zDfrNtiGtF6ui+T0n80Rq92yPH/OgPbWqoel5OJHnxjLzVVeUtDftbHqOJre7bqu5YLgkzGCkQA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340506; c=relaxed/simple; bh=oUH7C74aUXg4d9WGHoMwZhQPfePjjTPQlokmfgZcYd0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eN+40llWatXRRJB9Nt5TWv53t8DHmtQBOBV9T/Fz0mhj9flVSnbYnrjPSfveleOA2gtweMscXaCo9zBEh/HOa/w/ipKrVIgETOtBucoaM4lmXCXQ4DEs1Qdt7gCWgY7FFWjK9GmcJAZg0kNOWFXLmS+AG6bsuD46QAUCMeIRuv0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=mKqg1pt2; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="mKqg1pt2" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-a7a9185e1c0so93826866b.1 for ; Thu, 22 Aug 2024 08:28:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724340502; x=1724945302; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3txPUwxmR4fX7LzFPWhcfk9alhQ/U1SsqoBALbg0+o8=; b=mKqg1pt2CZoeMwJSMruM8a17QtgxTEL/9SW2A8WWiIiBytZ0TE5SJFBmXExsU4b4o8 5Jj64i2giRaz7mnQdzHI09fR0Xud9AmUB/N9Y23AHXTLJm4K07WksJgUel67snJUyzGf 6KQ2ZjTI/fn3x2zn0nopq8djlkXlLb5H6Auw/+qSBpCY1SpfggSL6T42xMfl6X3eQ2lj MPJrPPW/USTI1VdKjHYf8kqSwYKlLKK9W27sVOkrJd+O9RejkWYYd9W4Istu5XKEv2kW 7KOdagtfDbjKhdOdPL9MMSGu9Kdnf/wIWHHo4XVXy+r2W/ZpgcXAelfUdATU+P857P1d 9g4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724340502; x=1724945302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3txPUwxmR4fX7LzFPWhcfk9alhQ/U1SsqoBALbg0+o8=; b=JZmOo1qIiM+Xk6m7bAV1iNOgGdwNjdXHgs6edv+IePynfX1T1vAo3dGbyvFLxQjsNb BJ47RKx3yR/VRgq6HeRJyaCAJzOuWvfRvPgYBzmvAieTLkPMeStL/Md/QejR/+vsGVSf JwryHi1wbljyK2WrWth6GSxk0yuKosBHg/S0sgeSKH3HNdDt/K1lB+FQt6M7KJZ0jNtE G/h4LUQ2oMfGOzLvL+SlAemiSOiR0cdi8GEMzfqMR2EsuinMOR3H9dWVJ/2Agyo/HYB7 AUgexN61SeKULSq6xOo3g2rR7X4G3gTcUoOOGHzC4mHtP4p/lYqXTzMaHYFVmTdnYqdJ Mj1A== X-Forwarded-Encrypted: i=1; AJvYcCWEQlI12OXDmkKjn2I8N5nS4ny90aKcMn47bid44iFJEhKxURoPIoQ1PHZpzIJFwNVZG1nOXEkyf3Q=@vger.kernel.org X-Gm-Message-State: AOJu0YwWNk4LtWQkJuxBKH+GudxCxUxO/+42rVtRbxI4C8ONcEl8m7jS jLQHs/usTNcmz6fpuxEgtElCf59979VEhhRCLrqvCxZoSI0YEAHTQ0Oc0Is1gOU= X-Google-Smtp-Source: AGHT+IGwmGUufY0I/wXnuKumGBXx6MTOJSx969Oopy4E3RE8Z417JclZShJ68eMp0wCAWKbVhUr4SA== X-Received: by 2002:a17:907:efd2:b0:a86:3c01:cf08 with SMTP id a640c23a62f3a-a866f705025mr477276566b.47.1724340502213; Thu, 22 Aug 2024 08:28:22 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:21 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 03/16] dt-bindings: reset: renesas,r9a08g045-sysc: Add reset IDs for RZ/G3S SYSC reset Date: Thu, 22 Aug 2024 18:27:48 +0300 Message-Id: <20240822152801.602318-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add reset IDs for the Renesas RZ/G3S SYSC reset controller driver. Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- include/dt-bindings/reset/renesas,r9a08g045-sysc.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 include/dt-bindings/reset/renesas,r9a08g045-sysc.h diff --git a/include/dt-bindings/reset/renesas,r9a08g045-sysc.h b/include/dt-bindings/reset/renesas,r9a08g045-sysc.h new file mode 100644 index 000000000000..675872a32121 --- /dev/null +++ b/include/dt-bindings/reset/renesas,r9a08g045-sysc.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_RESET_R9A08G045_SYSC_H +#define __DT_BINDINGS_RESET_R9A08G045_SYSC_H + +#define R9A08G045_SYSC_RESET_USB 0 +#define R9A08G045_SYSC_RESET_PCIE 1 + +#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ + From patchwork Thu Aug 22 15:27:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13773769 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 138911CDA18 for ; Thu, 22 Aug 2024 15:28:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340508; cv=none; b=PUVgzU3qoi8mg216zXgV0ERDylO/IT/LWsUw6KL6PKMEnfTe03gE2Jep72+QirB6ToJWgBhtb4jQ5JbfD88ACnt+Yw1mQfu85/IA5Yz8+9EpTBVLPfBLfXcrgM+Jxg+gIT84hwFPdaGFA+pzDmAFm5GGP4++ICmNdQjH8qEWnIY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340508; c=relaxed/simple; bh=+npf8sqx1TsaaMkEzhbJBWj+d9glTP2f3WsOgcb1NU4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TP/ekgh3yL3Mr9IrwW5rvy78acEzjglNgwe2wCjp+qCEqzEcwXNDauDO9oxIMDAXltEYNBlqnIJ13l/vz4W9Ka9ODdpPdRjQgA0oik58PI6SoxVntGUl2zfrqTW0eRclNVfLVnhvP0VWQv7D9KJKxfUru1DrbpSARsU9eqVPZ38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=P+n1/efy; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="P+n1/efy" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a868d7f92feso131439266b.2 for ; Thu, 22 Aug 2024 08:28:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724340504; x=1724945304; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+9DOBqvnZ/STjSdrebzztVFaplbBr0hBrOhxjpVMxCw=; b=P+n1/efy9JMGmwSBitQv4YqwYu4KAbPb1QMyVtTRxtQMXY8nItoc8J6oZSJnyGABD7 G9LdGSwh8Zz3WagfqrUUB17Y8w9YTGXzrW+c9cnDAtH5ldcGM0CkRArJ0W+HakrLxAmt RXd6tkxTlQ24c1n45yk/xCrvVm0lrCYzFDVC3hdaLViEf9xQAqWqo7VOVC5oxQMyECiM I3r17W1j9Isf30+J7p8C1FSZlQh4eoViHoi6BUQhXUckXy3KWYWP3Y/NpGXERjaSfAIm t/FtFx+qSKfl5R/toR3gtaontt4gLnxIMMj6mctEXgRo89Fyg5+dYfxcFW6Tls06lbw2 o4Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724340504; x=1724945304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+9DOBqvnZ/STjSdrebzztVFaplbBr0hBrOhxjpVMxCw=; b=K1d4aNugBpDSakKL652oK4BNpNfk/fDk3cphaK5thRx/JSI8640/mB/uzcsrrbneDz EZWq9rZqMb4ZfmWPgXXSjvJScqKNxjKqqNnQ1fP8KHu+8p8jo8jFtH2kk/JGCmFTVJeT g79mTr8hADMnisi8ZDXm9fU9qt7tjsVXBWpY9BcO2p/hWwzobV41AhXoKoTyBgU/GhY8 F7Kmx0Oo1/bKvOE8lZMNvp2CGudNfTeHU6Dye1yI9nIAbrTzSiNL6zz5U7QsbG1J/DiD CHsY7pPVm2gn6R5dT4cG6y5Dt3ki5lQ50dJIPY/xhiX4ikoQKvkX6N4PogX9M7OwKCd0 uaSA== X-Forwarded-Encrypted: i=1; AJvYcCXSNWQow46O8yDTqOMJyRquZPI5MdnHZ8q/xHDZQBM8+exxbfqxADNbEnUlnX1q9N4sjscoYZugkVY=@vger.kernel.org X-Gm-Message-State: AOJu0YwNJ9tpuLwWKxm1wPNiizYDhw031l24s2dtjvKLRxdTw4txmNZ9 /GDISuM349jvyQMvFNv5wvDO2vi86NsSNkxpT6U2nqFNY/5LJ8uMrKZAj3URJw0= X-Google-Smtp-Source: AGHT+IFlSIRkRZTOFLNyPatfUw5Y174bZy9lMxma4FnpCObFSnO03fmX9lo7w0eBmJXtveDmWb0cnA== X-Received: by 2002:a17:907:7f25:b0:a7a:b561:3564 with SMTP id a640c23a62f3a-a8691cb98f9mr188865766b.61.1724340504353; Thu, 22 Aug 2024 08:28:24 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:23 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 04/16] soc: renesas: Add SYSC driver for Renesas RZ/G3S Date: Thu, 22 Aug 2024 18:27:49 +0300 Message-Id: <20240822152801.602318-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ/G3S SYS Controller has 2 registers (one for PCIE one for USB) that need to be configured before/after powering off/on the PCI or USB ares. The bits in these registers control signals to PCIE and USB that need to be de-asserted/asserted after/before power on/off event. For this add SYSC controller driver that registers a reset controller driver on auxiliary bus which allows USB, PCIE drivers to control these signals. Signed-off-by: Claudiu Beznea --- Hi, Philipp, Ulf, Geert, all, In this series the control of USB and PCIE signals was implemented though a reset control driver. This approach was chosen as a result of looking though the HW manual and trying to understand how these signals behave. HW manual can be downloaded from [1] (download manual hardware button -> confirm -> extract archive -> Deliverables -> r01uh1014ej0110-rzg3s.pdf). The description of the USB and PCIE control registers is as follows: SYS_USB_PWRRDY Register (Signal is called PWRRDY), Chapter 6.3.83: Controls PWRRDY terminal of USB: 0: PWRRDY 1: PWRRDY down When turning off the USB region power, set this bit to 1. When turning on the USB region power, set this bit to 0. SYS_PCIE_RST_RSM_B (Signal is called RST_RSM_B), Chapter 6.3.84: Controls RST_RSM_B terminal of PCIe 0: RST_RSM_B=0 1: RST_RSM_B=1 Set RST_RSM_B=1 after PCIe power is applied. When the power in the PCIe region is turned off, set RST_RSM_B=0 before turning off the power supply. From this description I understood that the control of the USB PWRRDY, PCIE RST_RSM_B signals and the power control for the domains the USB, PCI belongs are different things [A]. As of Figure 41.1 (Power Domain and Power Supply) and Table 41.1 (Power Domain to which Power Supply Pins Belong) the USB and PCIE belongs to PD_ISOVCC power domain controlled though PMIC [B]. The USB, PCI signals are also reference in HW manual in the low power consumption chapter describing the transition to different power modes. E.g., chapter 41.6.1 (ALL_ON to VBATT), Table 41.8 (Example Transition Flow Outline from ALL_ON Mode to VBATT Mode) says at steps 6 and 7: 6. USB PHY PWRRDY signal control (if using USB) SYS_USB_PWRRDY 7. PCIe RST_RSM_B signal control (if using PCIe) SYS_PCIE_RST_RSM_B Meaning these signals need to be controlled before going to VBATT power mode (where the power supply to USB is turned off) [C]. Due to [A], [B] and [C] I chosed to have the implementation of these signals though a reset control driver. Other option I explored was though power domains as follows: 1/ registering one domain for USB, one of PCIE 2/ passed the domain ID to USB though device tree 3/ attach from USB PHY control driver to the USB power domain with dev_pm_domain_attach_by_name() 4/ and controlling the SYSC registers with pm_runtime_resume_and_get(usb_sysc_domain). Please let me know what do you think about this! Thank you, Claudiu Beznea [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250 drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-rzg3s-sysc.c | 140 +++++++++++++++++++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/rzg3s-sysc.c | 113 +++++++++++++++ include/linux/soc/renesas/rzg3s-sysc-reset.h | 24 ++++ 6 files changed, 286 insertions(+) create mode 100644 drivers/reset/reset-rzg3s-sysc.c create mode 100644 drivers/soc/renesas/rzg3s-sysc.c create mode 100644 include/linux/soc/renesas/rzg3s-sysc-reset.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 67bce340a87e..fbdf860b2293 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -218,6 +218,13 @@ config RESET_RZG2L_USBPHY_CTRL Support for USBPHY Control found on RZ/G2L family. It mainly controls reset and power down of the USB/PHY. +config RESET_RZG3S_SYSC + tristate "Renesas RZ/G3S SYSC reset driver" + depends on ARCH_R9A08G045 || COMPILE_TEST + help + Support for SYSC reset found on RZ/G3S family. It mainly + controls reset on USB and PCIE. + config RESET_SCMI tristate "Reset driver controlled via ARM SCMI interface" depends on ARM_SCMI_PROTOCOL || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 27b0bbdfcc04..ee5ca21acc44 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o +obj-$(CONFIG_RESET_RZG3S_SYSC) += reset-rzg3s-sysc.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git a/drivers/reset/reset-rzg3s-sysc.c b/drivers/reset/reset-rzg3s-sysc.c new file mode 100644 index 000000000000..56af03f1d8a2 --- /dev/null +++ b/drivers/reset/reset-rzg3s-sysc.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G3S SYSC reset driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define RZG3S_SYSC_USB_PWRRDY 0xd70 +#define RZG3S_SYSC_PCIE_RST_RSM_B 0xd74 +#define RZG3S_SYSC_RESET_MASK 0x1 + +/** + * struct rzg3s_sysc_reset_info - SYSC reset information + * @offset: offset to configure the reset + * @assert_val: value to write to register on assert + * @deassert_val: value to write to register on de-assert + */ +struct rzg3s_sysc_reset_info { + u16 offset; + u8 assert_val; + u8 deassert_val; +}; + +/** + * struct rzg3s_sysc_reset - SYSC reset + * @info: SYSC reset information + * @radev: SYSC reset auxiliary device + * @rcdev: reset controller device + */ +struct rzg3s_sysc_reset { + const struct rzg3s_sysc_reset_info *info; + struct rzg3s_sysc_reset_adev *radev; + struct reset_controller_dev rcdev; +}; + +#define to_rzg3s_sysc_reset(r) container_of(r, struct rzg3s_sysc_reset, rcdev) + +static int rzg3s_sysc_reset_set(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct rzg3s_sysc_reset *reset = to_rzg3s_sysc_reset(rcdev); + struct rzg3s_sysc_reset_adev *radev = reset->radev; + struct rzg3s_sysc_reset_info info = reset->info[id]; + unsigned long flags; + u32 tmp; + + spin_lock_irqsave(radev->lock, flags); + tmp = readl(radev->base + info.offset); + tmp &= ~RZG3S_SYSC_RESET_MASK; + tmp |= assert ? info.assert_val : info.deassert_val; + writel(tmp, radev->base + info.offset); + spin_unlock_irqrestore(radev->lock, flags); + + return 0; +} + +static int rzg3s_sysc_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return rzg3s_sysc_reset_set(rcdev, id, true); +} + +static int rzg3s_sysc_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return rzg3s_sysc_reset_set(rcdev, id, false); +} + +static int rzg3s_sysc_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzg3s_sysc_reset *reset = to_rzg3s_sysc_reset(rcdev); + const struct rzg3s_sysc_reset_info info = reset->info[id]; + struct rzg3s_sysc_reset_adev *radev = reset->radev; + u32 tmp; + + tmp = readl(radev->base + info.offset); + tmp = !!(tmp & RZG3S_SYSC_RESET_MASK); + + return info.assert_val ? tmp : !tmp; +} + +static const struct reset_control_ops rzg3s_sysc_reset_ops = { + .assert = rzg3s_sysc_reset_assert, + .deassert = rzg3s_sysc_reset_deassert, + .status = rzg3s_sysc_reset_status, +}; + +static const struct rzg3s_sysc_reset_info rzg3s_sysc_reset_info[] = { + [R9A08G045_SYSC_RESET_USB] = { + .offset = RZG3S_SYSC_USB_PWRRDY, .assert_val = 1, .deassert_val = 0 + }, + [R9A08G045_SYSC_RESET_PCIE] = { + .offset = RZG3S_SYSC_PCIE_RST_RSM_B, .assert_val = 0, .deassert_val = 1 + }, +}; + +static int rzg3s_sysc_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct rzg3s_sysc_reset_adev *reset_adev = to_rzg3s_sysc_reset_adev(adev); + struct device *dev = &adev->dev; + struct rzg3s_sysc_reset *reset; + + reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + reset->radev = reset_adev; + reset->info = rzg3s_sysc_reset_info; + + reset->rcdev.ops = &rzg3s_sysc_reset_ops; + reset->rcdev.of_reset_n_cells = 1; + reset->rcdev.nr_resets = ARRAY_SIZE(rzg3s_sysc_reset_info); + reset->rcdev.of_node = dev->parent->of_node; + reset->rcdev.dev = dev; + + return devm_reset_controller_register(dev, &reset->rcdev); +} + +static const struct auxiliary_device_id rzg3s_sysc_reset_ids[] = { + { .name = "rzg3s_sysc.reset" }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, rzg3s_sysc_reset_ids); + +static struct auxiliary_driver rzg3s_sysc_reset_driver = { + .probe = rzg3s_sysc_reset_probe, + .id_table = rzg3s_sysc_reset_ids, +}; +module_auxiliary_driver(rzg3s_sysc_reset_driver); diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 734f8f8cefa4..74c72ac46f91 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif +obj-$(CONFIG_ARCH_R9A08G045) += rzg3s-sysc.o # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o diff --git a/drivers/soc/renesas/rzg3s-sysc.c b/drivers/soc/renesas/rzg3s-sysc.c new file mode 100644 index 000000000000..e664d29ce5c3 --- /dev/null +++ b/drivers/soc/renesas/rzg3s-sysc.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3S System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include + +#include + +/** + * struct rzg3s_sysc - SYSC private data structure + * @base: base address + * @dev: device + * @lock: lock + */ +struct rzg3s_sysc { + void __iomem *base; + struct device *dev; + spinlock_t lock; +}; + +static void rzg3s_sysc_reset_adev_release(struct device *dev) +{ + struct auxiliary_device *adev = to_auxiliary_dev(dev); + struct rzg3s_sysc_reset_adev *reset_adev = to_rzg3s_sysc_reset_adev(adev); + + kfree(reset_adev); +} + +static void rzg3s_sysc_reset_unregister_adev(void *adev) +{ + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static int rzg3s_sysc_reset_probe(struct rzg3s_sysc *sysc, const char *adev_name, + u32 adev_id) +{ + struct rzg3s_sysc_reset_adev *radev; + struct auxiliary_device *adev; + int ret; + + radev = kzalloc(sizeof(*radev), GFP_KERNEL); + if (!radev) + return -ENOMEM; + + radev->base = sysc->base; + radev->lock = &sysc->lock; + + adev = &radev->adev; + adev->name = adev_name; + adev->dev.parent = sysc->dev; + adev->dev.release = rzg3s_sysc_reset_adev_release; + adev->id = adev_id; + + ret = auxiliary_device_init(adev); + if (ret) + return ret; + + ret = auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + return devm_add_action_or_reset(sysc->dev, rzg3s_sysc_reset_unregister_adev, adev); +} + +static int rzg3s_sysc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rzg3s_sysc *sysc; + + sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); + if (!sysc) + return -ENOMEM; + + sysc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sysc->base)) + return PTR_ERR(sysc->base); + + sysc->dev = dev; + spin_lock_init(&sysc->lock); + + return rzg3s_sysc_reset_probe(sysc, "reset", 0); +} + +static const struct of_device_id rzg3s_sysc_match[] = { + { .compatible = "renesas,r9a08g045-sysc" }, + { } +}; +MODULE_DEVICE_TABLE(of, rzg3s_sysc_match); + +static struct platform_driver rzg3s_sysc_driver = { + .driver = { + .name = "renesas-rzg3s-sysc", + .of_match_table = rzg3s_sysc_match + }, + .probe = rzg3s_sysc_probe +}; + +static int __init rzg3s_sysc_init(void) +{ + return platform_driver_register(&rzg3s_sysc_driver); +} +subsys_initcall(rzg3s_sysc_init); + +MODULE_DESCRIPTION("Renesas RZ/G3S System Controller Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); diff --git a/include/linux/soc/renesas/rzg3s-sysc-reset.h b/include/linux/soc/renesas/rzg3s-sysc-reset.h new file mode 100644 index 000000000000..813cbe82a68a --- /dev/null +++ b/include/linux/soc/renesas/rzg3s-sysc-reset.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __SOC_RENESAS_SYSC_RESET_RZG3S_H +#define __SOC_RENESAS_SYSC_RESET_RZG3S_H + +#include +#include +#include + +/** + * struct rzg3s_sysc_reset_adev - SYSC reset auxiliary device + * @base: base address + * @lock: lock + * @adev: auxiliary device + */ +struct rzg3s_sysc_reset_adev { + void __iomem *base; + spinlock_t *lock; + struct auxiliary_device adev; +}; + +#define to_rzg3s_sysc_reset_adev(a) container_of(a, struct rzg3s_sysc_reset_adev, adev) + +#endif From patchwork Thu Aug 22 15:27:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13773770 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16A1F1CDA33 for ; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:25 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 05/16] soc: renesas: sysc: Move RZ/G3S SoC detection on SYSC driver Date: Thu, 22 Aug 2024 18:27:50 +0300 Message-Id: <20240822152801.602318-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Now that we have a driver for SYSC driver for RZ/G3S move the SoC detection for RZ/G3S in SYSC driver. Signed-off-by: Claudiu Beznea --- drivers/soc/renesas/renesas-soc.c | 12 --------- drivers/soc/renesas/rzg3s-sysc.c | 45 +++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 12 deletions(-) diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 172d59e6fbcf..425d9037dcd0 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -71,10 +71,6 @@ static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = { .name = "RZ/G2UL", }; -static const struct renesas_family fam_rzg3s __initconst __maybe_unused = { - .name = "RZ/G3S", -}; - static const struct renesas_family fam_rzv2h __initconst __maybe_unused = { .name = "RZ/V2H", }; @@ -176,11 +172,6 @@ static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = { .id = 0x8450447, }; -static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = { - .family = &fam_rzg3s, - .id = 0x85e0447, -}; - static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = { .family = &fam_rzv2h, .id = 0x847a447, @@ -410,9 +401,6 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R9A07G054 { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, #endif -#ifdef CONFIG_ARCH_R9A08G045 - { .compatible = "renesas,r9a08g045", .data = &soc_rz_g3s }, -#endif #ifdef CONFIG_ARCH_R9A09G011 { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, #endif diff --git a/drivers/soc/renesas/rzg3s-sysc.c b/drivers/soc/renesas/rzg3s-sysc.c index e664d29ce5c3..1dd48c7255d1 100644 --- a/drivers/soc/renesas/rzg3s-sysc.c +++ b/drivers/soc/renesas/rzg3s-sysc.c @@ -6,10 +6,16 @@ */ #include +#include +#include #include +#include #include +#define RZG3S_SYS_LSI_DEVID 0xa04 +#define RZG3S_SYS_LSI_DEVID_REV GENMASK(31, 28) + /** * struct rzg3s_sysc - SYSC private data structure * @base: base address @@ -71,8 +77,14 @@ static int rzg3s_sysc_reset_probe(struct rzg3s_sysc *sysc, const char *adev_name static int rzg3s_sysc_probe(struct platform_device *pdev) { + const char *soc_id_start, *soc_id_end, *compatible; + struct soc_device_attribute *soc_dev_attr; struct device *dev = &pdev->dev; + struct soc_device *soc_dev; struct rzg3s_sysc *sysc; + char soc_id[32] = {0}; + u32 devid, revision; + u8 size; sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); if (!sysc) @@ -85,6 +97,39 @@ static int rzg3s_sysc_probe(struct platform_device *pdev) sysc->dev = dev; spin_lock_init(&sysc->lock); + compatible = of_get_property(dev->of_node, "compatible", NULL); + if (!compatible) + return -ENODEV; + + soc_id_start = strchr(compatible, ',') + 1; + soc_id_end = strchr(compatible, '-'); + size = soc_id_end - soc_id_start; + if (size > 32) + size = 32; + strscpy(soc_id, soc_id_start, size); + + soc_dev_attr = devm_kzalloc(dev, sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = "RZ/G3S"; + soc_dev_attr->soc_id = devm_kstrdup(dev, soc_id, GFP_KERNEL); + if (!soc_dev_attr->soc_id) + return -ENOMEM; + + devid = readl(sysc->base + RZG3S_SYS_LSI_DEVID); + revision = FIELD_GET(RZG3S_SYS_LSI_DEVID_REV, devid); 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:27 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 06/16] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S SoC Date: Thu, 22 Aug 2024 18:27:51 +0300 Message-Id: <20240822152801.602318-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Document the Renesas RZ/G3S USB PHY Control IP. This is similar with the one found on the RZ/G2L SoC the exception being that the SYSC USB specific signal need to be configured before accessing the USB area. This is done though a reset signal. Signed-off-by: Claudiu Beznea Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 35 +++++++++++++++---- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml index b0b20af15313..5f053981474e 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -15,12 +15,15 @@ description: properties: compatible: - items: - - enum: - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five - - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} - - renesas,r9a07g054-usbphy-ctrl # RZ/V2L - - const: renesas,rzg2l-usbphy-ctrl + oneOf: + - const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S + + - items: + - enum: + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L + - const: renesas,rzg2l-usbphy-ctrl reg: maxItems: 1 @@ -29,7 +32,8 @@ properties: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 power-domains: maxItems: 1 @@ -59,6 +63,23 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a08g045-usbphy-ctrl + then: + properties: + resets: + items: + - description: USB PHY Control module reset + - description: USB area reset + else: + properties: + resets: + maxItems: 1 + examples: - | #include From patchwork Thu Aug 22 15:27:52 2024 Content-Type: text/plain; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:30 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 07/16] reset: rzg2l-usbphy-ctrl: Get reset control array Date: Thu, 22 Aug 2024 18:27:52 +0300 Message-Id: <20240822152801.602318-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Before accessing the USB area of the RZ/G3S SoC the PWRRDY bit of the SYS_USB_PWRRDY register need to be cleared. When USB area is not used the PWRRDY bit of the SYS_USB_PWRRDY register need to be set. This register is in the SYSC controller address space and the assert/de-assert of the signal handled by SYSC_USB_PWRRDY was implemented as a reset signal. The USB modules available on the RZ/G3S SoC that need this bit set are: - USB ch0 (supporting host and peripheral mode) - USB ch2 (supporting host mode) - USBPHY control As the USBPHY control is the root device for all the other USB channels (USB ch0, USB ch1) add support to set the PWRRDY for the USB area when initializing the USBPHY control. As this is done though reset signals get the reset array in the USBPHY control driver. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/reset/reset-rzg2l-usbphy-ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c index 1cd157f4f03b..8b64c12f3bec 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -132,7 +132,7 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); + priv->rstc = devm_reset_control_array_get_exclusive(&pdev->dev); if (IS_ERR(priv->rstc)) return dev_err_probe(dev, PTR_ERR(priv->rstc), "failed to get reset\n"); From patchwork Thu Aug 22 15:27:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13773773 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D23D1CEACF for ; Thu, 22 Aug 2024 15:28:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340516; cv=none; b=lEClh9lKSHIpE2+k56/VYFvfZu1xXoFAKLXNlzHsRcJvPXKdFrhSoZzGxU6Oq3VDKMq2EDzu6dFlwOtst6Kn4A82mOa39iiLqFRHhXXOG5TgRPT1/0NUwO2TXPiOu+0wMv80w0Qc0CfXKeMAqvJijhaJq0WrTPUyaHCLJOEujoE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340516; c=relaxed/simple; bh=hwOPs3VjSqv+5Z5VfJP9Z8BIWsDCu8awKAb11KLvGp0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QH0UrXmR9ujS2NcsAwj27JO9bCEAxaDNVevSpsnMfuZgwxyK/MexoBpSLzFR+t4f1MZUQpp8+C2nSVz24K8a5+BVUaoA40Qnfc/Dz2JKeqtAMbLRJ7Fg5fh/8bSDI698f2dGAAouyu6JUCasQpAlwbFzZa2V2tbALbb2IletPQE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=nbD3wSrD; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="nbD3wSrD" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-a868831216cso129485266b.3 for ; Thu, 22 Aug 2024 08:28:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724340512; x=1724945312; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gkWgitHhldKdeisz33EiZdlfuv0bPsRGbcOFCT+k5gc=; b=nbD3wSrDmsDg6iwBHl98KBRcXrkXuv9bk0T33rtiyr0E+YQD+/Dp9bI2YgBrEj/GSJ AV7dasG/x9B1OPIdaiJ4WePATHqQ/xLQUN9kMrz4O3v+UqBJveYqR80uo9yagMYkmy+S dPXXDnCE4XtB9xr5Gr6FdHLDqwzoRzUC+/REiU88a+cpjHAxboR/L2sVMNwi3Pat+Zsa MfWyemeoLB3B6dN1RSV/dHonudhBsvFF+ICTyn68w2j12cTKuLh/e6soTnt4pN+ZN6Vf y1i7IE0tX4kwM1atst8ZfxkOYFpHb5DaeUltWiHA6BSXz9rl7HQ1QchHIj2hxcrHxkqf hryw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724340512; x=1724945312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gkWgitHhldKdeisz33EiZdlfuv0bPsRGbcOFCT+k5gc=; b=jDAZ60L29RKwTLQXjo/hmiTFGGnUR9q/qOuPwZ6HgY+y69jg2bZxxRBoLIED3Gat3E XRoX9o7c9tbQBiuBd2q6D6gnuqvWYcZLEw4CkrmEglRUeqit1pKZswQAry7ZgnFLaoUY KoVn3is1FhV0eX3kj/Fu/JpCZ+udJcK6OyKj3jatwcr5fopJ48WyivSqf6/iaE8Hg8R/ ajwMzpe8vDqFOtZibSzDp4ZW6dw9K4KN+bGZxlyDhkn66dlkmX6KdVk6cTqtwZYVd1X9 A5gk3t2vcjx/OPQ6ImWdH+pnNy/Op0gLf0aMGFO/2NvGkgg2pLJxy1q/+bQaMTFthUUh rXMw== X-Forwarded-Encrypted: i=1; AJvYcCWu5+ADIVLTs5NePz8P9w6W1Efvf2/n+Yrf4U5pLWCCkaLlJf7cSLVIh/kglWBjK64Y8Dk2Mt8UCs8=@vger.kernel.org X-Gm-Message-State: AOJu0YyNkHy9zslDwHEvPwp0yrRVVLVh73libnHhL9h7CAAllr1uSKww /jF2xYJje1yAp2IBm0q/GM/lTRmzzjirPUHuuQqs4Bl6z+KmeF6PW3nZaz/oV7Y= X-Google-Smtp-Source: AGHT+IFEWPJ3HqQL/w0KWFEJhV07xF/eMg4mv7Lejm46+5JkTivmt8Z+5f8B5VhGhYYih3FlUFQvOQ== X-Received: by 2002:a17:907:980e:b0:a86:9258:aeed with SMTP id a640c23a62f3a-a869258b023mr191608966b.61.1724340512413; Thu, 22 Aug 2024 08:28:32 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:32 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 08/16] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S Date: Thu, 22 Aug 2024 18:27:53 +0300 Message-Id: <20240822152801.602318-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add support for RZ/G3S SoC. It needs its own compatible as it uses 2 reset signals and it cannot work w/o both of them. To be able to fully validate this on DT schema, too, the RZ/G3S uses it's own compatible w/o a fallback (as if the fallback will be used the RZ/G3S will not work anyway). Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/reset/reset-rzg2l-usbphy-ctrl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c index 8b64c12f3bec..08b18d7de7ad 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -93,6 +93,7 @@ static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev, static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = { { .compatible = "renesas,rzg2l-usbphy-ctrl" }, + { .compatible = "renesas,r9a08g045-usbphy-ctrl" }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table); From patchwork Thu Aug 22 15:27:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13773774 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3BFE1CEADF for ; Thu, 22 Aug 2024 15:28:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340517; cv=none; b=B3ZNMtNUx90VG3d+mLp8+N+HhJPxB5Zl5aNxJxPywmwUyskRHv6u4IF/0AtnnLC8w9oV9LIOU2i5wrQq9svVAbvUcKshmtNroOox3IMwx5wkrELNTzMU4ZByYdT0BiYXFt4cJ8cRA+HofV4DZ+TUeyjf5MaeAZ3A5abEP9WEJ3I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340517; c=relaxed/simple; bh=mG2HhfWd8qCb8fqq+XG4F4xVuNxXzEDJIM8/ycCUv/E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aconfUEjp1RcIO0IXNlwaJtPkDxK0kFDTODy2fF0wP75Ngwp+bJz7eBOmHhXo2nnZcEZZgCD2kki8hecwqA2sMUV36yEcizWv/XuH91SoeUT03OR9o0MG/b23W0qhuqLi86g2E4fHysYnoOnNOTkrh6fd0uuSMdYVBjhyt1Ojx8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=TALQ1WPf; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="TALQ1WPf" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-5bed83488b3so1413034a12.0 for ; Thu, 22 Aug 2024 08:28:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724340514; x=1724945314; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mGjGXMgxdEYAGo1GbGD2zE9hgBaB/Zwy6Dj9nf1BYt0=; b=TALQ1WPfsGlwnkAcUoHj25P9VKpYFU+aShb4VqPEViLtKjkDktCDKkujlRbazFzGh1 rJrB9FsJ0frIrXfCw5BxgDbCwI904Z+3cg0ISE/ZIsLYWFaJW8rzMu/SIAMXUcRp5ZT8 +pGkiBKnhlCbiIjiyl+rn4vtN4Jh8WCBaCpi+6CB5ubtAaXCf9/L8QqRn8TT9knwphwu a384FK2gmqWDdeSMb+7DRB8sTH9equo624fxXNZvIwpiA0aYZJ7n4dDbAmDkIbeex7QN 4pANwMKr7a2weQdFgZua7+0NdbXJxxYpHDjZW3UOZX2Io776w76AkeLRS03twigAEPpq CRNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724340514; x=1724945314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mGjGXMgxdEYAGo1GbGD2zE9hgBaB/Zwy6Dj9nf1BYt0=; b=BZA9dXhJw38wtSXlwXq29oijQrry6kku2mnk/vwo/kX95UMn9clHZrNnT4DXk+6wfK 0lU4M/O5Wu+OwjUGBr/cvoDGfcxaooYNzSBhdXOUYmhP+4B4dClEnNaPXVWyOgMSKfXR LvyzEZ9HAwK7LQoVuKavn9qymtgMzocNUXX/Of/3jq/c7bls3FJMoUpCAelmGy246J7l wtoxDGMsTk0Sj+Z8XdpaCc00eVCBiJSphQaUXEsOdh9eBOdFI+FX1Qof8edqP3EInmq5 jbeogIMZDtk6MYpxY2C1pDlPX6sUsqK+QDYCppJk47PCa3qVZadAVG3FVo9v06oXIHoq /cJw== X-Forwarded-Encrypted: i=1; AJvYcCWX+RkHYYfknpRdLKn1l26ExQd/iMWu8CK4gKyqdBHLm14vYl3hyZ2Cs7V/UojOiFt7254oTSbo1/U=@vger.kernel.org X-Gm-Message-State: AOJu0Yx2jtJCxRSachCBIyp8a7fvI8mQhGTSeJE/noQwtj8HhCOmdhTN TQNjZ9MY9O+KrC0KMWdhkO+Xkj0n+iF6MY8HADAfMAQsIRKkj7mjy5gNbSGB6m4= X-Google-Smtp-Source: AGHT+IGJeJoxOq1tlRUs+MCEa5uz16WViXX/h9LB3VGUBluXlsLHOcyR6hbTFMMPgE0Rs2wdaLi06w== X-Received: by 2002:a17:907:f74f:b0:a72:40b4:c845 with SMTP id a640c23a62f3a-a866f70378emr511233066b.51.1724340514344; Thu, 22 Aug 2024 08:28:34 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:33 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 09/16] dt-bindings: usb: renesas,usbhs: Document RZ/G3S SoC Date: Thu, 22 Aug 2024 18:27:54 +0300 Message-Id: <20240822152801.602318-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The USBHS IP block on RZ/G3S SoC is identitcal to the one found on the RZ/G2L device. Document the RZ/G3S USBHS IP block. Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index c63db3ebd07b..0f84cba872ce 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -26,6 +26,7 @@ properties: - renesas,usbhs-r9a07g043 # RZ/G2UL and RZ/Five - renesas,usbhs-r9a07g044 # RZ/G2{L,LC} - renesas,usbhs-r9a07g054 # RZ/V2L + - renesas,usbhs-r9a08g045 # RZ/G3S - const: renesas,rzg2l-usbhs - items: @@ -126,6 +127,7 @@ allOf: - renesas,usbhs-r9a07g043 - renesas,usbhs-r9a07g044 - renesas,usbhs-r9a07g054 + - renesas,usbhs-r9a08g045 then: properties: interrupts: From patchwork Thu Aug 22 15:27:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13773775 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FD4A1CE6EC for ; Thu, 22 Aug 2024 15:28:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340520; cv=none; b=aW3JOk5sPKS9YoBAE6F/2uq7E3XpQj5f/gsQhwoD/W+a755pcZdUI7/OgcQywy4Wy8HPoSWP2cKCtwzCN8V2K3RIjaLXRCEDFzbdfbYpapUWDFiZioNo4+mD8r2P0uRQMgIICGhN4KlkPREEboE8dUSgFg++3yzuaEY9LbS89fs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340520; c=relaxed/simple; bh=e+aMAhnDBLszFLP58P9acFsRkrTnbYGFwK58/oU4n6s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=srF8I5J1zt3lmt5JaDGeJPkxBjqRXn+PH7Gmq7Ov/19MbwWC6ITB28fpGwxJx8wm+5c1ka9U66CAjO3kxwDJtsu8PEcY2Wrt5I14TRncn1rPgGsq+K0xj6jhFPD0GLvHpDf7kvs7Wg1OYqfm7gbqYxd5BjidJ84Gy9HlTpluwYw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=qFQAMKlS; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="qFQAMKlS" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-a8696e9bd24so68847766b.0 for ; Thu, 22 Aug 2024 08:28:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724340517; x=1724945317; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MLN4pb77vJ4aC8LA9dpwq6n4qe80J5V8TVd+pDGU9bo=; b=qFQAMKlS4w8/sVJw3h0CVKxSpLK6adEqPHq/LDzpCxqbhzZ6GwL7KaQi0r3qTDDgpN cNmf1ca2t6ZMYIPEAizmy+8EKYdbmcxc3uJkEOgv6aMCfBaqigv6u8U3rAWM2EsKQxeu uX8NruKefCdKou94U1STpRfiFlkL04jNUfa8f5Br80wjsNzfY8LvkzIbrHwO6mJlJn+6 Vu5VPtWMZpsFmNkYCMTLeJLeTCXeYhOA1XjvFKG0d0kK9adKv02J7khO3mB6VlVVtA9b q2gOTJ0g2ftLC8DAlmFIVuSJMDXm+EZCoNALrsjzGcU0NYiFKT1EF7cKwiW3AH2t+/eR LuhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724340517; x=1724945317; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MLN4pb77vJ4aC8LA9dpwq6n4qe80J5V8TVd+pDGU9bo=; b=DP1bowwdR7GBIozm7QEzz5JEOQdorGYNfylzo4IPNL5lXMLbXga/fMq98nO+pn8MPE fsAtprGuwf28m8LzG/BNgZ0cbzTH0is7k2sz6gR4eZlQ/Y84sTBACJD1Kfby9U5dTrli 5Sthp6E2MtLXSZxrrsAWgdlEja4cWTvNYnJp7AVWBrMZrOZwplQhQwtVmxeaQ1D7qOAV kQrmD1FltwDDWDx8cYb7J4wpkP3eM/HY6KdlEvgbd0bm3ziwXe3nOuIGC24BOcgB/Hhi 1EcBRFvNSUf3KEES82FEt8KJuvBTcTlP5t3X6YGx74jwQ69wm+kTCInqRf+2CQ7PHAId NRww== X-Forwarded-Encrypted: i=1; AJvYcCUGrt58X1uDHTXHWaQcwia2hkcV2L4eL0Zsg0/T/LmK1jzfhrJ4BcY3br5w0yXOA2TWX6DuI3gV+rg=@vger.kernel.org X-Gm-Message-State: AOJu0YwVYr2MJnEHdsaDl16SdIb593whgXHY/Pz2OB/HrOZOdbohI2Hb 6RM6TvFmDNtvF5U7eAHFFqvFIWO34GWcmMzZenq9TPcvNA4TDtvUKE8V0/fmg3M= X-Google-Smtp-Source: AGHT+IEYrxA2bm8mmwSX01X2yZ3QhHyjhFNmbYyUH1245MQKOvJG+Mgyld3wrG6KhxZVhMAa/kKlOQ== X-Received: by 2002:a17:907:2cc6:b0:a80:7c30:a836 with SMTP id a640c23a62f3a-a866f894098mr510823566b.56.1724340516716; Thu, 22 Aug 2024 08:28:36 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:35 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 10/16] phy: renesas: rcar-gen3-usb2: Add support to initialize the bus Date: Thu, 22 Aug 2024 18:27:55 +0300 Message-Id: <20240822152801.602318-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S need to initialize the USB BUS before transferring data due to hardware limitation. As the register that need to be touched for this is in the address space of the USB PHY, and the UBS PHY need to be initialized before any other USB drivers handling data transfer, add support to initialize the USB BUS. As the USB PHY is probed before any other USB drivers that enables clocks and de-assert the reset signals and the BUS initialization is done in the probe phase, we need to add code to de-assert reset signal and runtime resume the device (which enables its clocks) before accessing the registers. As the reset signals are not required by the USB PHY driver for the other USB PHY hardware variants, the reset signals and runtime PM was handled only in the function that initialize the USB BUS. The PHY initialization was done right after runtime PM enable to have all in place when the PHYs are registered. Signed-off-by: Claudiu Beznea --- drivers/phy/renesas/phy-rcar-gen3-usb2.c | 50 ++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c index 7594f64eb737..cf4299cea579 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -19,12 +19,14 @@ #include #include #include +#include #include #include #include /******* USB2.0 Host registers (original offset is +0x200) *******/ #define USB2_INT_ENABLE 0x000 +#define USB2_AHB_BUS_CTR 0x008 #define USB2_USBCTR 0x00c #define USB2_SPD_RSM_TIMSET 0x10c #define USB2_OC_TIMSET 0x110 @@ -40,6 +42,10 @@ #define USB2_INT_ENABLE_USBH_INTB_EN BIT(2) /* For EHCI */ #define USB2_INT_ENABLE_USBH_INTA_EN BIT(1) /* For OHCI */ +/* AHB_BUS_CTR */ +#define USB2_AHB_BUS_CTR_MBL_MASK GENMASK(1, 0) +#define USB2_AHB_BUS_CTR_MBL_INCR4 2 + /* USBCTR */ #define USB2_USBCTR_DIRPD BIT(2) #define USB2_USBCTR_PLL_RST BIT(1) @@ -111,6 +117,7 @@ struct rcar_gen3_chan { struct extcon_dev *extcon; struct rcar_gen3_phy rphys[NUM_OF_PHYS]; struct regulator *vbus; + struct reset_control *rstc; struct work_struct work; struct mutex lock; /* protects rphys[...].powered */ enum usb_dr_mode dr_mode; @@ -125,6 +132,7 @@ struct rcar_gen3_chan { struct rcar_gen3_phy_drv_data { const struct phy_ops *phy_usb2_ops; bool no_adp_ctrl; + bool init_bus; }; /* @@ -650,6 +658,35 @@ static enum usb_dr_mode rcar_gen3_get_dr_mode(struct device_node *np) return candidate; } +static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) +{ + struct device *dev = channel->dev; + int ret; + u32 val; + + channel->rstc = devm_reset_control_array_get_shared(dev); + if (IS_ERR(channel->rstc)) + return PTR_ERR(channel->rstc); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(channel->rstc); + if (ret) + goto rpm_put; + + val = readl(channel->base + USB2_AHB_BUS_CTR); + val &= ~USB2_AHB_BUS_CTR_MBL_MASK; + val |= USB2_AHB_BUS_CTR_MBL_INCR4; + writel(val, channel->base + USB2_AHB_BUS_CTR); + +rpm_put: + pm_runtime_put(dev); + + return ret; +} + static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) { const struct rcar_gen3_phy_drv_data *phy_data; @@ -703,6 +740,15 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) goto error; } + platform_set_drvdata(pdev, channel); + channel->dev = dev; + + if (phy_data->init_bus) { + ret = rcar_gen3_phy_usb2_init_bus(channel); + if (ret) + goto error; + } + channel->soc_no_adp_ctrl = phy_data->no_adp_ctrl; if (phy_data->no_adp_ctrl) channel->obint_enable_bits = USB2_OBINT_IDCHG_EN; @@ -733,9 +779,6 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) channel->vbus = NULL; } - platform_set_drvdata(pdev, channel); - channel->dev = dev; - provider = devm_of_phy_provider_register(dev, rcar_gen3_phy_usb2_xlate); if (IS_ERR(provider)) { dev_err(dev, "Failed to register PHY provider\n"); @@ -762,6 +805,7 @@ static void rcar_gen3_phy_usb2_remove(struct platform_device *pdev) if (channel->is_otg_channel) device_remove_file(&pdev->dev, &dev_attr_role); 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:38 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 11/16] dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings Date: Thu, 22 Aug 2024 18:27:56 +0300 Message-Id: <20240822152801.602318-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Document the RZ/G3S PHY bindings. The RZ/G3S USB PHY is almost identical with the RZ/G2L USB PHY. The difference is that there is a hardware limitation on the max burst size used when the BUS master interface issues a transfer request for RZ/G3S that is configured though PHY registers. Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index f82649a55e91..af275cea3456 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -13,7 +13,9 @@ properties: compatible: oneOf: - items: - - const: renesas,usb2-phy-r8a77470 # RZ/G1C + - enum: + - renesas,usb2-phy-r8a77470 # RZ/G1C + - renesas,usb2-phy-r9a08g045 # RZ/G3S - items: - enum: From patchwork Thu Aug 22 15:27:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13773777 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF5D31D0489 for ; Thu, 22 Aug 2024 15:28:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340524; cv=none; b=AQI/AabJ+7siljzFxRwSgYwnJdfiE1rXjD2f/Rka3KBSs1HxfPbNekZ1rBUxHIZikFc2B8nd6VZ+1OL81ibU+37YVpsdBtOCkzkgPFb1xNBvlp464BaM1+zxe/CEmPZa6mB8tEkdk/FdO2QRbLh9kEt8F7kM7MiTgFqFzIaSdv8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340524; c=relaxed/simple; bh=qfMyBWF/BL7cu1fLu2yMExkkMJ+Iv5WKiP7iKrRAAGk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OsJ7BTFqeRaX2EkJBbaF/VDWzr5Yu6+PY2ZvOhkq+iVdFBkq1PZYrTsrFBV7UoM9QUctcWV4SZm699lRn48ux5zOYCFtxmT4N14MmHcK92sPPqi9iHlKlQ/m7NUxlEVLImGJ3rPAZPOAlxq6B1ooRBvUmxJER96+bnSzhL6sHfg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=lSC0pPIt; arc=none smtp.client-ip=209.85.218.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="lSC0pPIt" Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-a8684c31c60so121164166b.3 for ; Thu, 22 Aug 2024 08:28:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724340521; x=1724945321; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XSWof3eimbYWdm3Zde2Iz4BDEJwC1Ylc5fdAQ7iNZKY=; b=lSC0pPItQ1mmbd/o/QKaAbzFexzBwZt/gpoSig4MEDA4mHOPelhwzMiF/rZuoZInu/ VBmHIcOAZuBPYPociUCPZ6/i7ddtKNX9wDIlf60CRd0/o2UD5NIFX8FeBseGM/bFzcq2 JZhSDAJNyfZP6dq9l39kgZg+aF08Vps8GNna4ZLCpuX21L3Nkzuq5/EGNLoKMjFs0kPp JdXpg5t4kTjozpqV3botNWvrNDrSihivB48ih82yxvFYvD00NQ/DCIxaifF5s61+OFVB VRKjzGxHaUxqJS5eazktQEb/1jl4E9KpvgEahhoq/0eUjAAFhLgyr4LzKkVWByARNMq7 /NSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724340521; x=1724945321; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XSWof3eimbYWdm3Zde2Iz4BDEJwC1Ylc5fdAQ7iNZKY=; b=KNKL3cc+O1UTZWD4SncmSRCAHpepS1akRabCSgirER8vaz92x+95+POv9/dibx38jO ev6ovgw7VNLp4T+LtYTFGVuMCcyJ1PtnnSmzOhXcWlOQLmSyO/3ueWscowGrYjistCvu CEjCLhKstZAqNHttAt1pxMGRV53r5OU8ri5iU7lkXCdjdnsP9yoNeoZuOEPuDF5lhw8U /4vcp4UpoH0IOYLKiiZPs79DV6d0OXz57kn+VHGAHZN0jg+l00evqFPJHiw2ID0n3hr4 wp3VpT0zzyOnM368I4hb/F0GjgF/Z8xhYjLSqYvvI3OscxYtjNyOUfwp8BlSQPOT59uv +alQ== X-Forwarded-Encrypted: i=1; AJvYcCWd4M35P+nXd4U+Z9sOUyalGLFkqTlOzpBy2rqYD5acKvel4qdJ1+2ZFJjKmjjLJXCks9UBt59aUEQ=@vger.kernel.org X-Gm-Message-State: AOJu0YyK7yShD/+XwOpexva92kjI+AtOEM5TucwnYNt7a9ki1ATvGFv4 VKz3wDpEWUFz/JGW/Hax67qlvip91tVYixzNIoWs6j9Ge0IFfSnZve0eA9Edoas= X-Google-Smtp-Source: AGHT+IEBQZ1FZ/LXCGsRTtDo2mrL6RRIsqfYVgMxLk7cvYuAGygDFmxNvFc2QDySBzsJWYCvzMOvmg== X-Received: by 2002:a17:907:7214:b0:a86:82e2:8c64 with SMTP id a640c23a62f3a-a8691b5c943mr185347366b.35.1724340521191; Thu, 22 Aug 2024 08:28:41 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:40 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 12/16] phy: renesas: rcar-gen3-usb2: Add support for the RZ/G3S SoC Date: Thu, 22 Aug 2024 18:27:57 +0300 Message-Id: <20240822152801.602318-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add support for the Renesas RZ/G3S SoC. The support is similar with the rest of RZ/G2 devices with the except that the RZ/G3S needs bus initialization due to hardware limitation. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/phy/renesas/phy-rcar-gen3-usb2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c index cf4299cea579..58e123305152 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -583,6 +583,12 @@ static const struct rcar_gen3_phy_drv_data rz_g2l_phy_usb2_data = { .no_adp_ctrl = true, }; +static const struct rcar_gen3_phy_drv_data rz_g3s_phy_usb2_data = { + .phy_usb2_ops = &rcar_gen3_phy_usb2_ops, + .no_adp_ctrl = true, + .init_bus = true, +}; + static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = { { .compatible = "renesas,usb2-phy-r8a77470", @@ -604,6 +610,10 @@ static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = { .compatible = "renesas,rzg2l-usb2-phy", .data = &rz_g2l_phy_usb2_data, }, + { + .compatible = "renesas,usb2-phy-r9a08g045", + .data = &rz_g3s_phy_usb2_data, + }, { .compatible = "renesas,rcar-gen3-usb2-phy", .data = &rcar_gen3_phy_usb2_data, From patchwork Thu Aug 22 15:27:58 2024 Content-Type: text/plain; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:42 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 13/16] arm64: dts: renesas: Add #reset-cells to system controller node Date: Thu, 22 Aug 2024 18:27:58 +0300 Message-Id: <20240822152801.602318-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea System controller on RZ/G3S can act as a reset controller. Add #reset-cells for it. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 0d5c47a65e46..cd7cefdb2bab 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -91,6 +91,7 @@ sysc: system-controller@11020000 { ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #reset-cells = <1>; status = "disabled"; }; From patchwork Thu Aug 22 15:27:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13773779 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5D831D0DE2 for ; Thu, 22 Aug 2024 15:28:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340528; cv=none; b=AVUuiX13Vye/k3Hp7m/6mqeTD6T7YERJYydjfYRMz5g37V3T/N2ihBXJ6dCD55UWcsVB5nECWvvX/8LKRdwl8Hkg/vF2ANrfcShxIPD98Mwz/selXKssyaW5ipMXV4/eU0+DCUXNrYKURwXYWWYRsex5GdPXXhMXoQzjxVlidaY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340528; c=relaxed/simple; bh=td5zEc+tb8JtMGLYePPo5uWb9J4ZFXnR8frS8gAesuU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GEM7mqxn3TJIKh2bYN2eVMRgpk2h16RR+l7c4nwKsNXib2/GtmFrUyLN9AMntqPMbI1XetKH0hI/pqWGtsrfa0yYHFp5amxDm86ZXBMQKvz3oO/wkp9ZnwCpRSztLYbB9My5K3JbSPLYqD4uijuRG6nVW4zE6jyFoZ0v0OxQs14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=VxnJeb7j; arc=none smtp.client-ip=209.85.218.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="VxnJeb7j" Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-a7a81bd549eso91775466b.3 for ; Thu, 22 Aug 2024 08:28:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724340525; x=1724945325; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xQy3IcKZPJI2hl6KCRWvj32xtpsEdmpbu7wAI3ouog0=; b=VxnJeb7js86RnVQ8QlPUxTVV0XKjmy7g9ELbeWaAawq0Heae7byvt7KqGciyTLV4NB Xd0JVIgo97bQhyc//tn+fmPSWm1qOW07PkIsg2f+WLaHwM+bMaj88HL1BcUwkFk49d0H BRWbl29D/s1g0KeVSnevjg3hWalRe6//4cA21oBLBUia4LJIK0kPzJf5lFYPLDoQx1/6 3/f0zxwFMJwTiMhOxwit9XRfN2sI7EeuarxoZks6QYKCe1GUPL3zo9uV4+zJnPBFEj7m RqCgg2MYKiYnEO6wKyQ7hKzLjtjJyDBhPu8/C99KjVJtaIYa5N6z5zMJldeY6jevXhWN qQUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724340525; x=1724945325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xQy3IcKZPJI2hl6KCRWvj32xtpsEdmpbu7wAI3ouog0=; b=IKTNmqMlFC3lgup+r8PaPAx0SfHMJiWyluEvRbLAEKe1VdGHigIVaE059s6YoslftW wPLJTC7KapiVByfOIrn7fWzn5tweTVMDCrBBs9iOz+oyP05h5kQOCnmG6+qlyvcqo3bC cpvII9nB8V2spFhnZ4G4NKe0HLjfhryVxEOu+r95quHXL5t+4e9606YMsriSXm191YO6 cmrRJBDOhC10u+tkgKgFxaFk0tg3OLD0gaLPIqwZpHH26FYFuspXK7lzDJSBUR3im8pg a0QoteFhgJNlxBfoRHfQfyxulfl0uMeimizyI7Obiq8AqhVQg8dXMRVVnPwZlOIgDgOR foXQ== X-Forwarded-Encrypted: i=1; AJvYcCXV6tobzD7k5Hnx0TaytwIM97CQU52d+xqYKDPyLvIkSjvKBgm9HpGATQiGbI3Bxt0QdIG1xsBrHDg=@vger.kernel.org X-Gm-Message-State: AOJu0YwtzDkppEMK9rTwXUu8s1xeYv60XEOi1XvNt1X/8Od5C4SeKs04 czIu2y2gIWqSfatk06Y1xrgDFQUoiekoogXOZWeLuxFqM9neyph8dnkX9gyamfY= X-Google-Smtp-Source: AGHT+IFxTIoKrOlLy0DfsD4U5A56PkQ2ZXDt8aAyKB79f3D2YVsPAO1B8nxgDwEOV3dbQje4XIXtCg== X-Received: by 2002:a17:907:808:b0:a77:e48d:bc8 with SMTP id a640c23a62f3a-a866f27a0d1mr551018366b.21.1724340525195; Thu, 22 Aug 2024 08:28:45 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:44 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 14/16] arm64: dts: renesas: r9a08g045: Add USB support Date: Thu, 22 Aug 2024 18:27:59 +0300 Message-Id: <20240822152801.602318-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset, host and device support. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 119 +++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index cd7cefdb2bab..c6c279dffccf 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { compatible = "renesas,r9a08g045"; @@ -265,6 +266,124 @@ eth1: ethernet@11c40000 { status = "disabled"; }; + phyrst: usbphy-ctrl@11e00000 { + compatible = "renesas,r9a08g045-usbphy-ctrl"; + reg = <0 0x11e00000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>; + resets = <&cpg R9A08G045_USB_PRESETN>, + <&sysc R9A08G045_SYSC_RESET_USB>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name = "vbus"; + }; + }; + + ohci0: usb@11e10000 { + compatible = "generic-ohci"; + reg = <0 0x11e10000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci0: usb@11e10100 { + compatible = "generic-ehci"; + reg = <0 0x11e10100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@11e10200 { + compatible = "renesas,usb2-phy-r9a08g045"; + reg = <0 0x11e10200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + hsusb: usb@11e20000 { + compatible = "renesas,usbhs-r9a08g045", + "renesas,rzg2l-usbhs"; + reg = <0 0x11e20000 0 0x10000>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci1: usb@11e30000 { + compatible = "generic-ohci"; + reg = <0 0x11e30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci1: usb@11e30100 { + compatible = "generic-ehci"; + reg = <0 0x11e30100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@11e30200 { + compatible = "renesas,usb2-phy-r9a08g045"; + reg = <0 0x11e30200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Thu Aug 22 15:28:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13773780 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3447E1D1734 for ; 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Thu, 22 Aug 2024 08:28:47 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:46 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 15/16] arm64: dts: renesas: rzg3s-smarc: Enable USB support Date: Thu, 22 Aug 2024 18:28:00 +0300 Message-Id: <20240822152801.602318-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable USB support (host, device, USB PHYs and sysc). Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 61 ++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index deb2ad37bb2e..fd9355936803 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -66,6 +66,29 @@ vccq_sdhi1: regulator-vccq-sdhi1 { }; }; +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + &pinctrl { key-1-gpio-hog { gpio-hog; @@ -124,6 +147,27 @@ cd { pinmux = ; /* SD1_CD */ }; }; + + usb0_pins: usb0 { + peri { + pinmux = , /* VBUS */ + ; /* OVC */ + }; + + otg { + pinmux = ; /* OTG_ID */ + bias-pull-up; + }; + }; + + usb1_pins: usb1 { + pinmux = , /* OVC */ + ; /* VBUS */ + }; +}; + +&phyrst { + status = "okay"; }; &scif0 { @@ -144,3 +188,20 @@ &sdhi1 { max-frequency = <125000000>; status = "okay"; }; + +&sysc { + status = "okay"; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + vbus-supply = <&usb0_vbus_otg>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; From patchwork Thu Aug 22 15:28:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13773781 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 888D01D1F44 for ; Thu, 22 Aug 2024 15:28:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724340533; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:49 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 16/16] arm64: defconfig: Enable RZ/G3S SYSC reset driver Date: Thu, 22 Aug 2024 18:28:01 +0300 Message-Id: <20240822152801.602318-17-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> References: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable RZ/G3S SYSC reset driver. This exports the control to 2 signals (one for USB, one for PCI). Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7d32fca64996..4720367a41ea 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1510,6 +1510,7 @@ CONFIG_RESET_IMX7=y CONFIG_RESET_QCOM_AOSS=y CONFIG_RESET_QCOM_PDC=m CONFIG_RESET_RZG2L_USBPHY_CTRL=y +CONFIG_RESET_RZG3S_SYSC=y CONFIG_RESET_TI_SCI=y CONFIG_PHY_XGENE=y CONFIG_PHY_CAN_TRANSCEIVER=m