From patchwork Thu Aug 22 17:28:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63B10C3DA4A for ; Thu, 22 Aug 2024 17:28:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C94F510EB84; Thu, 22 Aug 2024 17:28:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G5D0xXKe"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id A23DB10EB87; Thu, 22 Aug 2024 17:28:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724347732; x=1755883732; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xBTBmpL924eHLaGaJlxfMEUf+QEa13q0knxeUnC7CKw=; b=G5D0xXKe3ojXJOKfC/BTRdraljmWXf9NKC5JxfiKS94EbmfDEJRztpGR ABevk1pUWIMzHUIhjkFR+2x923fWx+zT8zIfklHJc7I2d9siViHp0W+ZV yhCQR7oOfgE9uIvh9COkWhQqYdymhrio3j922Z9DHlzYh919EkxYN2AnL 29GNQoPz5hvOX2+Nmnd15T1X9A8w2JhStGCATwryeHCmVuVa2CBzSqYO1 5duQtWZn5BzNY5XlV/7mPv/bfCPuRMN49yE9iPSUTS5CSmZXcutCTibAv l1YjYqMu4RZ24vZCI/hTJ1tzrg1Q6RI77x7l+mXWSxqQ+qPVTD7X+mJlA A==; X-CSE-ConnectionGUID: Ifsp+r9TQzaJCxWUvLkLew== X-CSE-MsgGUID: asBqNQUFQWexTPDo0b7vpQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="33448234" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="33448234" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:28:51 -0700 X-CSE-ConnectionGUID: GitN2khwRdOI6eZuL2dABw== X-CSE-MsgGUID: rgbEW/lESve1aucOheldPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="61501024" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:28:50 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 01/15] drm/i915/gt: Avoid using masked workaround for CCS_MODE setting Date: Thu, 22 Aug 2024 19:28:18 +0200 Message-ID: <20240822172832.494994-2-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" When setting the CCS mode, we mistakenly used wa_masked_en() to apply the workaround, which reads from the register and masks the existing value with the new one. Our intention was to write the value directly, without masking it. So far, this hasn't caused issues because we've been using a register value that only enables a single CCS engine, typically with an ID of '0'. However, in upcoming patches, we will be utilizing multiple engines, and it's crucial that we write the new value directly without any masking. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index bfe6d8fc820f..f3082fad3f45 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2745,7 +2745,7 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li * assign all slices to a single CCS. We will call it CCS mode 1 */ mode = intel_gt_apply_ccs_mode(gt); - wa_masked_en(wal, XEHP_CCS_MODE, mode); + wa_add(wal, XEHP_CCS_MODE, 0, mode, mode, false); } /* From patchwork Thu Aug 22 17:28:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F422C3DA4A for ; Thu, 22 Aug 2024 17:28:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 803CF10EB8A; Thu, 22 Aug 2024 17:28:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="REOIqc1H"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5030210EB88; Thu, 22 Aug 2024 17:28:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724347737; x=1755883737; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FQO02+IaMgU5e/1DOI4Cdpxg4Wv0yNleSCLQLCvWwsE=; b=REOIqc1H4KEPT5IJ0xj0iknExhZ2efDAvFr1cvJibRORSrgqRD9cvUCY w19OK+j7vpKfIxBYkUlDwF8/8I+G4+1m6+FfdY37Umvnskl8Bg2LMpaKM 6FFCMR4osZUngjVq9IKoa59KrETAzJ0KRC26HIMrU/5bzb20djBy5kI5H mvZbAlvhjHPtQ1ybNNMQqmPgSITATnZ/qiEbZV2jmZc7N2XUB2xRU0fv/ FU1Z0MroQE025mtEkot/cbrRicDshpaOesU26oEa8LzAxSJ+K98eu7iRP OZzRGqYOzan9L9Wy15XRbwbbKlv5CZoCT/9YT2dNHxQwZrY4ic248p5pM w==; X-CSE-ConnectionGUID: hLk7ZoTCTviioqs2AoftXg== X-CSE-MsgGUID: kgLzzhlES+G+KLpCets5Vw== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="33448237" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="33448237" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:28:57 -0700 X-CSE-ConnectionGUID: OVHhYfaLQLe4M7/OExPq0w== X-CSE-MsgGUID: 1PNZ9LJZSWKCXBA/FtPRCw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="61501062" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:28:55 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 02/15] drm/i915/gt: Move the CCS mode variable to a global position Date: Thu, 22 Aug 2024 19:28:19 +0200 Message-ID: <20240822172832.494994-3-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Store the CCS mode value in the intel_gt->ccs structure to make it available for future instances that may need to change its value. Name it mode_reg_val because it holds the value that will be written into the CCS_MODE register, determining the CCS balancing and, consequently, the number of engines generated. No functional changes intended. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++ drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 16 +++++++++++----- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++-- 5 files changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index a6c69a706fd7..5af0527d822d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -18,6 +18,7 @@ #include "intel_ggtt_gmch.h" #include "intel_gt.h" #include "intel_gt_buffer_pool.h" +#include "intel_gt_ccs_mode.h" #include "intel_gt_clock_utils.h" #include "intel_gt_debugfs.h" #include "intel_gt_mcr.h" @@ -136,6 +137,8 @@ int intel_gt_init_mmio(struct intel_gt *gt) intel_sseu_info_init(gt); intel_gt_mcr_init(gt); + intel_gt_ccs_mode_init(gt); + return intel_engines_init_mmio(gt); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 3c62a44e9106..fcd07eb4728b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -8,15 +8,12 @@ #include "intel_gt_ccs_mode.h" #include "intel_gt_regs.h" -unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) +static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { int cslice; u32 mode = 0; int first_ccs = __ffs(CCS_MASK(gt)); - if (!IS_DG2(gt->i915)) - return 0; - /* Build the value for the fixed CCS load balancing */ for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { if (gt->ccs.cslices & BIT(cslice)) @@ -35,5 +32,14 @@ unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) XEHP_CCS_MODE_CSLICE_MASK); } - return mode; + gt->ccs.mode_reg_val = mode; +} + +void intel_gt_ccs_mode_init(struct intel_gt *gt) +{ + if (!IS_DG2(gt->i915)) + return; + + /* Initialize the CCS mode setting */ + intel_gt_apply_ccs_mode(gt); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 55547f2ff426..0f2506586a41 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -8,6 +8,6 @@ struct intel_gt; -unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); +void intel_gt_ccs_mode_init(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index bcee084b1f27..9e257f34d05b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -207,12 +207,23 @@ struct intel_gt { [MAX_ENGINE_INSTANCE + 1]; enum intel_submission_method submission_method; + /* + * Track fixed mapping between CCS engines and compute slices. + * + * In order to w/a HW that has the inability to dynamically load + * balance between CCS engines and EU in the compute slices, we have to + * reconfigure a static mapping on the fly. + * + * The mode variable is set by the user and sets the balancing mode, + * i.e. how the CCS streams are distributed amongs the slices. + */ struct { /* * Mask of the non fused CCS slices * to be used for the load balancing */ intel_engine_mask_t cslices; + u32 mode_reg_val; } ccs; /* diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index f3082fad3f45..f6135be3cd86 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2727,7 +2727,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt, static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct intel_gt *gt = engine->gt; - u32 mode; + u32 mode = gt->ccs.mode_reg_val; if (!IS_DG2(gt->i915)) return; @@ -2743,8 +2743,10 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li /* * After having disabled automatic load balancing we need to * assign all slices to a single CCS. We will call it CCS mode 1 + * + * The gt->ccs.mode_reg_val has already been set previously during + * initialization. */ - mode = intel_gt_apply_ccs_mode(gt); wa_add(wal, XEHP_CCS_MODE, 0, mode, mode, false); } From patchwork Thu Aug 22 17:28:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1DCF5C52D7C for ; Thu, 22 Aug 2024 17:29:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 97A0A10EB8B; Thu, 22 Aug 2024 17:29:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G6j3ORV0"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id C7E1110EB89; Thu, 22 Aug 2024 17:29:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724347744; x=1755883744; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SLL7iGK002dHV93S+9oR22+Ok3ozAZn/+5plhjwrlfU=; b=G6j3ORV0tTJOPy9osZathXjMtgDDw3uiW478zFbIefaN9W46x9yLDl19 ztwOP77JQxHShmMJUlNjzOeKh0Xxew8mBMO6H5Q4vdYclQ9USZwMmK3XQ 3cz21STAmIubWd25JOlk5th3MT0vg7XlXwqms5JsyL9SlV5xgZTY3WdUU etdlovbB14nAnwwGI3uHPsFEQXuDg9AAEWyl8S/wawW43/nSCGNjSuH0I 03GFAeVlrZsUeSWXq0epc7UU0//PKyqz2u7Y/ApK6Q+be9ylfaYFu8e+7 6X3knZpXtdD9+pT2kWu6SWskJeGKllv5Bx5qqkJzBCYyzajUKZlmdmD13 g==; X-CSE-ConnectionGUID: Ow0vDFmsTpqAVadBADs3bg== X-CSE-MsgGUID: 967acJEmR5uZr9BIV36U2Q== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="33448251" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="33448251" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:04 -0700 X-CSE-ConnectionGUID: DSxAGXvSRtS750emK+3HPw== X-CSE-MsgGUID: jQWS4mxJTEmahTRV7y3O0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="61501083" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:01 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 03/15] drm/i915/gt: Allow the creation of multi-mode CCS masks Date: Thu, 22 Aug 2024 19:28:20 +0200 Message-ID: <20240822172832.494994-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Until now, we have only set CCS mode balancing to 1, which means that only one compute engine is exposed to the user. The stream of compute commands submitted to that engine is then shared among all the dedicated execution units. This is done by calling the 'intel_gt_apply_ccs_mode(); function. With this change, the aforementioned function takes an additional parameter called 'mode' that specifies the desired mode to be set for the CCS engines balancing. The mode parameter can have the following values: - mode = 0: CCS load balancing mode 1 (1 CCS engine exposed) - mode = 1: CCS load balancing mode 2 (2 CCS engines exposed) - mode = 3: CCS load balancing mode 4 (4 CCS engines exposed) This allows us to generate the appropriate register value to be written to CCS_MODE, configuring how the exposed engine streams will be submitted to the execution units. No functional changes are intended yet, as no mode higher than '0' is currently being set. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 85 +++++++++++++++++---- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- 2 files changed, 72 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index fcd07eb4728b..a6c33b471567 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -4,35 +4,92 @@ */ #include "i915_drv.h" -#include "intel_gt.h" #include "intel_gt_ccs_mode.h" #include "intel_gt_regs.h" static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { + unsigned long cslices_mask = gt->ccs.cslices; + u32 mode_val = 0; + /* CCS engine id, i.e. the engines position in the engine's bitmask */ + int engine; int cslice; - u32 mode = 0; - int first_ccs = __ffs(CCS_MASK(gt)); - /* Build the value for the fixed CCS load balancing */ + /* + * The mode has two bit dedicated for each engine + * that will be used for the CCS balancing algorithm: + * + * BIT | CCS slice + * ------------------ + * 0 | CCS slice + * 1 | 0 + * ------------------ + * 2 | CCS slice + * 3 | 1 + * ------------------ + * 4 | CCS slice + * 5 | 2 + * ------------------ + * 6 | CCS slice + * 7 | 3 + * ------------------ + * + * When a CCS slice is not available, then we will write 0x7, + * oterwise we will write the user engine id which load will + * be forwarded to that slice. + * + * The possible configurations are: + * + * 1 engine (ccs0): + * slice 0, 1, 2, 3: ccs0 + * + * 2 engines (ccs0, ccs1): + * slice 0, 2: ccs0 + * slice 1, 3: ccs1 + * + * 4 engines (ccs0, ccs1, ccs2, ccs3): + * slice 0: ccs0 + * slice 1: ccs1 + * slice 2: ccs2 + * slice 3: ccs3 + */ + engine = __ffs(cslices_mask); + for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { - if (gt->ccs.cslices & BIT(cslice)) + if (!(cslices_mask & BIT(cslice))) { /* - * If available, assign the cslice - * to the first available engine... + * If not available, mark the slice as unavailable + * and no task will be dispatched here. */ - mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs); + mode_val |= XEHP_CCS_MODE_CSLICE(cslice, + XEHP_CCS_MODE_CSLICE_MASK); + continue; + } - else + mode_val |= XEHP_CCS_MODE_CSLICE(cslice, engine); + + engine = find_next_bit(&cslices_mask, I915_MAX_CCS, engine + 1); + /* + * If "engine" has reached the I915_MAX_CCS value it means that + * we have gone through all the unfused engines and now we need + * to reset its value to the first engine. + * + * From the find_next_bit() description: + * + * "Returns the bit number for the next set bit + * If no bits are set, returns @size." + */ + if (engine == I915_MAX_CCS) { /* - * ... otherwise, mark the cslice as - * unavailable if no CCS dispatches here + * CCS mode, will be used later to + * reset to a flexible value */ - mode |= XEHP_CCS_MODE_CSLICE(cslice, - XEHP_CCS_MODE_CSLICE_MASK); + engine = __ffs(cslices_mask); + continue; + } } - gt->ccs.mode_reg_val = mode; + gt->ccs.mode_reg_val = mode_val; } void intel_gt_ccs_mode_init(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 0f2506586a41..4a6763b95a78 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -6,7 +6,7 @@ #ifndef __INTEL_GT_CCS_MODE_H__ #define __INTEL_GT_CCS_MODE_H__ -struct intel_gt; +#include "intel_gt.h" void intel_gt_ccs_mode_init(struct intel_gt *gt); From patchwork Thu Aug 22 17:28:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8A03C3DA4A for ; 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X-CSE-ConnectionGUID: AK/bY7nfTNycQWHsjuvTqA== X-CSE-MsgGUID: X2y0e7bCQkSJ3pqI0HsQCQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="33448265" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="33448265" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:08 -0700 X-CSE-ConnectionGUID: cOfiNl/FTMuyHc++vBmxnQ== X-CSE-MsgGUID: SWP6Y0k6TCyFVnWCHQc+bg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="61501114" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:07 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 04/15] drm/i915/gt: Refactor uabi engine class/instance list creation Date: Thu, 22 Aug 2024 19:28:21 +0200 Message-ID: <20240822172832.494994-5-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For the upcoming changes we need a cleaner way to build the list of uabi engines. Suggested-by: Tvrtko Ursulin Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 ++++++++++++--------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 833987015b8b..11cc06c0c785 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -203,7 +203,7 @@ static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 void intel_engines_driver_register(struct drm_i915_private *i915) { - u16 name_instance, other_instance = 0; + u16 class_instance[I915_LAST_UABI_ENGINE_CLASS + 2] = { }; struct legacy_ring ring = {}; struct list_head *it, *next; struct rb_node **p, *prev; @@ -214,6 +214,8 @@ void intel_engines_driver_register(struct drm_i915_private *i915) prev = NULL; p = &i915->uabi_engines.rb_node; list_for_each_safe(it, next, &engines) { + u16 uabi_class; + struct intel_engine_cs *engine = container_of(it, typeof(*engine), uabi_list); @@ -222,15 +224,14 @@ void intel_engines_driver_register(struct drm_i915_private *i915) GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes)); engine->uabi_class = uabi_classes[engine->class]; - if (engine->uabi_class == I915_NO_UABI_CLASS) { - name_instance = other_instance++; - } else { - GEM_BUG_ON(engine->uabi_class >= - ARRAY_SIZE(i915->engine_uabi_class_count)); - name_instance = - i915->engine_uabi_class_count[engine->uabi_class]++; - } - engine->uabi_instance = name_instance; + + if (engine->uabi_class == I915_NO_UABI_CLASS) + uabi_class = I915_LAST_UABI_ENGINE_CLASS + 1; + else + uabi_class = engine->uabi_class; + + GEM_BUG_ON(uabi_class >= ARRAY_SIZE(class_instance)); + engine->uabi_instance = class_instance[uabi_class]++; /* * Replace the internal name with the final user and log facing @@ -238,11 +239,15 @@ void intel_engines_driver_register(struct drm_i915_private *i915) */ engine_rename(engine, intel_engine_class_repr(engine->class), - name_instance); + engine->uabi_instance); - if (engine->uabi_class == I915_NO_UABI_CLASS) + if (uabi_class > I915_LAST_UABI_ENGINE_CLASS) continue; + GEM_BUG_ON(uabi_class >= + ARRAY_SIZE(i915->engine_uabi_class_count)); + i915->engine_uabi_class_count[uabi_class]++; + rb_link_node(&engine->uabi_node, prev, p); rb_insert_color(&engine->uabi_node, &i915->uabi_engines); From patchwork Thu Aug 22 17:28:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43DD6C3DA4A for ; Thu, 22 Aug 2024 17:29:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A88E110EB8E; Thu, 22 Aug 2024 17:29:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="lHeRPjCr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 272EF10EB8D; Thu, 22 Aug 2024 17:29:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724347754; x=1755883754; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yuoaLHogE4J+aURd0F0ixJHZ0d7OeyV5+5WmcIZgjYY=; b=lHeRPjCrXVz0g9hkBCNTK+OTXmxdGbOl192EqTJ3hIfkKuIUQEoNjYvQ Jrq/nFfylFdzB5kO7ENy8fEEu0UAT6DAp8mwbXd6YBJzkjJ6UQoSOW+31 sA1zQ32IIopNmthNDv0oztxof1K3CnFDbOXcQUtkBPXbNoAb32NiEc9p/ F5Jc7HCeo+vaEAUfboC77eH+2nZEwUBhFzREa5LQGov6QZNhUnju5KFGT klheYrua68uHjG5dg9/lJ1QlyBSGtQUS/51fNWznh8PUvLwF2AHt0JQFV MVtx5emZNqhHACW+Ojuhg0k3BqnsM6jmyqc5XtqYAt07oGC9X+xTqKPLc A==; X-CSE-ConnectionGUID: 1edn/fIGQTGmvDPtK8j6og== X-CSE-MsgGUID: 5lNzCtsvSbuxM/wxgD8qpw== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="33448271" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="33448271" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:14 -0700 X-CSE-ConnectionGUID: 4IbWwxnESDGPs9+K6tmCcA== X-CSE-MsgGUID: xaEjc0XBQeGvDPjmQ2g9Kg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="61501135" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:12 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 05/15] drm/i915/gem: Mark and verify UABI engine validity Date: Thu, 22 Aug 2024 19:28:22 +0200 Message-ID: <20240822172832.494994-6-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Mark engines as invalid when they are not added to the UABI list to prevent accidental assignment of batch buffers. Currently, this change is mostly precautionary with minimal impact. However, in the future, when CCS engines will be dynamically added and removed by the user, this mechanism will be used for determining engine validity. Signed-off-by: Andi Shyti --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 28 +++++++++++++++++-- drivers/gpu/drm/i915/gt/intel_engine_user.c | 9 ++++-- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c58290274f97..770875e72056 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2682,6 +2682,22 @@ eb_select_legacy_ring(struct i915_execbuffer *eb) return user_ring_map[user_ring_id]; } +static bool engine_valid(struct intel_context *ce) +{ + if (!intel_engine_is_virtual(ce->engine)) + return !RB_EMPTY_NODE(&ce->engine->uabi_node); + + /* + * TODO: check virtual sibilings; we need to walk through all the + * virtual engines and ask whether the physical engine where it is based + * is still valid. For each of them we need to check with + * RB_EMPTY_NODE(...) + * + * This can be a placed in a new ce_ops. + */ + return true; +} + static int eb_select_engine(struct i915_execbuffer *eb) { @@ -2712,8 +2728,6 @@ eb_select_engine(struct i915_execbuffer *eb) eb->num_batches = ce->parallel.number_children + 1; gt = ce->engine->gt; - for_each_child(ce, child) - intel_context_get(child); eb->wakeref = intel_gt_pm_get(ce->engine->gt); /* * Keep GT0 active on MTL so that i915_vma_parked() doesn't @@ -2722,6 +2736,16 @@ eb_select_engine(struct i915_execbuffer *eb) if (gt->info.id) eb->wakeref_gt0 = intel_gt_pm_get(to_gt(gt->i915)); + /* We need to hold the wakeref to stabilize i915->uabi_engines */ + if (!engine_valid(ce)) { + intel_context_put(ce); + err = -ENODEV; + goto err; + } + + for_each_child(ce, child) + intel_context_get(child); + if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { err = intel_context_alloc_state(ce); if (err) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 11cc06c0c785..cd7662b1ad59 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -220,7 +220,7 @@ void intel_engines_driver_register(struct drm_i915_private *i915) container_of(it, typeof(*engine), uabi_list); if (intel_gt_has_unrecoverable_error(engine->gt)) - continue; /* ignore incomplete engines */ + goto clear_node_continue; /* ignore incomplete engines */ GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes)); engine->uabi_class = uabi_classes[engine->class]; @@ -242,7 +242,7 @@ void intel_engines_driver_register(struct drm_i915_private *i915) engine->uabi_instance); if (uabi_class > I915_LAST_UABI_ENGINE_CLASS) - continue; + goto clear_node_continue; GEM_BUG_ON(uabi_class >= ARRAY_SIZE(i915->engine_uabi_class_count)); @@ -260,6 +260,11 @@ void intel_engines_driver_register(struct drm_i915_private *i915) prev = &engine->uabi_node; p = &prev->rb_right; + + continue; + +clear_node_continue: + RB_CLEAR_NODE(&engine->uabi_node); } if (IS_ENABLED(CONFIG_DRM_I915_SELFTESTS) && From patchwork Thu Aug 22 17:28:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 951BAC52D7C for ; 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X-CSE-ConnectionGUID: kHiayj/zT4SO7ZRjtoXGpw== X-CSE-MsgGUID: 176vznWHQjq8cF3uPTSGtQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22935354" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="22935354" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:19 -0700 X-CSE-ConnectionGUID: NE/4J3CmQbi3u3CB0vfPUg== X-CSE-MsgGUID: lREevMtqQlirWeLo5xzedg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="84706361" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:17 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 06/15] drm/i915/gt: Introduce for_each_enabled_engine() and apply it in selftests Date: Thu, 22 Aug 2024 19:28:23 +0200 Message-ID: <20240822172832.494994-7-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Selftests should run only on enabled engines, as disabled engines are not intended for use. A practical example is when, on DG2 machines, the user chooses to utilize only one CCS stream instead of all four. To address this, introduce the for_each_enabled_engine() loop, which will skip engines when they are marked as RB_EMPTY. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt.h | 12 +++++ drivers/gpu/drm/i915/gt/selftest_context.c | 6 +-- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 4 +- .../drm/i915/gt/selftest_engine_heartbeat.c | 6 +-- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 6 +-- drivers/gpu/drm/i915/gt/selftest_execlists.c | 52 +++++++++---------- drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 22 ++++---- drivers/gpu/drm/i915/gt/selftest_lrc.c | 18 +++---- drivers/gpu/drm/i915/gt/selftest_mocs.c | 6 +-- drivers/gpu/drm/i915/gt/selftest_rc6.c | 4 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 8 +-- .../drm/i915/gt/selftest_ring_submission.c | 2 +- drivers/gpu/drm/i915/gt/selftest_rps.c | 14 ++--- drivers/gpu/drm/i915/gt/selftest_timeline.c | 14 ++--- drivers/gpu/drm/i915/gt/selftest_tlb.c | 2 +- .../gpu/drm/i915/gt/selftest_workarounds.c | 14 ++--- 17 files changed, 102 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 998ca029b73a..1c52db1b5e25 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -188,6 +188,18 @@ int intel_gt_tiles_init(struct drm_i915_private *i915); (id__)++) \ for_each_if ((engine__) = (gt__)->engine[(id__)]) +/* + * Iterator over all initialized and enabled engines. Some engines, like CCS, + * may be "disabled" (i.e., not exposed to the user). Disabling is indicated + * by marking the rb_node as empty. + */ +#define for_each_enabled_engine(engine__, gt__, id__) \ + for ((id__) = 0; \ + (id__) < I915_NUM_ENGINES; \ + (id__)++) \ + for_each_if ( ((engine__) = (gt__)->engine[(id__)]) && \ + (!RB_EMPTY_NODE(&(engine__)->uabi_node)) ) + /* Iterator over subset of engines selected by mask */ #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c index 5eb46700dc4e..9976e231248d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_context.c +++ b/drivers/gpu/drm/i915/gt/selftest_context.c @@ -157,7 +157,7 @@ static int live_context_size(void *arg) * HW tries to write past the end of one. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct file *saved; if (!engine->context_size) @@ -311,7 +311,7 @@ static int live_active_context(void *arg) enum intel_engine_id id; int err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = __live_active_context(engine); if (err) break; @@ -424,7 +424,7 @@ static int live_remote_context(void *arg) enum intel_engine_id id; int err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = __live_remote_context(engine); if (err) break; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c index 5ffa5e30f419..038723a401df 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c @@ -142,7 +142,7 @@ static int perf_mi_bb_start(void *arg) return 0; wakeref = perf_begin(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce = engine->kernel_context; struct i915_vma *batch; u32 cycles[COUNT]; @@ -270,7 +270,7 @@ static int perf_mi_noop(void *arg) return 0; wakeref = perf_begin(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce = engine->kernel_context; struct i915_vma *base, *nop; u32 cycles[COUNT]; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c index 9e4f0e417b3b..74d4c2dc69cf 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c @@ -160,7 +160,7 @@ static int live_idle_flush(void *arg) /* Check that we can flush the idle barriers */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { st_engine_heartbeat_disable(engine); err = __live_idle_pulse(engine, intel_engine_flush_barriers); st_engine_heartbeat_enable(engine); @@ -180,7 +180,7 @@ static int live_idle_pulse(void *arg) /* Check that heartbeat pulses flush the idle barriers */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { st_engine_heartbeat_disable(engine); err = __live_idle_pulse(engine, intel_engine_pulse); st_engine_heartbeat_enable(engine); @@ -246,7 +246,7 @@ static int live_heartbeat_off(void *arg) if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (!intel_engine_has_preemption(engine)) continue; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index 10e556a7eac4..1da3bddbf02e 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -203,7 +203,7 @@ static int live_engine_timestamps(void *arg) if (GRAPHICS_VER(gt->i915) < 8) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { int err; st_engine_heartbeat_disable(engine); @@ -257,7 +257,7 @@ static int live_engine_busy_stats(void *arg) return -ENOMEM; GEM_BUG_ON(intel_gt_pm_is_awake(gt)); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; ktime_t busyness, dummy; ktime_t de, dt; @@ -363,7 +363,7 @@ static int live_engine_pm(void *arg) } GEM_BUG_ON(intel_gt_pm_is_awake(gt)); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { const typeof(*igt_atomic_phases) *p; for (p = igt_atomic_phases; p->name; p++) { diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c index 4202df5b8c12..4179f9c0d650 100644 --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c @@ -120,7 +120,7 @@ static int live_sanitycheck(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; struct i915_request *rq; @@ -177,7 +177,7 @@ static int live_unlite_restore(struct intel_gt *gt, int prio) return err; err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce[2] = {}; struct i915_request *rq[2]; struct igt_live_test t; @@ -339,7 +339,7 @@ static int live_unlite_ring(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce[2] = {}; struct i915_request *rq; struct igt_live_test t; @@ -488,7 +488,7 @@ static int live_pin_rewind(void *arg) * To simulate this, let's apply a bit of deliberate sabotague. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; struct i915_request *rq; struct intel_ring *ring; @@ -596,7 +596,7 @@ static int live_hold_reset(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; struct i915_request *rq; @@ -703,7 +703,7 @@ static int live_error_interrupt(void *arg) if (!intel_has_reset_engine(gt)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { const struct error_phase *p; int err = 0; @@ -938,7 +938,7 @@ slice_semaphore_queue(struct intel_engine_cs *outer, if (IS_ERR(head)) return PTR_ERR(head); - for_each_engine(engine, outer->gt, id) { + for_each_enabled_engine(engine, outer->gt, id) { if (!intel_engine_has_preemption(engine)) continue; @@ -1018,7 +1018,7 @@ static int live_timeslice_preempt(void *arg) if (err) goto err_pin; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (!intel_engine_has_preemption(engine)) continue; @@ -1124,7 +1124,7 @@ static int live_timeslice_rewind(void *arg) if (!CONFIG_DRM_I915_TIMESLICE_DURATION) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { enum { A1, A2, B1 }; enum { X = 1, Z, Y }; struct i915_request *rq[3] = {}; @@ -1325,7 +1325,7 @@ static int live_timeslice_queue(void *arg) if (err) goto err_pin; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct i915_request *rq, *nop; @@ -1425,7 +1425,7 @@ static int live_timeslice_nopreempt(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; struct i915_request *rq; unsigned long timeslice; @@ -1578,7 +1578,7 @@ static int live_busywait_preempt(void *arg) if (err) goto err_vma; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *lo, *hi; struct igt_live_test t; u32 *cs; @@ -1754,7 +1754,7 @@ static int live_preempt(void *arg) if (igt_spinner_init(&spin_lo, gt)) goto err_spin_hi; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct igt_live_test t; struct i915_request *rq; @@ -1847,7 +1847,7 @@ static int live_late_preempt(void *arg) /* Make sure ctx_lo stays before ctx_hi until we trigger preemption. */ ctx_lo->sched.priority = 1; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct igt_live_test t; struct i915_request *rq; @@ -1969,7 +1969,7 @@ static int live_nopreempt(void *arg) goto err_client_a; b.ctx->sched.priority = I915_PRIORITY_MAX; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq_a, *rq_b; if (!intel_engine_has_preemption(engine)) @@ -2396,7 +2396,7 @@ static int live_preempt_cancel(void *arg) if (preempt_client_init(gt, &data.b)) goto err_client_a; - for_each_engine(data.engine, gt, id) { + for_each_enabled_engine(data.engine, gt, id) { if (!intel_engine_has_preemption(data.engine)) continue; @@ -2463,7 +2463,7 @@ static int live_suppress_self_preempt(void *arg) if (preempt_client_init(gt, &b)) goto err_client_a; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq_a, *rq_b; int depth; @@ -2570,7 +2570,7 @@ static int live_chain_preempt(void *arg) if (preempt_client_init(gt, &lo)) goto err_client_hi; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct igt_live_test t; struct i915_request *rq; @@ -2928,7 +2928,7 @@ static int live_preempt_ring(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { int n; if (!intel_engine_has_preemption(engine)) @@ -2971,7 +2971,7 @@ static int live_preempt_gang(void *arg) * high priority levels into execution order. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq = NULL; struct igt_live_test t; IGT_TIMEOUT(end_time); @@ -3277,7 +3277,7 @@ static int live_preempt_user(void *arg) return PTR_ERR(result); } - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *client[3] = {}; struct igt_live_test t; int i; @@ -3393,7 +3393,7 @@ static int live_preempt_timeout(void *arg) if (igt_spinner_init(&spin_lo, gt)) goto err_ctx_lo; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { unsigned long saved_timeout; struct i915_request *rq; @@ -3567,7 +3567,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) memset(arg, 0, I915_NUM_ENGINES * sizeof(*arg)); - for_each_engine(engine, smoke->gt, id) { + for_each_enabled_engine(engine, smoke->gt, id) { arg[id] = *smoke; arg[id].engine = engine; if (!(flags & BATCH)) @@ -3585,7 +3585,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) } count = 0; - for_each_engine(engine, smoke->gt, id) { + for_each_enabled_engine(engine, smoke->gt, id) { if (IS_ERR_OR_NULL(worker[id])) continue; @@ -3613,7 +3613,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags) count = 0; do { - for_each_engine(smoke->engine, smoke->gt, id) { + for_each_enabled_engine(smoke->engine, smoke->gt, id) { struct i915_gem_context *ctx = smoke_context(smoke); int err; @@ -3876,7 +3876,7 @@ static int live_virtual_engine(void *arg) if (intel_uc_uses_guc_submission(>->uc)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = nop_virtual_engine(gt, &engine, 1, 1, 0); if (err) { pr_err("Failed to wrap engine %s: err=%d\n", diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c index 33351deeea4f..ddc4b5623f19 100644 --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c @@ -95,7 +95,7 @@ static int live_gt_clocks(void *arg) wakeref = intel_gt_pm_get(gt); intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { u32 cycles; u32 expected; u64 time; diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 9ce8ff1c04fe..1bfdb7a80334 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -296,7 +296,7 @@ static int igt_hang_sanitycheck(void *arg) if (err) return err; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_wedge_me w; long timeout; @@ -360,7 +360,7 @@ static int igt_reset_nop(void *arg) reset_count = i915_reset_count(global); count = 0; do { - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; int i; @@ -433,7 +433,7 @@ static int igt_reset_nop_engine(void *arg) if (!intel_has_reset_engine(gt)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { unsigned int reset_count, reset_engine_count, count; struct intel_context *ce; IGT_TIMEOUT(end_time); @@ -553,7 +553,7 @@ static int igt_reset_fail_engine(void *arg) if (!intel_has_reset_engine(gt)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { unsigned int count; struct intel_context *ce; IGT_TIMEOUT(end_time); @@ -700,7 +700,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) return err; } - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { unsigned int reset_count, reset_engine_count; unsigned long count; bool using_guc = intel_engine_uses_guc(engine); @@ -990,7 +990,7 @@ static int __igt_reset_engines(struct intel_gt *gt, if (!threads) return -ENOMEM; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { unsigned long device = i915_reset_count(global); unsigned long count = 0, reported; bool using_guc = intel_engine_uses_guc(engine); @@ -1010,7 +1010,7 @@ static int __igt_reset_engines(struct intel_gt *gt, } memset(threads, 0, sizeof(*threads) * I915_NUM_ENGINES); - for_each_engine(other, gt, tmp) { + for_each_enabled_engine(other, gt, tmp) { struct kthread_worker *worker; threads[tmp].resets = @@ -1185,7 +1185,7 @@ static int __igt_reset_engines(struct intel_gt *gt, } unwind: - for_each_engine(other, gt, tmp) { + for_each_enabled_engine(other, gt, tmp) { int ret; if (!threads[tmp].worker) @@ -1621,7 +1621,7 @@ static int wait_for_others(struct intel_gt *gt, struct intel_engine_cs *engine; enum intel_engine_id id; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (engine == exclude) continue; @@ -1649,7 +1649,7 @@ static int igt_reset_queue(void *arg) if (err) goto unlock; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_selftest_saved_policy saved; struct i915_request *prev; IGT_TIMEOUT(end_time); @@ -1982,7 +1982,7 @@ static int igt_reset_engines_atomic(void *arg) struct intel_engine_cs *engine; enum intel_engine_id id; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = igt_atomic_reset_engine(engine, p); if (err) goto out; diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index e17b8777d21d..fa786b9eab8d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -171,7 +171,7 @@ static int live_lrc_layout(void *arg) GEM_BUG_ON(offset_in_page(lrc)); err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { u32 *hw; int dw; @@ -294,7 +294,7 @@ static int live_lrc_fixed(void *arg) * the context image. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { const struct { u32 reg; u32 offset; @@ -516,7 +516,7 @@ static int live_lrc_state(void *arg) if (IS_ERR(scratch)) return PTR_ERR(scratch); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = __live_lrc_state(engine, scratch); if (err) break; @@ -710,7 +710,7 @@ static int live_lrc_gpr(void *arg) if (IS_ERR(scratch)) return PTR_ERR(scratch); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { st_engine_heartbeat_disable(engine); err = __live_lrc_gpr(engine, scratch, false); @@ -867,7 +867,7 @@ static int live_lrc_timestamp(void *arg) * with a second request (carrying more poison into the timestamp). */ - for_each_engine(data.engine, gt, id) { + for_each_enabled_engine(data.engine, gt, id) { int i, err = 0; st_engine_heartbeat_disable(data.engine); @@ -1525,7 +1525,7 @@ static int live_lrc_isolation(void *arg) * context image and attempt to modify that list from a remote context. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { int i; /* Just don't even ask */ @@ -1713,7 +1713,7 @@ static int lrc_wabb_ctx(void *arg, bool per_ctx) enum intel_engine_id id; int err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { intel_engine_pm_get(engine); err = __lrc_wabb_ctx(engine, per_ctx); intel_engine_pm_put(engine); @@ -1849,7 +1849,7 @@ static int live_lrc_garbage(void *arg) if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { I915_RND_STATE(prng); int err = 0, i; @@ -1951,7 +1951,7 @@ static int live_pphwsp_runtime(void *arg) * is monotonic. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = __live_pphwsp_runtime(engine); if (err) break; diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index d73e438fb85f..6fd9fb0cd9f6 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -271,7 +271,7 @@ static int live_mocs_kernel(void *arg) if (err) return err; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { intel_engine_pm_get(engine); err = check_mocs_engine(&mocs, engine->kernel_context); intel_engine_pm_put(engine); @@ -297,7 +297,7 @@ static int live_mocs_clean(void *arg) if (err) return err; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; ce = mocs_context_create(engine); @@ -400,7 +400,7 @@ static int live_mocs_reset(void *arg) return err; igt_global_reset_lock(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { bool using_guc = intel_engine_uses_guc(engine); struct intel_selftest_saved_policy saved; struct intel_context *ce; diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c index 1aa1446c8fb0..ad60103c90a2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -165,7 +165,7 @@ randomised_engines(struct intel_gt *gt, int n; n = 0; - for_each_engine(engine, gt, id) + for_each_enabled_engine(engine, gt, id) n++; if (!n) return NULL; @@ -175,7 +175,7 @@ randomised_engines(struct intel_gt *gt, return NULL; n = 0; - for_each_engine(engine, gt, id) + for_each_enabled_engine(engine, gt, id) engines[n++] = engine; i915_prandom_shuffle(engines, sizeof(*engines), n, prng); diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c index 2cfc23c58e90..548e00ec47bd 100644 --- a/drivers/gpu/drm/i915/gt/selftest_reset.c +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c @@ -55,7 +55,7 @@ __igt_reset_stolen(struct intel_gt *gt, if (err) goto err_lock; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; struct i915_request *rq; @@ -113,7 +113,7 @@ __igt_reset_stolen(struct intel_gt *gt, if (mask == ALL_ENGINES) { intel_gt_reset(gt, mask, NULL); } else { - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (mask & engine->mask) intel_engine_reset(engine, NULL); } @@ -197,7 +197,7 @@ static int igt_reset_engines_stolen(void *arg) if (!intel_has_reset_engine(gt)) return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { err = __igt_reset_stolen(gt, engine->mask, engine->name); if (err) return err; @@ -326,7 +326,7 @@ static int igt_atomic_engine_reset(void *arg) if (!igt_force_reset(gt)) goto out_unlock; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct tasklet_struct *t = &engine->sched_engine->tasklet; if (t->func) diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c index 87ceb0f374b6..a447fec027e1 100644 --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c @@ -259,7 +259,7 @@ static int live_ctx_switch_wa(void *arg) * and equally important it was wasn't run when we don't! */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_vma *saved_wa; int err; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index dcef8d498919..49f23d19bd70 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -242,7 +242,7 @@ int live_rps_clock_interval(void *arg) intel_gt_check_clock_frequency(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; u32 cycles; u64 dt; @@ -401,7 +401,7 @@ int live_rps_control(void *arg) rps->work.func = dummy_rps_work; wakeref = intel_gt_pm_get(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; ktime_t min_dt, max_dt; int f, limit; @@ -629,7 +629,7 @@ int live_rps_frequency_cs(void *arg) saved_work = rps->work.func; rps->work.func = dummy_rps_work; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; struct i915_vma *vma; u32 *cancel, *cntr; @@ -768,7 +768,7 @@ int live_rps_frequency_srm(void *arg) saved_work = rps->work.func; rps->work.func = dummy_rps_work; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; struct i915_vma *vma; u32 *cancel, *cntr; @@ -1051,7 +1051,7 @@ int live_rps_interrupt(void *arg) saved_work = rps->work.func; rps->work.func = dummy_rps_work; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { /* Keep the engine busy with a spinner; expect an UP! */ if (pm_events & GEN6_PM_RP_UP_THRESHOLD) { intel_gt_pm_wait_for_idle(engine->gt); @@ -1157,7 +1157,7 @@ int live_rps_power(void *arg) saved_work = rps->work.func; rps->work.func = dummy_rps_work; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; struct { u64 power; @@ -1259,7 +1259,7 @@ int live_rps_dynamic(void *arg) if (intel_rps_uses_timer(rps)) pr_info("RPS has timer support\n"); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq; struct { ktime_t dt; diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c index fa36cf920bde..47d6f02808ba 100644 --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c @@ -543,7 +543,7 @@ static int live_hwsp_engine(void *arg) return -ENOMEM; count = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (!intel_engine_can_store_dword(engine)) continue; @@ -619,7 +619,7 @@ static int live_hwsp_alternate(void *arg) count = 0; for (n = 0; n < NUM_TIMELINES; n++) { - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_timeline *tl; struct i915_request *rq; @@ -691,7 +691,7 @@ static int live_hwsp_wrap(void *arg) if (err) goto out_free; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { const u32 *hwsp_seqno[2]; struct i915_request *rq; u32 seqno[2]; @@ -1016,7 +1016,7 @@ static int live_hwsp_read(void *arg) goto out; } - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; unsigned long count = 0; IGT_TIMEOUT(end_time); @@ -1188,7 +1188,7 @@ static int live_hwsp_rollover_kernel(void *arg) * see a seqno rollover. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce = engine->kernel_context; struct intel_timeline *tl = ce->timeline; struct i915_request *rq[3] = {}; @@ -1266,7 +1266,7 @@ static int live_hwsp_rollover_user(void *arg) * on the user's timeline. */ - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_request *rq[3] = {}; struct intel_timeline *tl; struct intel_context *ce; @@ -1357,7 +1357,7 @@ static int live_hwsp_recycle(void *arg) */ count = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { IGT_TIMEOUT(end_time); if (!intel_engine_can_store_dword(engine)) diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c b/drivers/gpu/drm/i915/gt/selftest_tlb.c index 3941f2d6fa47..ea52fe24901f 100644 --- a/drivers/gpu/drm/i915/gt/selftest_tlb.c +++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c @@ -293,7 +293,7 @@ mem_tlbinv(struct intel_gt *gt, } err = 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_gem_ww_ctx ww; struct intel_context *ce; int bit; diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 14a8b25b6204..55f9f5c556c3 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -70,7 +70,7 @@ reference_lists_init(struct intel_gt *gt, struct wa_lists *lists) gt_init_workarounds(gt, &lists->gt_wa_list); wa_init_finish(&lists->gt_wa_list); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct i915_wa_list *wal = &lists->engine[id].wa_list; wa_init_start(wal, gt, "REF", engine->name); @@ -89,7 +89,7 @@ reference_lists_fini(struct intel_gt *gt, struct wa_lists *lists) struct intel_engine_cs *engine; enum intel_engine_id id; - for_each_engine(engine, gt, id) + for_each_enabled_engine(engine, gt, id) intel_wa_list_free(&lists->engine[id].wa_list); intel_wa_list_free(&lists->gt_wa_list); @@ -764,7 +764,7 @@ static int live_dirty_whitelist(void *arg) if (GRAPHICS_VER(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */ return 0; - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; int err; @@ -794,7 +794,7 @@ static int live_reset_whitelist(void *arg) /* If we reset the gpu, we should not lose the RING_NONPRIV */ igt_global_reset_lock(gt); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { if (engine->whitelist.count == 0) continue; @@ -1089,7 +1089,7 @@ static int live_isolated_whitelist(void *arg) } } - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce[2]; if (!engine->kernel_context->vm) @@ -1172,7 +1172,7 @@ verify_wa_lists(struct intel_gt *gt, struct wa_lists *lists, ok &= wa_list_verify(gt, &lists->gt_wa_list, str); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_context *ce; ce = intel_context_create(engine); @@ -1257,7 +1257,7 @@ live_engine_reset_workarounds(void *arg) reference_lists_init(gt, lists); - for_each_engine(engine, gt, id) { + for_each_enabled_engine(engine, gt, id) { struct intel_selftest_saved_policy saved; bool using_guc = intel_engine_uses_guc(engine); bool ok; From patchwork Thu Aug 22 17:28:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5FB0C5321E for ; Thu, 22 Aug 2024 17:29:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 54A3610EB94; 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X-CSE-ConnectionGUID: eLLYfI2XR+2JLV0A9sW5HA== X-CSE-MsgGUID: M7OCqy+lTsW6Hjj7Tlt7Qg== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22935360" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="22935360" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:24 -0700 X-CSE-ConnectionGUID: SBP9oAheQTSFZlUshfq1cQ== X-CSE-MsgGUID: D7Ki1jU2TpSJM8/BBTKHVA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="84706375" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:22 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 07/15] drm/i915/gt: Manage CCS engine creation within UABI exposure Date: Thu, 22 Aug 2024 19:28:24 +0200 Message-ID: <20240822172832.494994-8-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In commit ea315f98e5d6 ("drm/i915/gt: Do not generate the command streamer for all the CCS"), we restricted the creation of physical CCS engines to only one stream. This allowed the user to submit a single compute workload, with all CCS slices sharing the workload from that stream. This patch removes that limitation but still exposes only one stream to the user. The physical memory for each engine remains allocated but unused, however the user will only see one engine exposed. Do this by adding only one engine to the UABI list, ensuring that only one engine is visible to the user. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 23 --------------------- drivers/gpu/drm/i915/gt/intel_engine_user.c | 17 ++++++++++++--- 2 files changed, 14 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 4d30a86016f2..def255ee0b96 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -876,29 +876,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) info->engine_mask &= ~BIT(GSC0); } - /* - * Do not create the command streamer for CCS slices beyond the first. - * All the workload submitted to the first engine will be shared among - * all the slices. - * - * Once the user will be allowed to customize the CCS mode, then this - * check needs to be removed. - */ - if (IS_DG2(gt->i915)) { - u8 first_ccs = __ffs(CCS_MASK(gt)); - - /* - * Store the number of active cslices before - * changing the CCS engine configuration - */ - gt->ccs.cslices = CCS_MASK(gt); - - /* Mask off all the CCS engine */ - info->engine_mask &= ~GENMASK(CCS3, CCS0); - /* Put back in the first CCS engine */ - info->engine_mask |= BIT(_CCS(first_ccs)); - } - return info->engine_mask; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index cd7662b1ad59..8e5284af8335 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -246,6 +246,20 @@ void intel_engines_driver_register(struct drm_i915_private *i915) GEM_BUG_ON(uabi_class >= ARRAY_SIZE(i915->engine_uabi_class_count)); + + /* Fix up the mapping to match default execbuf::user_map[] */ + add_legacy_ring(&ring, engine); + + /* + * Do not create the command streamer for CCS slices beyond the + * first. All the workload submitted to the first engine will be + * shared among all the slices. + */ + if (IS_DG2(i915) && + uabi_class == I915_ENGINE_CLASS_COMPUTE && + engine->uabi_instance) + goto clear_node_continue; + i915->engine_uabi_class_count[uabi_class]++; rb_link_node(&engine->uabi_node, prev, p); @@ -255,9 +269,6 @@ void intel_engines_driver_register(struct drm_i915_private *i915) engine->uabi_class, engine->uabi_instance) != engine); - /* Fix up the mapping to match default execbuf::user_map[] */ - add_legacy_ring(&ring, engine); - prev = &engine->uabi_node; p = &prev->rb_right; From patchwork Thu Aug 22 17:28:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D1BAC3DA4A for ; Thu, 22 Aug 2024 17:29:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0111910EB92; Thu, 22 Aug 2024 17:29:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FDN1u6Mx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id E191510EB92; Thu, 22 Aug 2024 17:29:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724347769; x=1755883769; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RZXagvd9a/iXlh5duGIJn7XPRJeVbbKXDz7sy800Ifs=; b=FDN1u6MxyCD6IGgADfPvzJhluLEFPVb+A2Yfcv/T7Q8M7uA/xh1K9RZA OYIZW11wgy4pZNdkLPtyTK4AnqtgWDf1qxGQX0BAD4dUimiEBZ2LH9nHE cmBwMo8rgliSH7tFg/hYHWV1H/+zxaqilDkm82z5ZNYzLItLxsg+qsRwl N1XWSq0VZ/rmQ2AHtIzZVYVaNb6IReWUzDrLYJsNhLygHCwc3mkqnrgOf J3dhFa6ylvZO5xxWRVeUut7EvcKqNEawxV8WYlhBnVVcoUv8qyKp3AQYH aHqiK3+sn3W/xwmsli3fAaWs1oaIX6NtIDgyrkRRTXLUikr92VOujby5h A==; X-CSE-ConnectionGUID: rPJXbT3GR3eb45zKBwI5sw== X-CSE-MsgGUID: V7QyAZsnTHOhBWkQx1blaw== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22935366" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="22935366" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:28 -0700 X-CSE-ConnectionGUID: 61bA9HpYT9+FhYRBoscSgg== X-CSE-MsgGUID: 3D1B/9lpTLSRaP6HgHRphA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="84706391" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:27 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 08/15] drm/i915/gt: Remove cslices mask value from the CCS structure Date: Thu, 22 Aug 2024 19:28:25 +0200 Message-ID: <20240822172832.494994-9-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Following the decision to manage CCS engine creation within UABI engines, the "cslices" variable in the "ccs" structure in the "gt" is no longer needed. Remove it is now redundant. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 ----- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index a6c33b471567..fc8a23fc28b6 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -9,7 +9,7 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { - unsigned long cslices_mask = gt->ccs.cslices; + unsigned long cslices_mask = CCS_MASK(gt); u32 mode_val = 0; /* CCS engine id, i.e. the engines position in the engine's bitmask */ int engine; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 9e257f34d05b..71e43071da0b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -218,11 +218,6 @@ struct intel_gt { * i.e. how the CCS streams are distributed amongs the slices. */ struct { - /* - * Mask of the non fused CCS slices - * to be used for the load balancing - */ - intel_engine_mask_t cslices; u32 mode_reg_val; } ccs; From patchwork Thu Aug 22 17:28:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9FF7FC3DA4A for ; Thu, 22 Aug 2024 17:29:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C70910EB96; Thu, 22 Aug 2024 17:29:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NyLyAXM3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id BFF8A10EB93; Thu, 22 Aug 2024 17:29:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724347773; x=1755883773; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jEGYw4KyKdqhB83EaX+pdmWXrOyBplimR5b19OZt8zY=; b=NyLyAXM3b2Q6465RprH88DT3IT0FBwhg08aMCqbJGnIoIR7kwiAkA8ny IAkN8zhRq1J/7R/mMvPvwkeZGJv/3mUlHv7PcrLcw7a8LcUC5nTLnoOCv 3piYUFXUvAEkKzPzb6CsNMQqweIyTRlorQz76PdL6WnKXMKlToRNP1GsE ieYsCwCTlzZU3Mu/GIeV7fWV2p3u/r/v0YAu/sFiDNDfHV/6xCJLgt0bH XCp0k3Qxnw7GJ18265YuJiJjEXkl6wSV/BZ1CBbV0kDJBjqbVjiEN5MHP RzjpQj/vxztHRhG8ga7s706bPETXLS6rtuGCylm65/cexH35ZaKS+EMJp g==; X-CSE-ConnectionGUID: ppuVzeFZQ+mtnFrjBwtb6g== X-CSE-MsgGUID: l1SgXmb9RuisLaA3v1rnTQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22935376" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="22935376" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:33 -0700 X-CSE-ConnectionGUID: rxuCELzvQt6DCklQZWKCSA== X-CSE-MsgGUID: oJQqyj8GQ0OVV8qyGuJ+1w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="84706408" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:31 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 09/15] drm/i915/gt: Expose the number of total CCS slices Date: Thu, 22 Aug 2024 19:28:26 +0200 Message-ID: <20240822172832.494994-10-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement a sysfs interface to show the number of available CCS slices. The displayed number does not take into account the CCS balancing mode. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 2 ++ 3 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index fc8a23fc28b6..edb6a4b63826 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -5,7 +5,9 @@ #include "i915_drv.h" #include "intel_gt_ccs_mode.h" +#include "intel_gt_print.h" #include "intel_gt_regs.h" +#include "intel_gt_sysfs.h" static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { @@ -100,3 +102,22 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) /* Initialize the CCS mode setting */ intel_gt_apply_ccs_mode(gt); } + +static ssize_t num_cslices_show(struct device *dev, + struct device_attribute *attr, + char *buff) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + u32 num_slices; + + num_slices = hweight32(CCS_MASK(gt)); + + return sysfs_emit(buff, "%u\n", num_slices); +} +static DEVICE_ATTR_RO(num_cslices); + +void intel_gt_sysfs_ccs_init(struct intel_gt *gt) +{ + if (sysfs_create_file(>->sysfs_gt, &dev_attr_num_cslices.attr)) + gt_warn(gt, "Failed to create sysfs num_cslices files\n"); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 4a6763b95a78..9696cc9017f6 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -9,5 +9,6 @@ #include "intel_gt.h" void intel_gt_ccs_mode_init(struct intel_gt *gt); +void intel_gt_sysfs_ccs_init(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c index 33cba406b569..895eedc402ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c @@ -12,6 +12,7 @@ #include "i915_drv.h" #include "i915_sysfs.h" #include "intel_gt.h" +#include "intel_gt_ccs_mode.h" #include "intel_gt_print.h" #include "intel_gt_sysfs.h" #include "intel_gt_sysfs_pm.h" @@ -101,6 +102,7 @@ void intel_gt_sysfs_register(struct intel_gt *gt) goto exit_fail; intel_gt_sysfs_pm_init(gt, >->sysfs_gt); + intel_gt_sysfs_ccs_init(gt); return; From patchwork Thu Aug 22 17:28:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80095C52D7C for ; Thu, 22 Aug 2024 17:29:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DB61210EB9D; Thu, 22 Aug 2024 17:29:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Nz0pCvEa"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id B6CC910EB9C; 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22 Aug 2024 10:29:38 -0700 X-CSE-ConnectionGUID: MWA9CRWlTNWj3FA6QeignQ== X-CSE-MsgGUID: t54Bmj7dT4aA4xnsmS07wA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="84706433" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:36 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 10/15] drm/i915/gt: Store engine-related sysfs kobjects Date: Thu, 22 Aug 2024 19:28:27 +0200 Message-ID: <20240822172832.494994-11-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Upcoming commits will need to access engine-related kobjects to enable the creation and destruction of sysfs interfaces at runtime. For this, store the "engine" directory (i915->sysfs_engine), the engine files (gt->kobj), and the default data (gt->kobj_defaults). Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 ++ drivers/gpu/drm/i915/gt/sysfs_engines.c | 4 ++++ drivers/gpu/drm/i915/i915_drv.h | 1 + 3 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index ba55c059063d..cdc695fda918 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -388,6 +388,8 @@ struct intel_engine_cs { u32 context_size; u32 mmio_base; + struct kobject *kobj; + struct intel_engine_tlb_inv tlb_inv; /* diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c b/drivers/gpu/drm/i915/gt/sysfs_engines.c index 021f51d9b456..f67f76df1cfe 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.c +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c @@ -506,6 +506,8 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) if (!dir) return; + i915->sysfs_engine = dir; + for_each_uabi_engine(engine, i915) { struct kobject *kobj; @@ -526,6 +528,8 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) add_defaults(container_of(kobj, struct kobj_engine, base)); + engine->kobj = kobj; + if (0) { err_object: kobject_put(kobj); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 94f7f6cc444c..3a8a757f5bd5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -320,6 +320,7 @@ struct drm_i915_private { struct intel_gt *gt[I915_MAX_GT]; struct kobject *sysfs_gt; + struct kobject *sysfs_engine; /* Quick lookup of media GT (current platforms only have one) */ struct intel_gt *media_gt; From patchwork Thu Aug 22 17:28:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECAC8C3DA4A for ; Thu, 22 Aug 2024 17:29:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7598310EB9A; Thu, 22 Aug 2024 17:29:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CGKCO4wp"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7669110EB99; Thu, 22 Aug 2024 17:29:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724347783; x=1755883783; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e+wURl4r29wSs0FL33YanvspYuQKsNNyQhEACXzu54g=; b=CGKCO4wp3UzuJV+CBJ5qAXeiat3MKTWauIMlv3IiS4ohWa1HdTsq0bPO mmBFJGhNf5l6cXgydXPgxQTW3GMcYfU29iCU/Ib+G9QSR5hheyI4l1Cbk 4fDgkp1xzH+mciqHK65RcKPXlreXjuO442PUwuHA/DFoPHXS0I1dFge+5 mDK36DO5DcyhU3W+jA2hPB14VvrnGq76hYsO/C3W08EVnD9KaHsTE9WeT 8n5Ef41rdf0gcP+XcRxxeRGLOhg0L7baSJUDaNCvsjcH/gdmAsUmFeJGt xRi6SLhKoO3SQ2C6exjCx2rB8JmWK/qqMcV7pcoPcmLVc/Kr6gWMyl070 Q==; X-CSE-ConnectionGUID: VUK9gRqiTdy4G7mlihk+HA== X-CSE-MsgGUID: JIfq2mKLRZmlPuW/YXmHBg== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22935389" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="22935389" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:43 -0700 X-CSE-ConnectionGUID: 5GE5rZp1ShWlBfiziVwRXg== X-CSE-MsgGUID: Xd4YWbslQESXvJuSyi5kqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="84706449" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:41 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 11/15] drm/i915/gt: Store active CCS mask Date: Thu, 22 Aug 2024 19:28:28 +0200 Message-ID: <20240822172832.494994-12-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To support upcoming patches, we need to store the current mask for active CCS engines. Active engines refer to those exposed to userspace via the UABI engine list. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 41 +++++++++++++++++++-- drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 ++++ 2 files changed, 44 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index edb6a4b63826..5eead7b18f57 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -12,6 +12,7 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { unsigned long cslices_mask = CCS_MASK(gt); + unsigned long ccs_mask = gt->ccs.id_mask; u32 mode_val = 0; /* CCS engine id, i.e. the engines position in the engine's bitmask */ int engine; @@ -55,7 +56,7 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) * slice 2: ccs2 * slice 3: ccs3 */ - engine = __ffs(cslices_mask); + engine = __ffs(ccs_mask); for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { if (!(cslices_mask & BIT(cslice))) { @@ -86,7 +87,7 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) * CCS mode, will be used later to * reset to a flexible value */ - engine = __ffs(cslices_mask); + engine = __ffs(ccs_mask); continue; } } @@ -94,13 +95,45 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) gt->ccs.mode_reg_val = mode_val; } +static void __update_ccs_mask(struct intel_gt *gt, u32 ccs_mode) +{ + unsigned long cslices_mask = CCS_MASK(gt); + int i; + + /* Mask off all the CCS engines */ + gt->ccs.id_mask = 0; + + for_each_set_bit(i, &cslices_mask, I915_MAX_CCS) { + gt->ccs.id_mask |= BIT(i); + + ccs_mode--; + if (!ccs_mode) + break; + } + + /* + * It's impossible for 'ccs_mode' to be zero at this point. + * This scenario would only occur if the 'ccs_mode' provided by + * the caller exceeded the total number of CCS engines, a condition + * we check before calling the 'update_ccs_mask()' function. + */ + GEM_BUG_ON(ccs_mode); + + /* Initialize the CCS mode setting */ + intel_gt_apply_ccs_mode(gt); +} + void intel_gt_ccs_mode_init(struct intel_gt *gt) { if (!IS_DG2(gt->i915)) return; - /* Initialize the CCS mode setting */ - intel_gt_apply_ccs_mode(gt); + /* + * Set CCS balance mode 1 in the ccs_mask. + * + * During init the workaround are not set up yet. + */ + __update_ccs_mask(gt, 1); } static ssize_t num_cslices_show(struct device *dev, diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 71e43071da0b..641be69016e1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -219,6 +219,13 @@ struct intel_gt { */ struct { u32 mode_reg_val; + + /* + * CCS id_mask is the command streamer instance + * exposed to the user. While the CCS_MASK(gt) + * is the available unfused compute slices. + */ + intel_engine_mask_t id_mask; } ccs; /* From patchwork Thu Aug 22 17:28:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8235FC5321D for ; Thu, 22 Aug 2024 17:29:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EBA8C10EB9B; Thu, 22 Aug 2024 17:29:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MMpzOLgT"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id DFF9010EB99; Thu, 22 Aug 2024 17:29:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724347789; x=1755883789; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R+6ZlsH+1XWqkejIIzB9mWSBuTWypOFHaaSBbN0dS/g=; b=MMpzOLgTGPMsUsBmj/7TSmZ8hjASqLzB+KhrM4e/CVucmLGzh1D064a/ 0jEEapufq3liSNEIao/cd4bJih/q/gGK1wMhGg+Fn8wDybT1hSXLGx8JH NYOXcIhEjrbcWyE/aLnigIGVAM4lgcMtADaEHIGpbVOK38T5w7j5UkeLk hZ3tUNFLQTuQcHBtnDaWnMwWrs3QCk88YXptriwteJ7QOxB+wSKHbNucg oN7tFiOft/eVaKPhqU+fFeSMnVj2d9trnJlfOenIuGTZ+Woiv7gjDOIrS y18/y2lk1W+7UfCzNXlMYjvF/koTn/QH4dRVt0cuyAmGDIOf8MepXFNHg g==; X-CSE-ConnectionGUID: sh7K98lzQjODKLJIOzo/xw== X-CSE-MsgGUID: jReg11D1TdqgSyMLZY7syQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22935404" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="22935404" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:48 -0700 X-CSE-ConnectionGUID: k+kJu7VhSg+fjwIpUAUP3w== X-CSE-MsgGUID: wnAjjQm1RIOTScRRt3FYNQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="84706486" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:46 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 12/15] drm/i915: Protect access to the UABI engines list with a mutex Date: Thu, 22 Aug 2024 19:28:29 +0200 Message-ID: <20240822172832.494994-13-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Until now, the UABI engines list has been accessed in read-only mode, as it was created once during boot and destroyed upon module unload. In upcoming commits, we will be modifying this list by changing the CCS mode, allowing compute engines to be dynamically added and removed at runtime based on user whims. To ensure thread safety and prevent race conditions, we need to protect the engine list with a mutex, thereby serializing access to it. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 3 +++ drivers/gpu/drm/i915/gt/intel_engine_user.c | 7 +++++++ drivers/gpu/drm/i915/gt/sysfs_engines.c | 5 +++++ drivers/gpu/drm/i915/i915_cmd_parser.c | 2 ++ drivers/gpu/drm/i915/i915_debugfs.c | 4 ++++ drivers/gpu/drm/i915/i915_drv.h | 4 ++++ drivers/gpu/drm/i915/i915_gem.c | 4 ++++ drivers/gpu/drm/i915/i915_perf.c | 2 ++ drivers/gpu/drm/i915/i915_pmu.c | 4 ++++ drivers/gpu/drm/i915/i915_query.c | 2 ++ 10 files changed, 37 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index c0543c35cd6a..0ccbe447f51d 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -1124,6 +1124,7 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx, if (!e) return ERR_PTR(-ENOMEM); + mutex_lock(&ctx->i915->uabi_engines_mutex); for_each_uabi_engine(engine, ctx->i915) { struct intel_context *ce; struct intel_sseu sseu = {}; @@ -1155,9 +1156,11 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx, } + mutex_unlock(&ctx->i915->uabi_engines_mutex); return e; free_engines: + mutex_unlock(&ctx->i915->uabi_engines_mutex); free_engines(e); return err; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 8e5284af8335..209d5badbd3d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -210,6 +210,13 @@ void intel_engines_driver_register(struct drm_i915_private *i915) LIST_HEAD(engines); sort_engines(i915, &engines); + mutex_init(&i915->uabi_engines_mutex); + + /* + * We are still booting i915 and we are sure we are running + * single-threaded. We don't need at this point to protect the + * uabi_engines access list with the mutex. + */ prev = NULL; p = &i915->uabi_engines.rb_node; diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c b/drivers/gpu/drm/i915/gt/sysfs_engines.c index f67f76df1cfe..c1cc0981c8fb 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.c +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c @@ -508,6 +508,11 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) i915->sysfs_engine = dir; + /* + * We are still booting i915 and we are sure we are running + * single-threaded. We don't need at this point to protect the + * uabi_engines access list with the mutex. + */ for_each_uabi_engine(engine, i915) { struct kobject *kobj; diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 2905df83e180..12987ece6f8e 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -1592,12 +1592,14 @@ int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) bool active = false; /* If the command parser is not enabled, report 0 - unsupported */ + mutex_lock(&dev_priv->uabi_engines_mutex); for_each_uabi_engine(engine, dev_priv) { if (intel_engine_using_cmd_parser(engine)) { active = true; break; } } + mutex_unlock(&dev_priv->uabi_engines_mutex); if (!active) return 0; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index bc717cf544e4..8b5e365eb6bd 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -459,8 +459,10 @@ static int i915_engine_info(struct seq_file *m, void *unused) to_gt(i915)->clock_period_ns); p = drm_seq_file_printer(m); + mutex_lock(&i915->uabi_engines_mutex); for_each_uabi_engine(engine, i915) intel_engine_dump(engine, &p, "%s\n", engine->name); + mutex_unlock(&i915->uabi_engines_mutex); intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule); @@ -474,6 +476,7 @@ static int i915_wa_registers(struct seq_file *m, void *unused) struct drm_i915_private *i915 = node_to_i915(m->private); struct intel_engine_cs *engine; + mutex_lock(&i915->uabi_engines_mutex); for_each_uabi_engine(engine, i915) { const struct i915_wa_list *wal = &engine->ctx_wa_list; const struct i915_wa *wa; @@ -493,6 +496,7 @@ static int i915_wa_registers(struct seq_file *m, void *unused) seq_printf(m, "\n"); } + mutex_unlock(&i915->uabi_engines_mutex); return 0; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3a8a757f5bd5..5210e130ca0c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -231,6 +231,10 @@ struct drm_i915_private { struct rb_root uabi_engines; }; unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; + /* + * Protect access to the uabi_engines list. + */ + struct mutex uabi_engines_mutex; /* protects the irq masks */ spinlock_t irq_lock; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1391c01d7663..36eab0d31756 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1263,7 +1263,11 @@ void i915_gem_driver_remove(struct drm_i915_private *dev_priv) i915_gem_suspend_late(dev_priv); for_each_gt(gt, dev_priv, i) intel_gt_driver_remove(gt); + + /* Let's make sure no one is using the uabi_engines list */ + mutex_lock(>->i915->uabi_engines_mutex); dev_priv->uabi_engines = RB_ROOT; + mutex_unlock(>->i915->uabi_engines_mutex); /* Flush any outstanding unpin_work. */ i915_gem_drain_workqueue(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 025a79fe5920..40850a4e8f2e 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2732,6 +2732,7 @@ oa_configure_all_contexts(struct i915_perf_stream *stream, * If we don't modify the kernel_context, we do not get events while * idle. */ + mutex_lock(&i915->uabi_engines_mutex); for_each_uabi_engine(engine, i915) { struct intel_context *ce = engine->kernel_context; @@ -2744,6 +2745,7 @@ oa_configure_all_contexts(struct i915_perf_stream *stream, if (err) return err; } + mutex_unlock(&i915->uabi_engines_mutex); return 0; } diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 21eb0c5b320d..bcef2d460680 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -1022,6 +1022,7 @@ create_event_attributes(struct i915_pmu *pmu) } } + mutex_lock(&i915->uabi_engines_mutex); for_each_uabi_engine(engine, i915) { for (i = 0; i < ARRAY_SIZE(engine_events); i++) { if (!engine_event_status(engine, @@ -1029,6 +1030,7 @@ create_event_attributes(struct i915_pmu *pmu) count++; } } + mutex_unlock(&i915->uabi_engines_mutex); /* Allocate attribute objects and table. */ i915_attr = kcalloc(count, sizeof(*i915_attr), GFP_KERNEL); @@ -1086,6 +1088,7 @@ create_event_attributes(struct i915_pmu *pmu) } /* Initialize supported engine counters. */ + mutex_lock(&i915->uabi_engines_mutex); for_each_uabi_engine(engine, i915) { for (i = 0; i < ARRAY_SIZE(engine_events); i++) { char *str; @@ -1115,6 +1118,7 @@ create_event_attributes(struct i915_pmu *pmu) pmu_iter = add_pmu_attr(pmu_iter, str, "ns"); } } + mutex_unlock(&i915->uabi_engines_mutex); pmu->i915_attr = i915_attr; pmu->pmu_attr = pmu_attr; diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 14d9ec0ed777..730df29b4728 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -140,6 +140,7 @@ query_engine_info(struct drm_i915_private *i915, if (query_item->flags) return -EINVAL; + mutex_lock(&i915->uabi_engines_mutex); for_each_uabi_engine(engine, i915) num_uabi_engines++; @@ -168,6 +169,7 @@ query_engine_info(struct drm_i915_private *i915, query.num_engines++; info_ptr++; } + mutex_unlock(&i915->uabi_engines_mutex); if (copy_to_user(query_ptr, &query, sizeof(query))) return -EFAULT; From patchwork Thu Aug 22 17:28:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BA46C52D7C for ; Thu, 22 Aug 2024 17:30:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 141B510EB9C; Thu, 22 Aug 2024 17:30:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ce9psKNN"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id E349A10EB9C; Thu, 22 Aug 2024 17:30:01 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="62225847" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:52 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 13/15] drm/i915/gt: Isolate single sysfs engine file creation Date: Thu, 22 Aug 2024 19:28:30 +0200 Message-ID: <20240822172832.494994-14-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for upcoming patches, we need the ability to create and remove individual sysfs files. To facilitate this, extract from the intel_engines_add_sysfs() function the creation of individual files. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/sysfs_engines.c | 74 +++++++++++++++---------- drivers/gpu/drm/i915/gt/sysfs_engines.h | 2 + 2 files changed, 48 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c b/drivers/gpu/drm/i915/gt/sysfs_engines.c index c1cc0981c8fb..ef2eda72ac7f 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.c +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "intel_engine.h" #include "intel_engine_heartbeat.h" +#include "intel_gt_print.h" #include "sysfs_engines.h" struct kobj_engine { @@ -481,7 +482,7 @@ static void add_defaults(struct kobj_engine *parent) return; } -void intel_engines_add_sysfs(struct drm_i915_private *i915) +int intel_engine_add_single_sysfs(struct intel_engine_cs *engine) { static const struct attribute * const files[] = { &name_attr.attr, @@ -497,7 +498,48 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) #endif NULL }; + struct kobject *dir = engine->i915->sysfs_engine; + struct kobject *kobj = engine->kobj; + int err; + + kobj = kobj_engine(dir, engine); + if (!kobj) { + err = -EFAULT; + goto err_engine; + } + + err = sysfs_create_files(kobj, files); + if (err) + goto err_object; + + if (intel_engine_has_timeslices(engine)) { + err = sysfs_create_file(kobj, ×lice_duration_attr.attr); + if (err) + goto err_object; + } + + if (intel_engine_has_preempt_reset(engine)) { + err = sysfs_create_file(kobj, &preempt_timeout_attr.attr); + if (err) + goto err_object; + } + + add_defaults(container_of(kobj, struct kobj_engine, base)); + + engine->kobj = kobj; + + return 0; + +err_object: + kobject_put(kobj); +err_engine: + gt_warn(engine->gt, "Failed to add sysfs engine '%s'\n", engine->name); + + return err; +} +void intel_engines_add_sysfs(struct drm_i915_private *i915) +{ struct device *kdev = i915->drm.primary->kdev; struct intel_engine_cs *engine; struct kobject *dir; @@ -514,34 +556,10 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) * uabi_engines access list with the mutex. */ for_each_uabi_engine(engine, i915) { - struct kobject *kobj; - - kobj = kobj_engine(dir, engine); - if (!kobj) - goto err_engine; - - if (sysfs_create_files(kobj, files)) - goto err_object; - - if (intel_engine_has_timeslices(engine) && - sysfs_create_file(kobj, ×lice_duration_attr.attr)) - goto err_engine; - - if (intel_engine_has_preempt_reset(engine) && - sysfs_create_file(kobj, &preempt_timeout_attr.attr)) - goto err_engine; - - add_defaults(container_of(kobj, struct kobj_engine, base)); + int err; - engine->kobj = kobj; - - if (0) { -err_object: - kobject_put(kobj); -err_engine: - dev_err(kdev, "Failed to add sysfs engine '%s'\n", - engine->name); + err = intel_engine_add_single_sysfs(engine); + if (err) break; - } } } diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.h b/drivers/gpu/drm/i915/gt/sysfs_engines.h index 9546fffe03a7..2e3ec2df14a9 100644 --- a/drivers/gpu/drm/i915/gt/sysfs_engines.h +++ b/drivers/gpu/drm/i915/gt/sysfs_engines.h @@ -7,7 +7,9 @@ #define INTEL_ENGINE_SYSFS_H struct drm_i915_private; +struct intel_engine_cs; void intel_engines_add_sysfs(struct drm_i915_private *i915); +int intel_engine_add_single_sysfs(struct intel_engine_cs *engine); #endif /* INTEL_ENGINE_SYSFS_H */ From patchwork Thu Aug 22 17:28:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13773986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60A96C3DA4A for ; Thu, 22 Aug 2024 17:30:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CFCF210EBA0; Thu, 22 Aug 2024 17:30:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="RDQEIg0N"; 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d="scan'208";a="34164084" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:59 -0700 X-CSE-ConnectionGUID: nMyvcTHkQF+h/XxhTKYH/A== X-CSE-MsgGUID: edeOH79gTUWtbNgcMQSWEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="62225850" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:29:57 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 14/15] drm/i915/gt: Implement creation and removal routines for CCS engines Date: Thu, 22 Aug 2024 19:28:31 +0200 Message-ID: <20240822172832.494994-15-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for upcoming patches, we need routines to dynamically create and destroy CCS engines based on the CCS mode that the user wants to set. The process begins by calculating the engine mask for the engines that need to be added or removed. We then update the UABI list of exposed engines and create or destroy the corresponding sysfs interfaces accordingly. These functions are not yet in use, so no functional changes are intended at this stage. Mark the functions 'add_uabi_ccs_engines()' and 'remove_uabi_ccs_engines()' as '__maybe_unused' to ensure successful compilation and maintain bisectability. This annotation will be removed in subsequent commits. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 123 ++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 5eead7b18f57..4462e07ee903 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -4,10 +4,12 @@ */ #include "i915_drv.h" +#include "intel_engine_user.h" #include "intel_gt_ccs_mode.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" #include "intel_gt_sysfs.h" +#include "sysfs_engines.h" static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { @@ -123,6 +125,29 @@ static void __update_ccs_mask(struct intel_gt *gt, u32 ccs_mode) intel_gt_apply_ccs_mode(gt); } +static void update_ccs_mask(struct intel_gt *gt, u32 ccs_mode) +{ + struct intel_engine_cs *engine; + intel_engine_mask_t tmp; + + __update_ccs_mask(gt, ccs_mode); + + /* Update workaround values */ + for_each_engine_masked(engine, gt, gt->ccs.id_mask, tmp) { + struct i915_wa_list *wal = &engine->wa_list; + struct i915_wa *wa; + int i; + + for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { + if (!i915_mmio_reg_equal(wa->reg, XEHP_CCS_MODE)) + continue; + + wa->set = gt->ccs.mode_reg_val; + wa->read = gt->ccs.mode_reg_val; + } + } +} + void intel_gt_ccs_mode_init(struct intel_gt *gt) { if (!IS_DG2(gt->i915)) @@ -136,6 +161,104 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) __update_ccs_mask(gt, 1); } +static int rb_engine_cmp(struct rb_node *rb_new, const struct rb_node *rb_old) +{ + struct intel_engine_cs *new = rb_to_uabi_engine(rb_new); + struct intel_engine_cs *old = rb_to_uabi_engine(rb_old); + + if (new->uabi_class - old->uabi_class == 0) + return new->uabi_instance - old->uabi_instance; + + return new->uabi_class - old->uabi_class; +} + +static void __maybe_unused add_uabi_ccs_engines(struct intel_gt *gt, u32 ccs_mode) +{ + struct drm_i915_private *i915 = gt->i915; + intel_engine_mask_t new_ccs_mask, tmp; + struct intel_engine_cs *e; + + /* Store the current ccs mask */ + new_ccs_mask = gt->ccs.id_mask; + update_ccs_mask(gt, ccs_mode); + + /* + * Store only the mask of the CCS engines that need to be added by + * removing from the new mask the engines that are already active + */ + new_ccs_mask = gt->ccs.id_mask & ~new_ccs_mask; + new_ccs_mask <<= CCS0; + + for_each_engine_masked(e, gt, new_ccs_mask, tmp) { + int err; + + i915->engine_uabi_class_count[I915_ENGINE_CLASS_COMPUTE]++; + + /* + * The engine is now inserted and marked as valid. + * + * rb_find_add() should always return NULL. If it returns a + * pointer to an rb_node it means that it found the engine we + * are trying to insert which means that something is really + * wrong. + */ + if (rb_find_add(&e->uabi_node, + &i915->uabi_engines, rb_engine_cmp)) { + gt_err(gt, "Failed to apply CCS mode!\n"); + return; + } + + /* We inserted the engine, let's check if now we can find it */ + GEM_BUG_ON(intel_engine_lookup_user(i915, e->uabi_class, + e->uabi_instance) != e); + + /* + * If the engine has never been used before (e.g. we are moving + * for the first time from CCS mode 1 to CCS mode 2 or 4), then + * also its sysfs entry has never been created. In this case its + * value will be null and we need to allocate it. + */ + if (!e->kobj) + err = intel_engine_add_single_sysfs(e); + else + err = kobject_add(e->kobj, + i915->sysfs_engine, "%s", e->name); + + if (err) + gt_warn(gt, + "Unable to create sysfs entries for %s engine", + e->name); + } +} + +static void __maybe_unused remove_uabi_ccs_engines(struct intel_gt *gt, u8 ccs_mode) +{ + struct drm_i915_private *i915 = gt->i915; + intel_engine_mask_t new_ccs_mask, tmp; + struct intel_engine_cs *e; + + /* Store the current ccs mask */ + new_ccs_mask = gt->ccs.id_mask; + update_ccs_mask(gt, ccs_mode); + + /* + * Store only the mask of the CCS engines that need to be removed by + * unmasking them from the new mask the engines that are already active + */ + new_ccs_mask = new_ccs_mask & ~gt->ccs.id_mask; + new_ccs_mask <<= CCS0; + + for_each_engine_masked(e, gt, new_ccs_mask, tmp) { + i915->engine_uabi_class_count[I915_ENGINE_CLASS_COMPUTE]--; + + rb_erase(&e->uabi_node, &i915->uabi_engines); + RB_CLEAR_NODE(&e->uabi_node); + + /* Remove sysfs entries */ + kobject_del(e->kobj); + } +} + static ssize_t num_cslices_show(struct device *dev, struct device_attribute *attr, char *buff) From patchwork Thu Aug 22 17:28:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13774004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F4A4C52D7C for ; Thu, 22 Aug 2024 17:30:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0344610EB9F; Thu, 22 Aug 2024 17:30:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mSSFew0+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 36C1910EBA2; Thu, 22 Aug 2024 17:30:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724347805; x=1755883805; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uP/mkNzyOCjkw3CWxQgWY32MvUawl2y/kvqpsVqVuPY=; b=mSSFew0+IpZgWpuUSTq0a2eJAZnAXfAb2nL+gwW6QnM2PHpXNHA7hP6R AtHjM+sdfzNJJVXJGS7Xxx1zzujab3a0xjiPoonnO26o484kwKOXAWsZM 5WRfmySCy8gAdWaH91GNUzEyLWIqH5cyrBVVFAOs3wE4XsF9ntXiRytRV 4GquaGRXJ9GobcDKzFgpp6MmkhyeGr8uxnHNMTqfMBKYfmwWXOTNbUDvt rj6sVlbdtVExeb52WfS1srHgTBvkSYDkFm+L8LYl/cwdOW0YIQpRtI2Pk mx/MKyKmSMfSZ3apNtSboO0eH3yFmL02tr46ZayqFu/dchVamcq3FqV/0 Q==; X-CSE-ConnectionGUID: z+S0HX35RDO/82kjUcg86g== X-CSE-MsgGUID: +IfCI4KoTwm5kCkN5dp61A== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="34164098" X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="34164098" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:30:04 -0700 X-CSE-ConnectionGUID: lUry2Lc1QIaebATnscnmGA== X-CSE-MsgGUID: v3cFE2A1QOqF6vLY02lZQw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,167,1719903600"; d="scan'208";a="62225860" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO intel.com) ([10.245.246.104]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 10:30:02 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v2 15/15] drm/i915/gt: Allow the user to change the CCS mode through sysfs Date: Thu, 22 Aug 2024 19:28:32 +0200 Message-ID: <20240822172832.494994-16-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240822172832.494994-1-andi.shyti@linux.intel.com> References: <20240822172832.494994-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Create the 'ccs_mode' file under /sys/class/drm/cardX/gt/gt0/ccs_mode This file allows the user to read and set the current CCS mode. - Reading: The user can read the current CCS mode, which can be 1, 2, or 4. This value is derived from the current engine mask. - Writing: The user can set the CCS mode to 1, 2, or 4, depending on the desired number of exposed engines and the required load balancing. The interface will return -EBUSY if other clients are connected to i915, or -EINVAL if an invalid value is set. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 82 ++++++++++++++++++++- 1 file changed, 80 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 4462e07ee903..b0f69ae435ca 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -6,6 +6,7 @@ #include "i915_drv.h" #include "intel_engine_user.h" #include "intel_gt_ccs_mode.h" +#include "intel_gt_pm.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" #include "intel_gt_sysfs.h" @@ -172,7 +173,7 @@ static int rb_engine_cmp(struct rb_node *rb_new, const struct rb_node *rb_old) return new->uabi_class - old->uabi_class; } -static void __maybe_unused add_uabi_ccs_engines(struct intel_gt *gt, u32 ccs_mode) +static void add_uabi_ccs_engines(struct intel_gt *gt, u32 ccs_mode) { struct drm_i915_private *i915 = gt->i915; intel_engine_mask_t new_ccs_mask, tmp; @@ -231,7 +232,7 @@ static void __maybe_unused add_uabi_ccs_engines(struct intel_gt *gt, u32 ccs_mod } } -static void __maybe_unused remove_uabi_ccs_engines(struct intel_gt *gt, u8 ccs_mode) +static void remove_uabi_ccs_engines(struct intel_gt *gt, u8 ccs_mode) { struct drm_i915_private *i915 = gt->i915; intel_engine_mask_t new_ccs_mask, tmp; @@ -272,8 +273,85 @@ static ssize_t num_cslices_show(struct device *dev, } static DEVICE_ATTR_RO(num_cslices); +static ssize_t ccs_mode_show(struct device *dev, + struct device_attribute *attr, char *buff) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + u32 ccs_mode; + + ccs_mode = hweight32(gt->ccs.id_mask); + + return sysfs_emit(buff, "%u\n", ccs_mode); +} + +static ssize_t ccs_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buff, size_t count) +{ + struct intel_gt *gt = kobj_to_gt(&dev->kobj); + int num_cslices = hweight32(CCS_MASK(gt)); + int ccs_mode = hweight32(gt->ccs.id_mask); + ssize_t ret; + u32 val; + + ret = kstrtou32(buff, 0, &val); + if (ret) + return ret; + + /* + * As of now possible values to be set are 1, 2, 4, + * up to the maximum number of available slices + */ + if (!val || val > num_cslices || (num_cslices % val)) + return -EINVAL; + + /* Let's wait until the GT is no longer in use */ + ret = intel_gt_pm_wait_for_idle(gt); + if (ret) + return ret; + + mutex_lock(>->wakeref.mutex); + + /* + * Let's check again that the GT is idle, + * we don't want to change the CCS mode + * while someone is using the GT + */ + if (intel_gt_pm_is_awake(gt)) { + ret = -EBUSY; + goto out; + } + + /* + * Nothing to do if the requested setting + * is the same as the current one + */ + if (val == ccs_mode) + goto out; + else if (val > ccs_mode) + add_uabi_ccs_engines(gt, val); + else + remove_uabi_ccs_engines(gt, val); + +out: + mutex_unlock(>->wakeref.mutex); + + return ret ?: count; +} +static DEVICE_ATTR_RW(ccs_mode); + void intel_gt_sysfs_ccs_init(struct intel_gt *gt) { if (sysfs_create_file(>->sysfs_gt, &dev_attr_num_cslices.attr)) gt_warn(gt, "Failed to create sysfs num_cslices files\n"); + + /* + * Do not create the ccs_mode file for non DG2 platforms + * because they don't need it as they have only one CCS engine + */ + if (!IS_DG2(gt->i915)) + return; + + if (sysfs_create_file(>->sysfs_gt, &dev_attr_ccs_mode.attr)) + gt_warn(gt, "Failed to create sysfs ccs_mode files\n"); }