From patchwork Wed Mar 6 10:41:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 10840841 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD3DD1575 for ; Wed, 6 Mar 2019 10:41:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C0DBC2CFA0 for ; Wed, 6 Mar 2019 10:41:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B0F732D1FE; Wed, 6 Mar 2019 10:41:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 282C52CFA0 for ; Wed, 6 Mar 2019 10:41:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729414AbfCFKlb (ORCPT ); Wed, 6 Mar 2019 05:41:31 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:18526 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729223AbfCFKlb (ORCPT ); Wed, 6 Mar 2019 05:41:31 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 06 Mar 2019 02:41:29 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 06 Mar 2019 02:41:28 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 06 Mar 2019 02:41:28 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 6 Mar 2019 10:41:28 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 6 Mar 2019 10:41:28 +0000 Received: from linux.nvidia.com (Not Verified[10.24.34.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 06 Mar 2019 02:41:27 -0800 From: Sameer Pujar To: , , , , CC: , , , , , , , Sameer Pujar Subject: [PATCH 1/3] bus: tegra-aconnect: use devm_clk_*() helpers Date: Wed, 6 Mar 2019 16:11:16 +0530 Message-ID: <1551868878-1131-1-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551868889; bh=2P8UBw6vXPbZ7oSbE4OEK5sJXWd0pcAkC41A42Jcnic=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:Content-Type; b=hXP+Yies2msM77JGhBBBQgLwuQ9FFvAz6qmEeJlb2vOczKnlNTgamFTwgGb7F7S1Q NXFgnt6gqjnqUQIEGBl9JNfItWn6SsQ764DnScwyRKCHTwI7JYBR9WMAE0sNrjVlDG ZyXEcu+Eq4sfs2q6AVNbkVxKYfrLVnHv+DBjvTtMplunZFWy1X4mUDHwvA/+pjM0Wf mx6AhZ085IKPnUiPFw5uNF9S0Wbom3zVSBho6QCjHZi0qyOHCCJHmVUyuKuCOnnWCf wLrYDLo9W6iyppN3EC2jVZoJ3593A355pyWZgvbcYxzxYjaJhzeDxuGeUWz6vGLhhj wtwEDZiq6WyKg== Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP aconnect bus driver is using pm_clk_*() for managing required clocks. With this, clocks seem to be always ON. This happens because, the clock prepare count is incremented in pm_clock_acquire() which is called during device probe(). The count is decremented during remove(). Hence the prepare_count for the clock is non-zero till the remove() gets executed. This is true for BPMP managed clock sources, where clock enable and disable happens during prepare and unprepare phases respectively. Thus clocks remain ON always and that is why pm_clk_*() cannot be used on Tegra. This patch replaces pm_clk_*() with devm_clk_*() and runtime PM callbacks reflect this. System suspend/resume can use pm_runtime_force_suspend/resume Suggested-by: Mohan Kumar D Reviewed-by: Jonathan Hunter Signed-off-by: Sameer Pujar --- drivers/bus/tegra-aconnect.c | 66 ++++++++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 20 deletions(-) diff --git a/drivers/bus/tegra-aconnect.c b/drivers/bus/tegra-aconnect.c index 084ae28..ac58142 100644 --- a/drivers/bus/tegra-aconnect.c +++ b/drivers/bus/tegra-aconnect.c @@ -12,28 +12,38 @@ #include #include #include -#include #include +struct tegra_aconnect { + struct clk *ape_clk; + struct clk *apb2ape_clk; +}; + static int tegra_aconnect_probe(struct platform_device *pdev) { - int ret; + struct tegra_aconnect *aconnect; if (!pdev->dev.of_node) return -EINVAL; - ret = pm_clk_create(&pdev->dev); - if (ret) - return ret; + aconnect = devm_kzalloc(&pdev->dev, sizeof(struct tegra_aconnect), + GFP_KERNEL); + if (!aconnect) + return -ENOMEM; - ret = of_pm_clk_add_clk(&pdev->dev, "ape"); - if (ret) - goto clk_destroy; + aconnect->ape_clk = devm_clk_get(&pdev->dev, "ape"); + if (IS_ERR(aconnect->ape_clk)) { + dev_err(&pdev->dev, "Can't retrieve ape clock\n"); + return PTR_ERR(aconnect->ape_clk); + } - ret = of_pm_clk_add_clk(&pdev->dev, "apb2ape"); - if (ret) - goto clk_destroy; + aconnect->apb2ape_clk = devm_clk_get(&pdev->dev, "apb2ape"); + if (IS_ERR(aconnect->apb2ape_clk)) { + dev_err(&pdev->dev, "Can't retrieve apb2ape clock\n"); + return PTR_ERR(aconnect->apb2ape_clk); + } + dev_set_drvdata(&pdev->dev, aconnect); pm_runtime_enable(&pdev->dev); of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); @@ -41,35 +51,51 @@ static int tegra_aconnect_probe(struct platform_device *pdev) dev_info(&pdev->dev, "Tegra ACONNECT bus registered\n"); return 0; - -clk_destroy: - pm_clk_destroy(&pdev->dev); - - return ret; } static int tegra_aconnect_remove(struct platform_device *pdev) { pm_runtime_disable(&pdev->dev); - pm_clk_destroy(&pdev->dev); - return 0; } static int tegra_aconnect_runtime_resume(struct device *dev) { - return pm_clk_resume(dev); + struct tegra_aconnect *aconnect = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(aconnect->ape_clk); + if (ret) { + dev_err(dev, "ape clk_enable failed: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(aconnect->apb2ape_clk); + if (ret) { + clk_disable_unprepare(aconnect->ape_clk); + dev_err(dev, "apb2ape clk_enable failed: %d\n", ret); + return ret; + } + + return 0; } static int tegra_aconnect_runtime_suspend(struct device *dev) { - return pm_clk_suspend(dev); + struct tegra_aconnect *aconnect = dev_get_drvdata(dev); + + clk_disable_unprepare(aconnect->ape_clk); + clk_disable_unprepare(aconnect->apb2ape_clk); + + return 0; } static const struct dev_pm_ops tegra_aconnect_pm_ops = { SET_RUNTIME_PM_OPS(tegra_aconnect_runtime_suspend, tegra_aconnect_runtime_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) }; static const struct of_device_id tegra_aconnect_of_match[] = { From patchwork Wed Mar 6 10:41:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 10840845 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 35FF8922 for ; Wed, 6 Mar 2019 10:41:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2131A2D096 for ; Wed, 6 Mar 2019 10:41:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 15CF42D4ED; Wed, 6 Mar 2019 10:41:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0EEA92D1FE for ; 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Wed, 6 Mar 2019 10:41:32 +0000 Received: from linux.nvidia.com (Not Verified[10.24.34.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 06 Mar 2019 02:41:32 -0800 From: Sameer Pujar To: , , , , CC: , , , , , , , Sameer Pujar Subject: [PATCH 2/3] dmaengine: tegra210-adma: use devm_clk_*() helpers Date: Wed, 6 Mar 2019 16:11:17 +0530 Message-ID: <1551868878-1131-2-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551868878-1131-1-git-send-email-spujar@nvidia.com> References: <1551868878-1131-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551868893; bh=zd+T0jSSPTNtSGYxDwl/VtyPt5PqZbL4yl5jQ2tur9U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=PUVbjOZav1l6/MPfZtcwX3ngizp+cxULeQ/acMCUTDAfPkWlmO1k9wX/gMDAwG0nj 1KoA6n+Vse5pl03zJYSs1sRl4Yg8dvfJQTtA92XOEiY2K9uqgaqqCMERKWpl0Ci5cL vs0Xv2m092xyC1eQJEhZcWj3iPYX3ZX9VII3NC27+4igi8ZzUhBdejKaplqXp2o534 CexUYiIEyjmG6N/C4nAQ1Q8moSBzE74B3aknAkLxvLJs9H+tQgj8wNWHfJR21IOsql nBbb9SBasWXU5G8y6cDHddTk4hEFbEDaL1DzeWiaEJYl23r0eDN69V7aBaOWKN9M8z 4IKCYuuitGbgA== Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Usage of pm_clk_*() results in non-zero prepare_count for clocks and hence module clocks remain ON always. This is not desired as it will leak power unncessarily. This patch replaces pm_clk_*() with devm_clk_*() interface. This helps to keep refcounts balanced when device is not in use and runtime PM callbacks help to enable or disable clocks. System suspend/resume calls can use pm_runtime_force_suspend/resume. Suggested-by: Mohan Kumar D Reviewed-by: Jonathan Hunter Signed-off-by: Sameer Pujar --- drivers/dma/tegra210-adma.c | 37 ++++++++++++++----------------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index b26256f..123fc6d 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include @@ -141,6 +140,7 @@ struct tegra_adma { struct dma_device dma_dev; struct device *dev; void __iomem *base_addr; + struct clk *ahub_clk; unsigned int nr_channels; unsigned long rx_requests_reserved; unsigned long tx_requests_reserved; @@ -637,8 +637,9 @@ static int tegra_adma_runtime_suspend(struct device *dev) struct tegra_adma *tdma = dev_get_drvdata(dev); tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); + clk_disable_unprepare(tdma->ahub_clk); - return pm_clk_suspend(dev); + return 0; } static int tegra_adma_runtime_resume(struct device *dev) @@ -646,10 +647,11 @@ static int tegra_adma_runtime_resume(struct device *dev) struct tegra_adma *tdma = dev_get_drvdata(dev); int ret; - ret = pm_clk_resume(dev); - if (ret) + ret = clk_prepare_enable(tdma->ahub_clk); + if (ret) { + dev_err(dev, "ahub clk_enable failed: %d\n", ret); return ret; - + } tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); return 0; @@ -692,13 +694,11 @@ static int tegra_adma_probe(struct platform_device *pdev) if (IS_ERR(tdma->base_addr)) return PTR_ERR(tdma->base_addr); - ret = pm_clk_create(&pdev->dev); - if (ret) - return ret; - - ret = of_pm_clk_add_clk(&pdev->dev, "d_audio"); - if (ret) - goto clk_destroy; + tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); + if (IS_ERR(tdma->ahub_clk)) { + dev_err(&pdev->dev, "Error: Missing ahub controller clock\n"); + return PTR_ERR(tdma->ahub_clk); + } pm_runtime_enable(&pdev->dev); @@ -775,8 +775,6 @@ static int tegra_adma_probe(struct platform_device *pdev) pm_runtime_put_sync(&pdev->dev); rpm_disable: pm_runtime_disable(&pdev->dev); -clk_destroy: - pm_clk_destroy(&pdev->dev); return ret; } @@ -793,22 +791,15 @@ static int tegra_adma_remove(struct platform_device *pdev) pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); - pm_clk_destroy(&pdev->dev); return 0; } -#ifdef CONFIG_PM_SLEEP -static int tegra_adma_pm_suspend(struct device *dev) -{ - return pm_runtime_suspended(dev) == false; -} -#endif - static const struct dev_pm_ops tegra_adma_dev_pm_ops = { SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend, tegra_adma_runtime_resume, NULL) - SET_SYSTEM_SLEEP_PM_OPS(tegra_adma_pm_suspend, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) }; static struct platform_driver tegra_admac_driver = { From patchwork Wed Mar 6 10:41:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 10840843 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0AF271575 for ; Wed, 6 Mar 2019 10:41:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB5C42D096 for ; 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Wed, 06 Mar 2019 02:41:31 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 06 Mar 2019 02:41:39 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 06 Mar 2019 02:41:39 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 6 Mar 2019 10:41:38 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 6 Mar 2019 10:41:39 +0000 Received: from linux.nvidia.com (Not Verified[10.24.34.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 06 Mar 2019 02:41:38 -0800 From: Sameer Pujar To: , , , , CC: , , , , , , , Sameer Pujar Subject: [PATCH 3/3] irqchip/gic-pm: use devm_clk_*() helpers Date: Wed, 6 Mar 2019 16:11:18 +0530 Message-ID: <1551868878-1131-3-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551868878-1131-1-git-send-email-spujar@nvidia.com> References: <1551868878-1131-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551868891; bh=Qp/M0Ct3Oo0YiRVr0xnM8LvxXwBgpIbzfj5yKAhzP2o=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=onknNf+/beK5k7tlEnJbTJC0cfUCP5UBcEAw9ErBdS784aDTMpSVaesuaO91fBjNW 6TFAxVrqr6DJj/Vdq6rdZPaEtxVwZLEaiNUzUEZdJIKj0q46YZSxLeCla86/UTjuts 4eMDeQJLvo7tqRjURolEa0I/atgeIYgXgoJ0uZFZYHjpoTnBoMrwe8WDsfN+NcgcC4 khr4Q+P3Yn+Odi54cFPpj5yoOrPC1FMWQLpXRHUIfeEh7YJYEqrRWUzcGaXpdQDW3H 9cvxsx74uhMALhRaEN5EU1BTwOy0JzjgutFMHMw8rhbFRdO6jkHCksQjjjonusLu6k 0+o0ZHuReVmaw== Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With pm_clk_*() usage, it is seen that clocks always remain ON. This happens because clocks are managed by BPMP on Tegra devices and clock enable/disable happens during prepare/unprepare phase. This patch avoids use of pm_clk_*() and replaces it with devm_clk_*() helpers. Suggested-by: Mohan Kumar D Reviewed-by: Jonathan Hunter Signed-off-by: Sameer Pujar --- drivers/irqchip/irq-gic-pm.c | 69 +++++++++++++++++++++++++++++--------------- 1 file changed, 46 insertions(+), 23 deletions(-) diff --git a/drivers/irqchip/irq-gic-pm.c b/drivers/irqchip/irq-gic-pm.c index ecafd29..1690939 100644 --- a/drivers/irqchip/irq-gic-pm.c +++ b/drivers/irqchip/irq-gic-pm.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -28,14 +27,29 @@ struct gic_clk_data { const char *const *clocks; }; +struct gic_chip_pm { + struct gic_chip_data *chip_data; + const struct gic_clk_data *clk_data; + struct clk **clk_handle; +}; + static int gic_runtime_resume(struct device *dev) { - struct gic_chip_data *gic = dev_get_drvdata(dev); - int ret; + struct gic_chip_pm *chip_pm = dev_get_drvdata(dev); + struct gic_chip_data *gic = chip_pm->chip_data; + const struct gic_clk_data *data = chip_pm->clk_data; + int ret, i; - ret = pm_clk_resume(dev); - if (ret) - return ret; + for (i = 0; i < data->num_clocks; i++) { + ret = clk_prepare_enable(chip_pm->clk_handle[i]); + if (ret) { + while (--i >= 0) + clk_disable_unprepare(chip_pm->clk_handle[i]); + + dev_err(dev, " clk_enable failed: %d\n", ret); + return ret; + } + } /* * On the very first resume, the pointer to the driver data @@ -54,33 +68,39 @@ static int gic_runtime_resume(struct device *dev) static int gic_runtime_suspend(struct device *dev) { - struct gic_chip_data *gic = dev_get_drvdata(dev); + struct gic_chip_pm *chip_pm = dev_get_drvdata(dev); + struct gic_chip_data *gic = chip_pm->chip_data; + const struct gic_clk_data *data = chip_pm->clk_data; + int i; gic_dist_save(gic); gic_cpu_save(gic); - return pm_clk_suspend(dev); + for (i = 0; i < data->num_clocks; i++) + clk_disable_unprepare(chip_pm->clk_handle[i]); + + return 0; } -static int gic_get_clocks(struct device *dev, const struct gic_clk_data *data) +static int gic_get_clocks(struct device *dev, struct gic_chip_pm *chip_pm) { unsigned int i; - int ret; + const struct gic_clk_data *data = chip_pm->clk_data; if (!dev || !data) return -EINVAL; - ret = pm_clk_create(dev); - if (ret) - return ret; + chip_pm->clk_handle = devm_kzalloc(dev, data->num_clocks * + sizeof(struct clk *), GFP_KERNEL); + if (!chip_pm->clk_handle) + return -ENOMEM; for (i = 0; i < data->num_clocks; i++) { - ret = of_pm_clk_add_clk(dev, data->clocks[i]); - if (ret) { + chip_pm->clk_handle[i] = devm_clk_get(dev, data->clocks[i]); + if (IS_ERR(chip_pm->clk_handle[i])) { dev_err(dev, "failed to add clock %s\n", data->clocks[i]); - pm_clk_destroy(dev); - return ret; + return PTR_ERR(chip_pm->clk_handle[i]); } } @@ -91,14 +111,20 @@ static int gic_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct gic_clk_data *data; - struct gic_chip_data *gic; + struct gic_chip_pm *gic_chip_pm; int ret, irq; + gic_chip_pm = devm_kzalloc(dev, sizeof(*gic_chip_pm), GFP_KERNEL); + if (!gic_chip_pm) + return -ENOMEM; + data = of_device_get_match_data(&pdev->dev); if (!data) { dev_err(&pdev->dev, "no device match found\n"); return -ENODEV; } + gic_chip_pm->clk_data = data; + platform_set_drvdata(pdev, gic_chip_pm); irq = irq_of_parse_and_map(dev->of_node, 0); if (!irq) { @@ -106,7 +132,7 @@ static int gic_probe(struct platform_device *pdev) return -EINVAL; } - ret = gic_get_clocks(dev, data); + ret = gic_get_clocks(dev, gic_chip_pm); if (ret) goto irq_dispose; @@ -116,12 +142,10 @@ static int gic_probe(struct platform_device *pdev) if (ret < 0) goto rpm_disable; - ret = gic_of_init_child(dev, &gic, irq); + ret = gic_of_init_child(dev, &gic_chip_pm->chip_data, irq); if (ret) goto rpm_put; - platform_set_drvdata(pdev, gic); - pm_runtime_put(dev); dev_info(dev, "GIC IRQ controller registered\n"); @@ -132,7 +156,6 @@ static int gic_probe(struct platform_device *pdev) pm_runtime_put_sync(dev); rpm_disable: pm_runtime_disable(dev); - pm_clk_destroy(dev); irq_dispose: irq_dispose_mapping(irq);