From patchwork Fri Aug 23 04:25:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13774583 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F11D2481DA; Fri, 23 Aug 2024 04:25:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387156; cv=none; b=gsW1R7j1BDSiHpxu+16t26VncEHNp83tMv6E2ENsOlSzTV5smLcwbGnJjVh6F9nDLOKp1Fw3/J1yOiCDB2wWxM++38sS28xXkNPnhhavPeJRp9GMtkcP8WaDPXKnwb2iJxFP9l9EEMkQrafDknxCg+F9TkTrGASezwM9xMWugTU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387156; c=relaxed/simple; bh=0sL7dvmOd/DrdQHOQnY94UEhfSdGHNz/sBxQOe72fXs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=H4eyIlsZ+Y0z2O/1qHsFz90gmru/SGuembbWUIUCYXIDledWuDkWOlVhcmt7wcinHNDaRWLwqu/p+85KiD6dVP3wy0pplZz3K8rYZ0lFRifcoRgjR4t4TQBu0dmDEfjni/LrCiwUZCaOdT/TgcOgEV+5ExwqlCRxyVVrLroJj/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GoUosSTE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GoUosSTE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 711BFC4AF0E; Fri, 23 Aug 2024 04:25:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724387155; bh=0sL7dvmOd/DrdQHOQnY94UEhfSdGHNz/sBxQOe72fXs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GoUosSTEucLe0YwexNf7dYI5VfZWZVBwBybYoHM+RnWuYFuTeFW/qolExBRb4SXAk XtNVEIgYCgY8ToZhpwohHOm9d/Ij77oNC2F4uYJRNPFd0QLRmVwev9BxQ6cPsHI5po 7DbPNYkS4ZiChM9F2z77A6eHFeiVcm2QBtMK4eFpIcgmhFbvOfP1g1t3Hul/B4hTqG shY0YU8BhSyUzZBW3k8WRZizo/UEZv6n/yuKcwFhxnoNjDVvlJU+RNek9GBWzm86lE SBdahko9DAVNSXLHmgmct8RjbooXNOq+I7FUCPgn+bnWXQGRmxR1KOTuQj7Uflt6Xq kssxoA0fcmaIw== From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?utf-8?q?Ilpo_J=C3=A4rvin?= =?utf-8?q?en?= , Mario Limonciello Subject: [PATCH v4 1/5] PCI: Use an enum for reset type in pci_dev_wait() Date: Thu, 22 Aug 2024 23:25:03 -0500 Message-ID: <20240823042508.1057791-2-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823042508.1057791-1-superm1@kernel.org> References: <20240823042508.1057791-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello A string is passed to all callers of pci_dev_wait() which is utilized to demonstrate what kind of reset happened when there was a problem. This doesn't allow making the behavior for different reset types conditional though. Lay some plumbing to allow making comparisons of reset types with integers instead. No functional changes. Suggested-by: Ilpo Järvinen Signed-off-by: Mario Limonciello Reviewed-by: Ilpo Järvinen --- v3->v4: * Use index-based array initialization format for pci_reset_types * Fix LKP reported sparse issue --- drivers/pci/pci-driver.c | 2 +- drivers/pci/pci.c | 29 +++++++++++++++++++---------- drivers/pci/pci.h | 11 ++++++++++- drivers/pci/pcie/dpc.c | 2 +- 4 files changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index f412ef73a6e4b..ac3cfbfa137d9 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -572,7 +572,7 @@ static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev) { int ret; - ret = pci_bridge_wait_for_secondary_bus(pci_dev, "resume"); + ret = pci_bridge_wait_for_secondary_bus(pci_dev, PCI_DEV_WAIT_RESUME); if (ret) { /* * The downstream link failed to come up, so mark the diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ffaaca0978cbc..e4a7f5dfe6bf4 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -181,6 +181,15 @@ static int __init pcie_port_pm_setup(char *str) } __setup("pcie_port_pm=", pcie_port_pm_setup); +static const char * const pci_reset_types[] = { + [PCI_DEV_WAIT_FLR] = "FLR", + [PCI_DEV_WAIT_AF_FLR] = "AF_FLR", + [PCI_DEV_WAIT_D3HOT_D0] = "PM D3HOT->D0", + [PCI_DEV_WAIT_BUS_RESET] = "bus reset", + [PCI_DEV_WAIT_RESUME] = "resume", + [PCI_DEV_WAIT_DPC] = "DPC", +}; + /** * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children * @bus: pointer to PCI bus structure to search @@ -1279,7 +1288,7 @@ void pci_resume_bus(struct pci_bus *bus) pci_walk_bus(bus, pci_resume_one, NULL); } -static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) +static int pci_dev_wait(struct pci_dev *dev, enum pci_reset_type reset_type, int timeout) { int delay = 1; bool retrain = false; @@ -1317,7 +1326,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) if (delay > timeout) { pci_warn(dev, "not ready %dms after %s; giving up\n", - delay - 1, reset_type); + delay - 1, pci_reset_types[reset_type]); return -ENOTTY; } @@ -1330,7 +1339,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) } } pci_info(dev, "not ready %dms after %s; waiting\n", - delay - 1, reset_type); + delay - 1, pci_reset_types[reset_type]); } msleep(delay); @@ -1339,10 +1348,10 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) if (delay > PCI_RESET_WAIT) pci_info(dev, "ready %dms after %s\n", delay - 1, - reset_type); + pci_reset_types[reset_type]); else pci_dbg(dev, "ready %dms after %s\n", delay - 1, - reset_type); + pci_reset_types[reset_type]); return 0; } @@ -4536,7 +4545,7 @@ int pcie_flr(struct pci_dev *dev) */ msleep(100); - return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + return pci_dev_wait(dev, PCI_DEV_WAIT_FLR, PCIE_RESET_READY_POLL_MS); } EXPORT_SYMBOL_GPL(pcie_flr); @@ -4603,7 +4612,7 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) */ msleep(100); - return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + return pci_dev_wait(dev, PCI_DEV_WAIT_AF_FLR, PCIE_RESET_READY_POLL_MS); } /** @@ -4648,7 +4657,7 @@ static int pci_pm_reset(struct pci_dev *dev, bool probe) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); - return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + return pci_dev_wait(dev, PCI_DEV_WAIT_D3HOT_D0, PCIE_RESET_READY_POLL_MS); } /** @@ -4822,7 +4831,7 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) * Return 0 on success or -ENOTTY if the first device on the secondary bus * failed to become accessible. */ -int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type) +int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, enum pci_reset_type reset_type) { struct pci_dev *child __free(pci_dev_put) = NULL; int delay; @@ -4959,7 +4968,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev) __builtin_return_address(0)); pcibios_reset_secondary_bus(dev); - return pci_bridge_wait_for_secondary_bus(dev, "bus reset"); + return pci_bridge_wait_for_secondary_bus(dev, PCI_DEV_WAIT_BUS_RESET); } EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 79c8398f39384..477257e843952 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -4,6 +4,15 @@ #include +enum pci_reset_type { + PCI_DEV_WAIT_FLR, + PCI_DEV_WAIT_AF_FLR, + PCI_DEV_WAIT_D3HOT_D0, + PCI_DEV_WAIT_BUS_RESET, + PCI_DEV_WAIT_RESUME, + PCI_DEV_WAIT_DPC, +}; + /* Number of possible devfns: 0.0 to 1f.7 inclusive */ #define MAX_NR_DEVFNS 256 @@ -137,7 +146,7 @@ void pci_msi_init(struct pci_dev *dev); void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); -int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); +int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, enum pci_reset_type reset_type); static inline void pci_wakeup_event(struct pci_dev *dev) { diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c index 2b6ef7efa3c11..95cd985244729 100644 --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c @@ -174,7 +174,7 @@ pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, PCI_EXP_DPC_STATUS_TRIGGER); - if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) { + if (pci_bridge_wait_for_secondary_bus(pdev, PCI_DEV_WAIT_DPC)) { clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); ret = PCI_ERS_RESULT_DISCONNECT; } else { From patchwork Fri Aug 23 04:25:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13774585 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 475827345B; Fri, 23 Aug 2024 04:25:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387158; cv=none; b=JJ8pk0njYPPVkqpPrhfRqd8jva9KnfI0GqeHCtQKy5sL1dp5Ab5PmFaK0p1PQ93i3K9wT1XwdsSpGW4FdA29j5+aEoqAhOweX2kBeu5FGHDGpaSroZY29beVCzyVj6zeOjnfqlc3r3Zg7ohd3f2INY5AEWDHs7sQ5C8suMlmWnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387158; c=relaxed/simple; bh=khgcZTdcadskw9ICjrzaNIg7PTgVIwoH2HRI4HWP9KA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=egnnglIAYb9P6Mzskge2/ATqVQPhRedodzH1NA49uyDgyYz1V5prGabm6Mkx1DaqZ4jWh5eM/RMoqaPkqr4LDbFDN3gIJXOAZcQmGVhihvoTLguwpGeBeyP3S5vCNmN5x2DQeQl4pLB4H7G7d1HBzZHdNC8WeaAQJnIdIbABRHU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n2ucnUs7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n2ucnUs7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1C074C32786; Fri, 23 Aug 2024 04:25:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724387158; bh=khgcZTdcadskw9ICjrzaNIg7PTgVIwoH2HRI4HWP9KA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n2ucnUs7aUD0SBaMn+cJjeszHD1Ml9yZoXuy2mgg14dfcbJEB/EO7ytzXZJ3Ko9qS Z2NlkAGES1aYrqApD+XrIV0JvZGM5vvPL1as0CEA6ZEzZ93leKUIldgBef519e9Duu 5WVgNIxviQfdRyIHqll3+/kP3JRHLEgj0uVBVgHRYK7D4V8n38flDye07XDlR9ym3k 07GA8mp1/C/cWyMnfESC7GPV4b/IiKt8oqQYHFydtwBmERRpTwvKAN1J2e9yIvmDvw rSK2t2Bvfq4Rn+EoDgVVPgQLMRahr4rjubg+ifU8QM1CpizbbpPuO51Y/gHsHX0bJH w6SKd89FhCrvA== From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?utf-8?q?Ilpo_J=C3=A4rvin?= =?utf-8?q?en?= , Mario Limonciello Subject: [PATCH v4 2/5] PCI: Check PCI_PM_CTRL instead of PCI_COMMAND in pci_dev_wait() Date: Thu, 22 Aug 2024 23:25:05 -0500 Message-ID: <20240823042508.1057791-4-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823042508.1057791-1-superm1@kernel.org> References: <20240823042508.1057791-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello A device that has gone through a reset may return a value in PCI_COMMAND but that doesn't mean it's finished transitioning to D0. On devices that support power management explicitly check PCI_PM_CTRL on everything but system resume to ensure the transition happened. Devices that don't support power management and system resume will continue to use PCI_COMMAND. Signed-off-by: Mario Limonciello --- drivers/pci/pci.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e4a7f5dfe6bf4..b7717155e2fd0 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1308,21 +1308,33 @@ static int pci_dev_wait(struct pci_dev *dev, enum pci_reset_type reset_type, int * the read (except when CRS SV is enabled and the read was for the * Vendor ID; in that case it synthesizes 0x0001 data). * - * Wait for the device to return a non-CRS completion. Read the - * Command register instead of Vendor ID so we don't have to - * contend with the CRS SV value. + * Wait for the device to return a non-CRS completion. On devices + * that support PM control and on waits that aren't part of system + * resume read the PM control register to ensure the device has + * transitioned to D0. On devices that don't support PM control, + * or during system resume read the command register to instead of + * Vendor ID so we don't have to contend with the CRS SV value. */ for (;;) { - u32 id; - if (pci_dev_is_disconnected(dev)) { pci_dbg(dev, "disconnected; not waiting\n"); return -ENOTTY; } - pci_read_config_dword(dev, PCI_COMMAND, &id); - if (!PCI_POSSIBLE_ERROR(id)) - break; + if (dev->pm_cap && reset_type != PCI_DEV_WAIT_RESUME) { + u16 pmcsr; + + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); + if (!PCI_POSSIBLE_ERROR(pmcsr) && + (pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D0) + break; + } else { + u32 id; + + pci_read_config_dword(dev, PCI_COMMAND, &id); + if (!PCI_POSSIBLE_ERROR(id)) + break; + } if (delay > timeout) { pci_warn(dev, "not ready %dms after %s; giving up\n", From patchwork Fri Aug 23 04:25:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13774586 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B1C4136658; Fri, 23 Aug 2024 04:25:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387159; cv=none; b=Y3Gt3mz2J3aETu8BweIzlnP7xtdvVBFMiT4SsIXI5yJ/KmzDqCovUbJNMLPiK9BusBv6w9u6jvY0BrzJu2WMlhqM5qgnyN6pjAPblikccMgXDL5+mipvb8aZ3JYvrJPBxbPwyJ5/FmaL9BUke0nifLpVAr6Q7AIpAgHyqw6UGdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387159; c=relaxed/simple; bh=6qJIy4WqqsO1C50A53jNHauk0l6sBv1X7ojJgbZaFU0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JOoK8p6AuLVqk4ld5jtOJQkRzsb7I8TbKqpyufuCQgAL9xN4u8sPvc8WYRJkVtbWwhl/NwUQqx1hJAemEEBYgZvNOWCwulhkZuc25xTvN1c38DVVs01/IlkBxsPGmUj6UtOZsfyLZ0GsYJaKwWd8PAMFqXbrUJslwDcZxU88HfU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E6sGQS6z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E6sGQS6z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6408AC4AF0E; Fri, 23 Aug 2024 04:25:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724387159; bh=6qJIy4WqqsO1C50A53jNHauk0l6sBv1X7ojJgbZaFU0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E6sGQS6zBe18pLlWufIsgJbEP2N5vMWLF3VJ04Sl96qIlYuI9rD1TJFghHmV31pvL RywmJBGjwhMlzUCGo897dV+mXk93DsxBOfe1j4CVTeqLVcpXjvHowvoDNOUf9pj8zi b6M9xvMCse/Seif5E93kJntUXH7x9iWbvzxo28HcbR7LIA4gDHz/ARzaGIZW+OtHQB fLEfh10QVA66XfCNZ47vL9hlX6G1Y/99+ypzGWRCInmBFAvsWhdNhGAgzd/g/MNxw8 MER0i9pyCG8HJx2g5PFH5BknbaptQpRjtO1rJTeZwclsZ4dPVG3nIRl7ptY+jLoH3U xCyxL5FJtk5rg== From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?utf-8?q?Ilpo_J=C3=A4rvin?= =?utf-8?q?en?= , Mario Limonciello Subject: [PATCH v4 3/5] PCI: Verify functions currently in D3cold have entered D0 Date: Thu, 22 Aug 2024 23:25:06 -0500 Message-ID: <20240823042508.1057791-5-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823042508.1057791-1-superm1@kernel.org> References: <20240823042508.1057791-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello It is reported that USB4 routers and downstream devices may behave incorrectly if a dock cable is plugged in at approximately the time that the autosuspend_delay is configured. In this situation the device has attempted to enter D3cold, but didn't finish D3cold entry when the PCI core tried to transition it back to D0. Empirically measuring this situation an "aborted" D3cold exit takes ~60ms and a "normal" D3cold exit takes ~6ms. The PCI-PM 1.2 spec specifies that the restore time for functions in D3cold is either 'Full context restore or boot latency'. As PCIe r6.0 sec 5.8 specifies that the device will have gone through a conventional reset, it may take some time for the device to be ready. Wait up to 1 sec as specified in PCIe r6.0 sec 6.6.1 for a device in D3cold to return to D0. Reviewed-by: Ilpo Järvinen Signed-off-by: Mario Limonciello --- drivers/pci/pci.c | 11 +++++++++++ drivers/pci/pci.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b7717155e2fd0..7e861b6923d0a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1425,6 +1425,17 @@ int pci_power_up(struct pci_dev *dev) else if (state == PCI_D2) udelay(PCI_PM_D2_DELAY); + /* + * D3cold -> D0 will have gone through a conventional reset and may need + * time to be ready. + */ + if (dev->current_state == PCI_D3cold) { + int ret; + + ret = pci_dev_wait(dev, PCI_DEV_WAIT_D3COLD_D0, PCI_RESET_WAIT); + if (ret) + return ret; + } end: dev->current_state = PCI_D0; if (need_restore) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 477257e843952..a675f5d55f298 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -11,6 +11,7 @@ enum pci_reset_type { PCI_DEV_WAIT_BUS_RESET, PCI_DEV_WAIT_RESUME, PCI_DEV_WAIT_DPC, + PCI_DEV_WAIT_D3COLD_D0, }; /* Number of possible devfns: 0.0 to 1f.7 inclusive */ From patchwork Fri Aug 23 04:25:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13774587 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30D9013AA2A; Fri, 23 Aug 2024 04:26:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387161; cv=none; b=EcKlougeCqacojgj4GU5gbzIxmtS4BMO1ZOJxb6Xuh6wVBPOMVOAF7FpOEnm6jH8qx062w0dGpab8fVBN/5qkgp317ioGejQOfdPy74OLbSFt+/wYUuW6YYxknxNVCTM77Wdq9Bo1xlY8y86DAreA6MQEQoIqJersL2pfO4kg0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387161; c=relaxed/simple; bh=JWSRlz8uRX9VxLn24AvyMy0LwzF2iYqEImctSnL1LEw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rJT/9kpBvqxYXMPlhSFLR1BGZR/sHNC8zHlu+g9/lwa6w089TQsGoGoNbzzteKrBjOfpr1vab2FeKU7jExh/cYY9x5dL/vAenri13XAlipuZW/Md7dspcWMPW0i4+XQxmPxSC63bg2AxIZqFzKJBWCzuerZDeSa8Ajgn534N+gI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RjRJO7c7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RjRJO7c7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AE819C4DDEE; Fri, 23 Aug 2024 04:25:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724387160; bh=JWSRlz8uRX9VxLn24AvyMy0LwzF2iYqEImctSnL1LEw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RjRJO7c76lM86qsTNCrtqG8/jdXa2IHrSc4V/YTA5BsumkSszZ4hu6cWVAd5Fe1N3 z1Qe3A49AzC0ep5BYiuSfINfLktqfXARIVGFNfMduP6e7S264msH6F5FpKw48mZ27h A8Hjln0IrFyzc0NPZe96JkGAti3qU/VFaO5D0bDuRUhrT3TdrpOm2zS4H7ll9II4Xt boDTHLbJzI4Lhh9GJOKYGR14++oaRUFG4DL/OWlfD2c66YO8TpKrqyiMtEphHFm8W1 XeLqJKL5uGDvhf0JZRX5vdKMrpHBoFZ4kKArdcuBBS1ji2MaerQ1QaOu9+2LWdbaCZ oQbmJ7bRNUaqA== From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?utf-8?q?Ilpo_J=C3=A4rvin?= =?utf-8?q?en?= , Mario Limonciello Subject: [PATCH v4 4/5] PCI: Allow Ryzen XHCI controllers into D3cold and drop delays Date: Thu, 22 Aug 2024 23:25:07 -0500 Message-ID: <20240823042508.1057791-6-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823042508.1057791-1-superm1@kernel.org> References: <20240823042508.1057791-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello As the PCI core now has a delay after D3cold exit, the Ryzen XHCI controllers that were quirked to not use D3cold and to add a delay on D3hot no longer need these quirks. Drop both the PCI and XHCI sets of quirks. Signed-off-by: Mario Limonciello Acked-by: Greg Kroah-Hartman --- drivers/pci/quirks.c | 17 ----------------- drivers/usb/host/xhci-pci.c | 11 ----------- 2 files changed, 28 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index a2ce4e08edf5a..3480a0445ff50 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2059,23 +2059,6 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_nvidia_hda_pm); -/* - * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. - * https://bugzilla.kernel.org/show_bug.cgi?id=205587 - * - * The kernel attempts to transition these devices to D3cold, but that seems - * to be ineffective on the platforms in question; the PCI device appears to - * remain on in D3hot state. The D3hot-to-D0 transition then requires an - * extended delay in order to succeed. - */ -static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) -{ - quirk_d3hot_delay(dev, 20); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); - #ifdef CONFIG_X86_IO_APIC static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) { diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index dc1e345ab67ea..d726810a04838 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -316,10 +316,6 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) xhci->quirks |= XHCI_U2_DISABLE_WAKE; - if (pdev->vendor == PCI_VENDOR_ID_AMD && - pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) - xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; - if (pdev->vendor == PCI_VENDOR_ID_INTEL) { xhci->quirks |= XHCI_LPM_SUPPORT; xhci->quirks |= XHCI_INTEL_HOST; @@ -752,13 +748,6 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) if (xhci->quirks & XHCI_COMP_MODE_QUIRK) pci_d3cold_disable(pdev); -#ifdef CONFIG_SUSPEND - /* d3cold is broken, but only when s2idle is used */ - if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && - xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) - pci_d3cold_disable(pdev); -#endif - if (xhci->quirks & XHCI_PME_STUCK_QUIRK) xhci_pme_quirk(hcd); From patchwork Fri Aug 23 04:25:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13774588 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8676513C66A; Fri, 23 Aug 2024 04:26:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387162; cv=none; b=QR6u6LcXg2bJTfhT9jKdN6QjkopmjqwvU+izqW3GBmsn6Y8tXHqe8WtCmyUxWzyX3l/+KJxEUDgKdGMcLog4xFP+2mSZ5JL3PWCt5Y5A92yfyePkcjTDr70zO6QQerQs+x4yDTeVaMU/UQEPgCOEHuRiKwKPfvgsu4Hcne8KQH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724387162; c=relaxed/simple; bh=Rzi8UdSIlhz3Lz27Lgf4llrXyRuDGgJEajx2s+fq7bM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hVkgyJbNhJC/Yf4am+LxAAY/1KVecrxpCc+CD2IwM3C1CgvzlInWKTNYXX569RGH/8ldV6y8ajw4AM8EAjp+UGbPe57b08Bd8xByXWrwF92OrgT0IjZ6rIUhFlI28579hGcpNZT7yG8GKzMPsE+C+FRPQNUcu5SIe3i2BVu23nE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uX1Hcz5d; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uX1Hcz5d" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08774C32786; Fri, 23 Aug 2024 04:26:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724387162; bh=Rzi8UdSIlhz3Lz27Lgf4llrXyRuDGgJEajx2s+fq7bM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uX1Hcz5dZVuGVBg+ODao+DPp4pCyuYwuvpA9Tuoa5xHlmEEVneOVXni4DQ5Mc3FY1 fRb6iFq6dKHCput+mUtlG3BoHxfbJBBaaJWfSpUGSZ6LTh+oW/g6BnWik+hoyq491Y lji4oUQhHQRzrBWOyhuGbBE+zJhJRjmFgoDPqi/YtpLGGQXiVEKCL3Dhvho+/ZM1wt TBIryOBvPp55dGnXeu6qm33D1u/sK77f0VUpwIdNJtngG4tmWQzGKR9CKxhNeA5w7x 8zQGL+Sn8vHTJ/c8PPDW2hy8NXOcpKJ+JDJJFo20C+UX16xINyLN5h0XaO4E+0RQaN gOZtD5dVdn8Dg== From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?utf-8?q?Ilpo_J=C3=A4rvin?= =?utf-8?q?en?= , Mario Limonciello Subject: [PATCH v4 5/5] PCI: Drop Radeon quirk for Macbook Pro 8.2 Date: Thu, 22 Aug 2024 23:25:08 -0500 Message-ID: <20240823042508.1057791-7-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823042508.1057791-1-superm1@kernel.org> References: <20240823042508.1057791-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello commit 5938628c51a7 ("drm/radeon: make MacBook Pro d3_delay quirk more generic") introduced a generic quirk for Macbook Pro 8.2s that contain Radeon graphics to ensure that enough time had past when the device was powered on. As the PCI core now verifies the device is in D0 during power on this extra artificial delay is no longer necessary. Signed-off-by: Mario Limonciello --- drivers/pci/quirks.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 3480a0445ff50..e76ff1037fb35 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2038,14 +2038,6 @@ static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) dev->d3hot_delay); } -static void quirk_radeon_pm(struct pci_dev *dev) -{ - if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && - dev->subsystem_device == 0x00e2) - quirk_d3hot_delay(dev, 20); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); - /* * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus * reset is performed too soon after transition to D0, extend d3hot_delay