From patchwork Fri Aug 23 15:40:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13775423 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2299718BC0A; Fri, 23 Aug 2024 15:40:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724427636; cv=none; b=tPmp8LKAsUfRm7sZEyysfcJFXNTJh++pZxHJoKjLnB9zdPgqJDO5Mtev0h9QgEErbE+G1LlAVz2Wa0T/ty8pX0lF53WxpsPobRT0kHgp1cyymTSgOi3rWjVLzilgveTaPzyp270q0F5UfbKhV14bD15VevwF///C9Ka/NjNF0Ac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724427636; c=relaxed/simple; bh=Tf2S1xZWRnKKEhmKPhTMu3cUntZAGi9lxHNWOj+Eg7M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XMlvMta91vTUbzIjUXdAlAYdGOiWeEev5tqrFdmaKEH1Jeq6yyAqeedDYkLNWn9sEsaKs/rbCA8cWjzBHvOppkh3JoYmavWkBsxZaseyXoJD8ugc+oOFuD4L+XTVrPyOTmOos1iPNxTsv7ftoDlgEGvkZU3yfNGQXqIbqepAbrg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jyGkbCpL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jyGkbCpL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A1096C32786; Fri, 23 Aug 2024 15:40:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724427635; bh=Tf2S1xZWRnKKEhmKPhTMu3cUntZAGi9lxHNWOj+Eg7M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jyGkbCpLjSAcgqHp/4ohcmkiyOA1570jvoeBmu0ks1eh9kdzdPEDTZzh5ZkL2pW8l e0aEjegyBVghlQF7Wu9G3sno61tOE9y5njtnzrUasApAkA9gKu4f8IOUfnBVGt4Hny XR+7Ub2VF2O6jvmPWUr3Z/t84U714UbaAOyMipUHORejPFGnTar7R79TzcLu/6t5pp Oy89yC0ZD5UAwYDQn+fEi6e5vDQaNzZohd9AhxwTB1Q442b5pN8BcYjxnXZUVR3RbX pUebBFH4UTU7HCo5YlHdviAHNBlYLN4ygmaKFGZKdoGsHzzb2IaAmzqTcCNDGeSBMw J8l0fKmmbdIUg== From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?utf-8?q?Ilpo_J=C3=A4rvin?= =?utf-8?q?en?= , Mario Limonciello Subject: [PATCH v5 1/5] PCI: Use an enum for reset type in pci_dev_wait() Date: Fri, 23 Aug 2024 10:40:19 -0500 Message-ID: <20240823154023.360234-2-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823154023.360234-1-superm1@kernel.org> References: <20240823154023.360234-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello A string is passed to all callers of pci_dev_wait() which is utilized to demonstrate what kind of reset happened when there was a problem. This doesn't allow making the behavior for different reset types conditional though. Lay some plumbing to allow making comparisons of reset types with integers instead. No functional changes. Suggested-by: Ilpo Järvinen Signed-off-by: Mario Limonciello --- v4->v5: * Add static assert and PCI_DEV_WAIT_MAX v3->v4: * Use index-based array initialization format for pci_reset_types * Fix LKP reported sparse issue --- drivers/pci/pci-driver.c | 2 +- drivers/pci/pci.c | 30 ++++++++++++++++++++---------- drivers/pci/pci.h | 12 +++++++++++- drivers/pci/pcie/dpc.c | 2 +- 4 files changed, 33 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index f412ef73a6e4b..ac3cfbfa137d9 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -572,7 +572,7 @@ static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev) { int ret; - ret = pci_bridge_wait_for_secondary_bus(pci_dev, "resume"); + ret = pci_bridge_wait_for_secondary_bus(pci_dev, PCI_DEV_WAIT_RESUME); if (ret) { /* * The downstream link failed to come up, so mark the diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ffaaca0978cbc..1e219057a5069 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -181,6 +181,16 @@ static int __init pcie_port_pm_setup(char *str) } __setup("pcie_port_pm=", pcie_port_pm_setup); +static const char * const pci_reset_types[] = { + [PCI_DEV_WAIT_FLR] = "FLR", + [PCI_DEV_WAIT_AF_FLR] = "AF_FLR", + [PCI_DEV_WAIT_D3HOT_D0] = "PM D3HOT->D0", + [PCI_DEV_WAIT_BUS_RESET] = "bus reset", + [PCI_DEV_WAIT_RESUME] = "resume", + [PCI_DEV_WAIT_DPC] = "DPC", +}; +static_assert(ARRAY_SIZE(pci_reset_types) == PCI_DEV_WAIT_MAX); + /** * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children * @bus: pointer to PCI bus structure to search @@ -1279,7 +1289,7 @@ void pci_resume_bus(struct pci_bus *bus) pci_walk_bus(bus, pci_resume_one, NULL); } -static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) +static int pci_dev_wait(struct pci_dev *dev, enum pci_reset_type reset_type, int timeout) { int delay = 1; bool retrain = false; @@ -1317,7 +1327,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) if (delay > timeout) { pci_warn(dev, "not ready %dms after %s; giving up\n", - delay - 1, reset_type); + delay - 1, pci_reset_types[reset_type]); return -ENOTTY; } @@ -1330,7 +1340,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) } } pci_info(dev, "not ready %dms after %s; waiting\n", - delay - 1, reset_type); + delay - 1, pci_reset_types[reset_type]); } msleep(delay); @@ -1339,10 +1349,10 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) if (delay > PCI_RESET_WAIT) pci_info(dev, "ready %dms after %s\n", delay - 1, - reset_type); + pci_reset_types[reset_type]); else pci_dbg(dev, "ready %dms after %s\n", delay - 1, - reset_type); + pci_reset_types[reset_type]); return 0; } @@ -4536,7 +4546,7 @@ int pcie_flr(struct pci_dev *dev) */ msleep(100); - return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + return pci_dev_wait(dev, PCI_DEV_WAIT_FLR, PCIE_RESET_READY_POLL_MS); } EXPORT_SYMBOL_GPL(pcie_flr); @@ -4603,7 +4613,7 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) */ msleep(100); - return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + return pci_dev_wait(dev, PCI_DEV_WAIT_AF_FLR, PCIE_RESET_READY_POLL_MS); } /** @@ -4648,7 +4658,7 @@ static int pci_pm_reset(struct pci_dev *dev, bool probe) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); - return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + return pci_dev_wait(dev, PCI_DEV_WAIT_D3HOT_D0, PCIE_RESET_READY_POLL_MS); } /** @@ -4822,7 +4832,7 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) * Return 0 on success or -ENOTTY if the first device on the secondary bus * failed to become accessible. */ -int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type) +int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, enum pci_reset_type reset_type) { struct pci_dev *child __free(pci_dev_put) = NULL; int delay; @@ -4959,7 +4969,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev) __builtin_return_address(0)); pcibios_reset_secondary_bus(dev); - return pci_bridge_wait_for_secondary_bus(dev, "bus reset"); + return pci_bridge_wait_for_secondary_bus(dev, PCI_DEV_WAIT_BUS_RESET); } EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 79c8398f39384..be06c38342c76 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -4,6 +4,16 @@ #include +enum pci_reset_type { + PCI_DEV_WAIT_FLR, + PCI_DEV_WAIT_AF_FLR, + PCI_DEV_WAIT_D3HOT_D0, + PCI_DEV_WAIT_BUS_RESET, + PCI_DEV_WAIT_RESUME, + PCI_DEV_WAIT_DPC, + PCI_DEV_WAIT_MAX, +}; + /* Number of possible devfns: 0.0 to 1f.7 inclusive */ #define MAX_NR_DEVFNS 256 @@ -137,7 +147,7 @@ void pci_msi_init(struct pci_dev *dev); void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); -int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); +int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, enum pci_reset_type reset_type); static inline void pci_wakeup_event(struct pci_dev *dev) { diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c index 2b6ef7efa3c11..95cd985244729 100644 --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c @@ -174,7 +174,7 @@ pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, PCI_EXP_DPC_STATUS_TRIGGER); - if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) { + if (pci_bridge_wait_for_secondary_bus(pdev, PCI_DEV_WAIT_DPC)) { clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); ret = PCI_ERS_RESULT_DISCONNECT; } else { From patchwork Fri Aug 23 15:40:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13775424 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CF4E18C90C; Fri, 23 Aug 2024 15:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724427637; cv=none; b=d3eK3pERbThOlOmzRveMQ+q300zaZSIHmf34NQk/lPQN8mSM2ewuCaLph7SK12UtOh2VHBSY2xYBgl8AVA5Mz7Vlnn1MxL9KKT/1ljAUCrbYAIGyLmVwdd0An7Ge6cLur/LwbgQ8WHOtz8iExtbXZ5slYQvezypl7FlZESTqWLI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724427637; c=relaxed/simple; bh=+H7Ob5CgTXkHeBCxTLSQpzmV08rXUMJJgwpIEqFFOvg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TIQTyOasAWhMSl2vmqk/H1i2Y03edrZNfm+H5SAIEIcn17MO/93MDB41wFvv7J3kWOpvGGR/DWHg3Bx5+EaW9U6Ea+u6EeUEfgaF5wgkN8TNZegdUMuUlbGzrjA2LD86+LfApdVFd8P/hMiNh9i6Zecz2CpjJMqgqK59Gy+4Y/s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GG+jAER6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GG+jAER6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F2BE2C4AF0B; Fri, 23 Aug 2024 15:40:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724427637; bh=+H7Ob5CgTXkHeBCxTLSQpzmV08rXUMJJgwpIEqFFOvg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GG+jAER6ctB5/V6Z2V5KpqNiXc8BAI63lz/sWVKXjjaaKjhoyxuL3QIJJGTP91bxw PvEe4VWzoNPb1M8ggfa3/wCiQIAO3owRWJ6tQxPRSbampjPCVzkM/6PHJ1uWo+efpB uQ6gBZqBzmm0q94MuFl9KdnDo7x8W1E0Tovg6ryrpIOqgRXJEEC73Lv8t3ALBWMXUH /MbKsFj27S/yVHaa3hnQkFYSMVlHOrS8+TvfqxaM1aQAAJ+OlJn3VdjCywIbG/PkKs IHLEwvqBNB9O5GGbr5u2IPYf5iXUmMWM3aNs0yNwY/P3ctGpQsJtvKH5CPlDDzhi+c KSD4Uoub0/mnQ== From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?utf-8?q?Ilpo_J=C3=A4rvin?= =?utf-8?q?en?= , Mario Limonciello Subject: [PATCH v5 2/5] PCI: Check PCI_PM_CTRL instead of PCI_COMMAND in pci_dev_wait() Date: Fri, 23 Aug 2024 10:40:20 -0500 Message-ID: <20240823154023.360234-3-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823154023.360234-1-superm1@kernel.org> References: <20240823154023.360234-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello If a dock is plugged in at the same time as autosuspend delay then this can cause malfunctions in the USB4 stack. This happens because the device is still in D3cold at the time that the PCI core handed control back to the USB4 stack. A device that has gone through a reset may return a value in PCI_COMMAND but that doesn't mean it's finished transitioning to D0. For evices that support power management explicitly check PCI_PM_CTRL on everything but system resume to ensure the transition happened. Devices that don't support power management and system resume will continue to use PCI_COMMAND. Signed-off-by: Mario Limonciello --- v4->v5: * Fix misleading indentation * Amend commit message --- drivers/pci/pci.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1e219057a5069..f032a4aaec268 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1309,21 +1309,33 @@ static int pci_dev_wait(struct pci_dev *dev, enum pci_reset_type reset_type, int * the read (except when CRS SV is enabled and the read was for the * Vendor ID; in that case it synthesizes 0x0001 data). * - * Wait for the device to return a non-CRS completion. Read the - * Command register instead of Vendor ID so we don't have to - * contend with the CRS SV value. + * Wait for the device to return a non-CRS completion. On devices + * that support PM control and on waits that aren't part of system + * resume read the PM control register to ensure the device has + * transitioned to D0. On devices that don't support PM control, + * or during system resume read the command register to instead of + * Vendor ID so we don't have to contend with the CRS SV value. */ for (;;) { - u32 id; - if (pci_dev_is_disconnected(dev)) { pci_dbg(dev, "disconnected; not waiting\n"); return -ENOTTY; } - pci_read_config_dword(dev, PCI_COMMAND, &id); - if (!PCI_POSSIBLE_ERROR(id)) - break; + if (dev->pm_cap && reset_type != PCI_DEV_WAIT_RESUME) { + u16 pmcsr; + + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); + if (!PCI_POSSIBLE_ERROR(pmcsr) && + (pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D0) + break; + } else { + u32 id; + + pci_read_config_dword(dev, PCI_COMMAND, &id); + if (!PCI_POSSIBLE_ERROR(id)) + break; + } if (delay > timeout) { pci_warn(dev, "not ready %dms after %s; giving up\n", From patchwork Fri Aug 23 15:40:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13775425 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 875EC18E02E; Fri, 23 Aug 2024 15:40:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724427638; cv=none; b=YuTXeoLqoF6nlkOc6o3aZ2qRoCOjumRhaeuqJ6HerFzE3AhBlzFt43PvaEBGDxQ/Z6Smex1IETAkey5yYdjEsmOgcHn85gD4QlV+kVsnv01V2kfmzr7yIjfF4OzlgpunhBwPlrVTcuYfYDCFqkemIKHVeLz2nsUrL8YIhMeMvtg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724427638; c=relaxed/simple; bh=YJmRm6eClwNstoqHflRiHBsbT7/PRWVFpj8/WSZOKdo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tO5K/QdRZqkuomrYRsoZhBm2vHvQ3u8oQKkHVhOhDOVceoKGKDRqNYq1PCdy7pkFGmpXT0/g2auOI6C/9fn+Jk93Pr8kj20ryDRQckANSrD60fspHMyNizw1v4n/+7OzXToxiWQGsrVPViublvdtBgtJxgLLJdXSBMmmav4n+1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sE02QXZ6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sE02QXZ6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53538C32786; Fri, 23 Aug 2024 15:40:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724427638; bh=YJmRm6eClwNstoqHflRiHBsbT7/PRWVFpj8/WSZOKdo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sE02QXZ6vCH+ZswKAXP1QFPKq4YIXoEhi9DL5+GGh3/LYf0ck85HwXH9Bb7ANB2hH p8nsEyd+BIeFJ4FwI0lNBInLh1NEXf1/g+pfI3VQYx8CABeGU7QvCxH2RsTZrxhv3B 5pyttE55xwzH1FVUB85kT5PU5SQhH9wOdGq0EjSxmJkFqN9mof3S+CgX3JtHFnsqLW W8y2F+r6V9rjfcyCGo+N3E0IZbs28x2mGAhbGhyvENvuK9Nl6LwF0dZ41g+NFZjcLX mzGuo1xMuW13sMLLTvp6IReUMTYIZ2qgj7m2PQNR3CHtHs7/+fP87k7RQkak7Pg0iM THifJ8CwmOMyA== From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?utf-8?q?Ilpo_J=C3=A4rvin?= =?utf-8?q?en?= , Mario Limonciello Subject: [PATCH v5 3/5] PCI: Verify functions currently in D3cold have entered D0 Date: Fri, 23 Aug 2024 10:40:21 -0500 Message-ID: <20240823154023.360234-4-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823154023.360234-1-superm1@kernel.org> References: <20240823154023.360234-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello It is reported that USB4 routers and downstream devices may behave incorrectly if a dock cable is plugged in at approximately the time that the autosuspend_delay is configured. In this situation the device has attempted to enter D3cold, but didn't finish D3cold entry when the PCI core tried to transition it back to D0. Empirically measuring this situation an "aborted" D3cold exit takes ~60ms and a "normal" D3cold exit takes ~6ms. The PCI-PM 1.2 spec specifies that the restore time for functions in D3cold is either 'Full context restore or boot latency'. As PCIe r6.0 sec 5.8 specifies that the device will have gone through a conventional reset, it may take some time for the device to be ready. Wait up to 1 sec as specified in PCIe r6.0 sec 6.6.1 for a device in D3cold to return to D0. Reviewed-by: Ilpo Järvinen Signed-off-by: Mario Limonciello --- v4->v5: * Add missing string for new pci_reset_type --- drivers/pci/pci.c | 12 ++++++++++++ drivers/pci/pci.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index f032a4aaec268..02d94e0527e6a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -188,6 +188,7 @@ static const char * const pci_reset_types[] = { [PCI_DEV_WAIT_BUS_RESET] = "bus reset", [PCI_DEV_WAIT_RESUME] = "resume", [PCI_DEV_WAIT_DPC] = "DPC", + [PCI_DEV_WAIT_D3COLD_D0] = "D3cold->D0", }; static_assert(ARRAY_SIZE(pci_reset_types) == PCI_DEV_WAIT_MAX); @@ -1426,6 +1427,17 @@ int pci_power_up(struct pci_dev *dev) else if (state == PCI_D2) udelay(PCI_PM_D2_DELAY); + /* + * D3cold -> D0 will have gone through a conventional reset and may need + * time to be ready. + */ + if (dev->current_state == PCI_D3cold) { + int ret; + + ret = pci_dev_wait(dev, PCI_DEV_WAIT_D3COLD_D0, PCI_RESET_WAIT); + if (ret) + return ret; + } end: dev->current_state = PCI_D0; if (need_restore) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index be06c38342c76..6a48419924ea1 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -11,6 +11,7 @@ enum pci_reset_type { PCI_DEV_WAIT_BUS_RESET, PCI_DEV_WAIT_RESUME, PCI_DEV_WAIT_DPC, + PCI_DEV_WAIT_D3COLD_D0, PCI_DEV_WAIT_MAX, }; From patchwork Fri Aug 23 15:40:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13775426 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B2A91922DA; Fri, 23 Aug 2024 15:40:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724427640; cv=none; b=HZmE4GaLqDTdzKfKDBe4Tao2Bz1a8/dYRIgO+7ATNw2C+pyvUNQ4M/1mJnBzn+DbClEUs5CUAbTqzo35/6FPnJXyBilJ3kl/jYr5V8ak8aVxIMApEkqHHmENSfoyE5eqUx2qSke+GG5IrSAVJNIa6NPzJdTRdrjqFx/27DwZHSE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724427640; c=relaxed/simple; bh=JWSRlz8uRX9VxLn24AvyMy0LwzF2iYqEImctSnL1LEw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o1qy4/UnaqUVsbht6hcSAmfC/n0nJ9aA+BHi0oBri/qjFfgFUo/pmuvPUwRO/ITEjZ+eGbgdFSUgGj4Ar79GlGPAkXO1GsMuCicr8KeO5i+sJ8sRPXLoVzhyPoHv1/WyrNyezVvz/VqFydO+lEwfUmpvoiuiqDjQYx5pQr2q6l0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=B7D5BNAk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="B7D5BNAk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7346C4AF09; Fri, 23 Aug 2024 15:40:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724427639; bh=JWSRlz8uRX9VxLn24AvyMy0LwzF2iYqEImctSnL1LEw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B7D5BNAkww4RHwj1geA+tvLT1y0kMHkp6UTmal1kX5VWSAQCRQ21aS63yLPEcGnpB zuI6nVHIvS3IRwPHp2qVtnY9X6z922BcFrLf5EkjJ8EF2xjHCSrLyMB8EXPaMxhb0X PPRhOq8dSotJNLSJmZhbXetvdC+Dg+hli4jMzMzSHGU+68W1WI2hNFCZ8BR8925WAl NMTN6QuvhwC9nR2g8+E/lEZlSuJ03TvleAUbXaiR+9eWO+jx3BUdhUvx5mVywYY1sg tEHadAC7eZUqD5JER8XeWnmDinDtF0s27BQyVySSWuwifxmdblsaCOVJg2tTV+UGuN pYEUwrQloI/yw== From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?utf-8?q?Ilpo_J=C3=A4rvin?= =?utf-8?q?en?= , Mario Limonciello Subject: [PATCH v5 4/5] PCI: Allow Ryzen XHCI controllers into D3cold and drop delays Date: Fri, 23 Aug 2024 10:40:22 -0500 Message-ID: <20240823154023.360234-5-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823154023.360234-1-superm1@kernel.org> References: <20240823154023.360234-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello As the PCI core now has a delay after D3cold exit, the Ryzen XHCI controllers that were quirked to not use D3cold and to add a delay on D3hot no longer need these quirks. Drop both the PCI and XHCI sets of quirks. Signed-off-by: Mario Limonciello --- drivers/pci/quirks.c | 17 ----------------- drivers/usb/host/xhci-pci.c | 11 ----------- 2 files changed, 28 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index a2ce4e08edf5a..3480a0445ff50 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2059,23 +2059,6 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_nvidia_hda_pm); -/* - * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. - * https://bugzilla.kernel.org/show_bug.cgi?id=205587 - * - * The kernel attempts to transition these devices to D3cold, but that seems - * to be ineffective on the platforms in question; the PCI device appears to - * remain on in D3hot state. The D3hot-to-D0 transition then requires an - * extended delay in order to succeed. - */ -static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) -{ - quirk_d3hot_delay(dev, 20); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); - #ifdef CONFIG_X86_IO_APIC static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) { diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index dc1e345ab67ea..d726810a04838 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -316,10 +316,6 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) xhci->quirks |= XHCI_U2_DISABLE_WAKE; - if (pdev->vendor == PCI_VENDOR_ID_AMD && - pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) - xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; - if (pdev->vendor == PCI_VENDOR_ID_INTEL) { xhci->quirks |= XHCI_LPM_SUPPORT; xhci->quirks |= XHCI_INTEL_HOST; @@ -752,13 +748,6 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) if (xhci->quirks & XHCI_COMP_MODE_QUIRK) pci_d3cold_disable(pdev); -#ifdef CONFIG_SUSPEND - /* d3cold is broken, but only when s2idle is used */ - if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && - xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) - pci_d3cold_disable(pdev); -#endif - if (xhci->quirks & XHCI_PME_STUCK_QUIRK) xhci_pme_quirk(hcd); From patchwork Fri Aug 23 15:40:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13775427 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38C3C1925A4; Fri, 23 Aug 2024 15:40:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724427641; cv=none; b=OrEvgYpL9Qu63fj459czKT0Hgbicy88yXnDm5wBhAcY+GqfAh6QHaV2gU1KoB3v31r/7PlR00fjRDsPP+cEaUL5y32hPRWKpvsS2SZNwlURFxMVa6FQwvnngAz2de24T9Q4kSPoP4nSlf7/jENSmt6+G/QhXbDfFjtXSyMBCebQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724427641; c=relaxed/simple; bh=Rzi8UdSIlhz3Lz27Lgf4llrXyRuDGgJEajx2s+fq7bM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XeE3Kr+O5byo4puKtJnIYFuDfI7TeaTGr/pX7g8A3kTmmJ+wPC24RmzJFpYLdScpqJ9wLpMnTCq79pQz1wYbBFEu0jDPcKmZd/5asEAjt0LGQbEBIsiGIrShcc+Bn3FwittPcka8J8H9o+Sk8eesndSa7WOcxK503Lg3Ukdfv+c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZainWfEj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZainWfEj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 041BFC32786; Fri, 23 Aug 2024 15:40:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724427641; bh=Rzi8UdSIlhz3Lz27Lgf4llrXyRuDGgJEajx2s+fq7bM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZainWfEjAcoLLIr/iwYN9VAPpOfo9SIuUVicFsmx/GEqolnS2f7HqQsExuei7QwOC xSdxTGWUenTNqzgSR4r36K88kVEB3HIbozH4X5K5pMYnPwBjbmiMn6K5enNIonQFWK ZoB+3mxo5eNK/HDzvGc8VKde7+x/YqS/PTmKes5nAcSn/uQZfnzqg6Y/7NH7i+myxR 4pDY8AJLRCYTWNuTuzEaBgojLWtcffJqBDRnREt8ou7VATyxfmKgcXLSR5Ces/a67C UIHh6QKY2fmSP+/HS/4ExaYYzA9t44E+LhoD/ObwZjx6GIYJbyTAkHCosPkIh7Ovur BE1qOWdS2uNCQ== From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Mika Westerberg Cc: "open list : PCI SUBSYSTEM" , open list , "open list : USB XHCI DRIVER" , Daniel Drake , Gary Li , Greg Kroah-Hartman , =?utf-8?q?Ilpo_J=C3=A4rvin?= =?utf-8?q?en?= , Mario Limonciello Subject: [PATCH v5 5/5] PCI: Drop Radeon quirk for Macbook Pro 8.2 Date: Fri, 23 Aug 2024 10:40:23 -0500 Message-ID: <20240823154023.360234-6-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823154023.360234-1-superm1@kernel.org> References: <20240823154023.360234-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello commit 5938628c51a7 ("drm/radeon: make MacBook Pro d3_delay quirk more generic") introduced a generic quirk for Macbook Pro 8.2s that contain Radeon graphics to ensure that enough time had past when the device was powered on. As the PCI core now verifies the device is in D0 during power on this extra artificial delay is no longer necessary. Signed-off-by: Mario Limonciello --- drivers/pci/quirks.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 3480a0445ff50..e76ff1037fb35 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2038,14 +2038,6 @@ static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) dev->d3hot_delay); } -static void quirk_radeon_pm(struct pci_dev *dev) -{ - if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && - dev->subsystem_device == 0x00e2) - quirk_d3hot_delay(dev, 20); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); - /* * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus * reset is performed too soon after transition to D0, extend d3hot_delay