From patchwork Mon Aug 26 11:15:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 895FFC5321D for ; Mon, 26 Aug 2024 11:14:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2392110E1AD; Mon, 26 Aug 2024 11:14:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Rvu+8AHD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 58F4310E1AA; Mon, 26 Aug 2024 11:14:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724670843; x=1756206843; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EYBIWQjdflTSjTogWjueep+mrfpHQ1XWbXtMEKF5kL8=; b=Rvu+8AHDTLNzgZZlcpu+o0/3sKzz6l4H5coXOyrN59Tx6vFWO+YCmrbI wJUMcJEbiVMoZw4wxf1E+3VmkBn+Uf/L0pqQ+vJ3GNNK5dIQw0+cgqipr i1veeOWYyn63M6K/5I604oK0sL8fwCGxGOykT/7SV6quKiSCgcAyrSD91 uwgcMQbchiT4bgCeXSkFEKQxfb9WzCtBHCc8iOSjcg84KxfQPbVgvj6po jIYlSiWa0R9cE951p19kJwUDe+oaRhKYdtacIdxGRffxDIBuKG4fOKW5L /Rj8QyFmYJZi3EttzwTaW4N2At7dhx4WjCSge+2AvpaUa+PauGiEk9MaL A==; X-CSE-ConnectionGUID: rgrgCDU6S+azQWbGJK9fPw== X-CSE-MsgGUID: iGjj3+8/SrmhrI2fMJ7Dtw== X-IronPort-AV: E=McAfee;i="6700,10204,11175"; a="23213526" X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="23213526" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:03 -0700 X-CSE-ConnectionGUID: nmZamRNdSQamOIOCGHtECA== X-CSE-MsgGUID: WWKNi1BTTION7d30Mf1hUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291274" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:02 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 01/12] drm/i915/display: Move all DSS control registers to a new file Date: Mon, 26 Aug 2024 16:45:15 +0530 Message-ID: <20240826111527.1113622-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move all registers and bits related to dss ctl to a new file. While at it, use REG_* macros for the fields. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/icl_dsi.c | 2 +- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_dss_regs.h | 49 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 1 + .../gpu/drm/i915/display/intel_vdsc_regs.h | 38 -------------- 6 files changed, 53 insertions(+), 41 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dss_regs.h diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 293efc1f841d..5ad5011e1fee 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -44,9 +44,9 @@ #include "intel_de.h" #include "intel_dsi.h" #include "intel_dsi_vbt.h" +#include "intel_dss_regs.h" #include "intel_panel.h" #include "intel_vdsc.h" -#include "intel_vdsc_regs.h" #include "skl_scaler.h" #include "skl_universal_plane.h" diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 25ff3ff0ab95..4566a60c981c 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -57,6 +57,7 @@ #include "intel_dp_tunnel.h" #include "intel_dpio_phy.h" #include "intel_dsi.h" +#include "intel_dss_regs.h" #include "intel_encoder.h" #include "intel_fdi.h" #include "intel_fifo_underrun.h" @@ -74,7 +75,6 @@ #include "intel_snps_phy.h" #include "intel_tc.h" #include "intel_vdsc.h" -#include "intel_vdsc_regs.h" #include "skl_scaler.h" #include "skl_universal_plane.h" diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1042f65967ba..8bce46bb7f3f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -87,6 +87,7 @@ #include "intel_drrs.h" #include "intel_dsb.h" #include "intel_dsi.h" +#include "intel_dss_regs.h" #include "intel_dvo.h" #include "intel_fb.h" #include "intel_fbc.h" @@ -118,7 +119,6 @@ #include "intel_tv.h" #include "intel_vblank.h" #include "intel_vdsc.h" -#include "intel_vdsc_regs.h" #include "intel_vga.h" #include "intel_vrr.h" #include "intel_wm.h" diff --git a/drivers/gpu/drm/i915/display/intel_dss_regs.h b/drivers/gpu/drm/i915/display/intel_dss_regs.h new file mode 100644 index 000000000000..462cc9aff4d7 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dss_regs.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_DSS_REGS_H__ +#define __INTEL_DSS_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* Display Stream Splitter Control */ +#define DSS_CTL1 _MMIO(0x67400) +#define SPLITTER_ENABLE REG_BIT(31) +#define JOINER_ENABLE REG_BIT(30) +#define DUAL_LINK_MODE_INTERLEAVE REG_BIT(24) +#define DUAL_LINK_MODE_FRONTBACK (0 << 24) +#define OVERLAP_PIXELS_MASK REG_GENMASK(19, 16) +#define OVERLAP_PIXELS(pixels) REG_FIELD_PREP(OVERLAP_PIXELS_MASK, pixels) +#define LEFT_DL_BUF_TARGET_DEPTH_MASK REG_GENMASK(12, 0) +#define LEFT_DL_BUF_TARGET_DEPTH(pixels) REG_FIELD_PREP(LEFT_DL_BUF_TARGET_DEPTH_MASK, pixels) +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 + +#define DSS_CTL2 _MMIO(0x67404) +#define LEFT_BRANCH_VDSC_ENABLE REG_BIT(31) +#define RIGHT_BRANCH_VDSC_ENABLE REG_BIT(15) +#define RIGHT_DL_BUF_TARGET_DEPTH_MASK REG_GENMASK(12, 0) +#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) REG_FIELD_PREP(RIGHT_DL_BUF_TARGET_DEPTH_MASK, pixels) + +#define _ICL_PIPE_DSS_CTL1_PB 0x78200 +#define _ICL_PIPE_DSS_CTL1_PC 0x78400 +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_PIPE_DSS_CTL1_PB, \ + _ICL_PIPE_DSS_CTL1_PC) +#define BIG_JOINER_ENABLE REG_BIT(29) +#define PRIMARY_BIG_JOINER_ENABLE REG_BIT(28) +#define VGA_CENTERING_ENABLE REG_BIT(27) +#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) +#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) +#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) +#define UNCOMPRESSED_JOINER_PRIMARY REG_BIT(21) +#define UNCOMPRESSED_JOINER_SECONDARY REG_BIT(20) + +#define _ICL_PIPE_DSS_CTL2_PB 0x78204 +#define _ICL_PIPE_DSS_CTL2_PC 0x78404 +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_PIPE_DSS_CTL2_PB, \ + _ICL_PIPE_DSS_CTL2_PC) + +#endif /* __INTEL_DSS_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 2e849b015e74..891346f1f09a 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -15,6 +15,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_dsi.h" +#include "intel_dss_regs.h" #include "intel_qp_tables.h" #include "intel_vdsc.h" #include "intel_vdsc_regs.h" diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index f921ad67b587..27c696e266af 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -8,44 +8,6 @@ #include "intel_display_reg_defs.h" -/* Display Stream Splitter Control */ -#define DSS_CTL1 _MMIO(0x67400) -#define SPLITTER_ENABLE (1 << 31) -#define JOINER_ENABLE (1 << 30) -#define DUAL_LINK_MODE_INTERLEAVE (1 << 24) -#define DUAL_LINK_MODE_FRONTBACK (0 << 24) -#define OVERLAP_PIXELS_MASK (0xf << 16) -#define OVERLAP_PIXELS(pixels) ((pixels) << 16) -#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) -#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 - -#define DSS_CTL2 _MMIO(0x67404) -#define LEFT_BRANCH_VDSC_ENABLE (1 << 31) -#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) -#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) -#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) - -#define _ICL_PIPE_DSS_CTL1_PB 0x78200 -#define _ICL_PIPE_DSS_CTL1_PC 0x78400 -#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_PIPE_DSS_CTL1_PB, \ - _ICL_PIPE_DSS_CTL1_PC) -#define BIG_JOINER_ENABLE (1 << 29) -#define PRIMARY_BIG_JOINER_ENABLE (1 << 28) -#define VGA_CENTERING_ENABLE (1 << 27) -#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) -#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) -#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) -#define UNCOMPRESSED_JOINER_PRIMARY (1 << 21) -#define UNCOMPRESSED_JOINER_SECONDARY (1 << 20) - -#define _ICL_PIPE_DSS_CTL2_PB 0x78204 -#define _ICL_PIPE_DSS_CTL2_PC 0x78404 -#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_PIPE_DSS_CTL2_PB, \ - _ICL_PIPE_DSS_CTL2_PC) - /* Icelake Display Stream Compression Registers */ #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) From patchwork Mon Aug 26 11:15:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3710EC5472E for ; Mon, 26 Aug 2024 11:14:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2347710E1AB; Mon, 26 Aug 2024 11:14:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="i1mwN6Ye"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D8E910E1AD; Mon, 26 Aug 2024 11:14:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724670845; x=1756206845; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ma1EJtPjYN8o2LuJIe/0GyFzb9FD8545FKwtc+pirnU=; b=i1mwN6YenNu+Pg16oDQ5ePM52+5oMl/eW0TcVENRulw9VYAfdor3LNSL j6RppJTDtioYBfTp7BUFWhq78Zfbna+Wk1xNPsKLWpA1Y4qkBs1SPGzaN T+Z5ECCeIjqJZ56yKVqtWqOGOgGjDr9/ZHxY/Ge0ckTtWuYlR9M6ecjDb UjfLkGNIBtgpL64A4Vp/dx+udB4thfRQ2TxHGeX5NrxHXK3qkW5XOlOP2 RaZpRTge7j64QrZwDs8qnT2vri6Z7SWFcDo3OKAD/Wi4zU2/ITuU7xsU8 rXjGCBDSX3K01m4yc34HIK5+Q3YezMdpOYh2kwfyFsPDq+7pqeDkGIVGU Q==; X-CSE-ConnectionGUID: O7vmbf5ZR3SuQ+HuWW5aug== X-CSE-MsgGUID: puT6YPgfSM+fJ9gbR6YMnw== X-IronPort-AV: E=McAfee;i="6700,10204,11175"; a="23213535" X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="23213535" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:05 -0700 X-CSE-ConnectionGUID: 6AgF2HFtTRiJLF1g9OTNKQ== X-CSE-MsgGUID: nTR4lrAQSFW1PNobsY/f/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291298" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:04 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 02/12] drm/i915/ddi: Move all mso related helpers to a new file Date: Mon, 26 Aug 2024 16:45:16 +0530 Message-ID: <20240826111527.1113622-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move the MSO related helper functions from intel_ddi.c to a new file intel_dss.c to improve code modularity and maintainability. The corresponding headers are also moved to intel_dss.h. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 86 ++--------------------- drivers/gpu/drm/i915/display/intel_dss.c | 87 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dss.h | 21 ++++++ drivers/gpu/drm/xe/Makefile | 1 + 5 files changed, 115 insertions(+), 81 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dss.c create mode 100644 drivers/gpu/drm/i915/display/intel_dss.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index c63fa2133ccb..e55ce8ba123c 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -328,6 +328,7 @@ i915-y += \ display/intel_dsi.o \ display/intel_dsi_dcs_backlight.o \ display/intel_dsi_vbt.o \ + display/intel_dss.o \ display/intel_dvo.o \ display/intel_encoder.o \ display/intel_gmbus.o \ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 4566a60c981c..28ef6814c56c 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -57,7 +57,7 @@ #include "intel_dp_tunnel.h" #include "intel_dpio_phy.h" #include "intel_dsi.h" -#include "intel_dss_regs.h" +#include "intel_dss.h" #include "intel_encoder.h" #include "intel_fdi.h" #include "intel_fifo_underrun.h" @@ -2349,82 +2349,6 @@ static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, } } -/* - * Splitter enable for eDP MSO is limited to certain pipes, on certain - * platforms. - */ -static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) -{ - if (DISPLAY_VER(i915) > 20) - return ~0; - else if (IS_ALDERLAKE_P(i915)) - return BIT(PIPE_A) | BIT(PIPE_B); - else - return BIT(PIPE_A); -} - -static void intel_ddi_mso_get_config(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) -{ - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; - u32 dss1; - - if (!HAS_MSO(i915)) - return; - - dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); - - pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; - if (!pipe_config->splitter.enable) - return; - - if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { - pipe_config->splitter.enable = false; - return; - } - - switch (dss1 & SPLITTER_CONFIGURATION_MASK) { - default: - drm_WARN(&i915->drm, true, - "Invalid splitter configuration, dss1=0x%08x\n", dss1); - fallthrough; - case SPLITTER_CONFIGURATION_2_SEGMENT: - pipe_config->splitter.link_count = 2; - break; - case SPLITTER_CONFIGURATION_4_SEGMENT: - pipe_config->splitter.link_count = 4; - break; - } - - pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); -} - -static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; - u32 dss1 = 0; - - if (!HAS_MSO(i915)) - return; - - if (crtc_state->splitter.enable) { - dss1 |= SPLITTER_ENABLE; - dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); - if (crtc_state->splitter.link_count == 2) - dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; - else - dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; - } - - intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), - SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | - OVERLAP_PIXELS_MASK, dss1); -} - static u8 mtl_get_port_width(u8 lane_count) { switch (lane_count) { @@ -2559,7 +2483,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. */ - intel_ddi_mso_configure(crtc_state); + intel_dss_configure_mso(crtc_state); if (!is_mst) intel_dp_set_power(intel_dp, DP_SET_POWER_D0); @@ -2714,7 +2638,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. */ - intel_ddi_mso_configure(crtc_state); + intel_dss_configure_mso(crtc_state); if (!is_mst) intel_dp_set_power(intel_dp, DP_SET_POWER_D0); @@ -3959,7 +3883,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, intel_ddi_read_func_ctl(encoder, pipe_config); - intel_ddi_mso_get_config(encoder, pipe_config); + intel_dss_get_mso_config(encoder, pipe_config); pipe_config->has_audio = intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); @@ -5191,7 +5115,7 @@ void intel_ddi_init(struct intel_display *display, dig_port->hpd_pulse = intel_dp_hpd_pulse; if (dig_port->dp.mso_link_count) - encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); + encoder->pipe_mask = intel_dss_splitter_pipe_mask(dev_priv); } /* diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c new file mode 100644 index 000000000000..41ea42d234f9 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dss.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#include "i915_drv.h" +#include "i915_reg_defs.h" +#include "intel_de.h" +#include "intel_display_types.h" +#include "intel_dss.h" +#include "intel_dss_regs.h" + +/* + * Splitter enable for eDP MSO is limited to certain pipes, on certain + * platforms. + */ +u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915) +{ + if (DISPLAY_VER(i915) > 20) + return ~0; + else if (IS_ALDERLAKE_P(i915)) + return BIT(PIPE_A) | BIT(PIPE_B); + else + return BIT(PIPE_A); +} + +void intel_dss_get_mso_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + u32 dss1; + + if (!HAS_MSO(i915)) + return; + + dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); + + pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; + if (!pipe_config->splitter.enable) + return; + + if (drm_WARN_ON(&i915->drm, !(intel_dss_splitter_pipe_mask(i915) & BIT(pipe)))) { + pipe_config->splitter.enable = false; + return; + } + + switch (dss1 & SPLITTER_CONFIGURATION_MASK) { + default: + drm_WARN(&i915->drm, true, + "Invalid splitter configuration, dss1=0x%08x\n", dss1); + fallthrough; + case SPLITTER_CONFIGURATION_2_SEGMENT: + pipe_config->splitter.link_count = 2; + break; + case SPLITTER_CONFIGURATION_4_SEGMENT: + pipe_config->splitter.link_count = 4; + break; + } + + pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); +} + +void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + u32 dss1 = 0; + + if (!HAS_MSO(i915)) + return; + + if (crtc_state->splitter.enable) { + dss1 |= SPLITTER_ENABLE; + dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); + if (crtc_state->splitter.link_count == 2) + dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; + else + dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; + } + + intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), + SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | + OVERLAP_PIXELS_MASK, dss1); +} diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h new file mode 100644 index 000000000000..632a00f0ebc1 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dss.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_DSS_H__ +#define __INTEL_DSS_H__ + +#include "linux/types.h" + +struct drm_i915_private; +struct intel_crtc_state; +struct intel_encoder; + +u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915); +void intel_dss_get_mso_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config); +void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state); + +#endif /* __INTEL_DSS_H__ */ + diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index b9670ae09a9e..619272783669 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -227,6 +227,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_dsi.o \ i915-display/intel_dsi_dcs_backlight.o \ i915-display/intel_dsi_vbt.o \ + i915-display/intel_dss.o \ i915-display/intel_encoder.o \ i915-display/intel_fb.o \ i915-display/intel_fbc.o \ From patchwork Mon Aug 26 11:15:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83E6FC5321E for ; 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X-CSE-ConnectionGUID: ErQTNM/NQRud6qOzK3OQRA== X-CSE-MsgGUID: kdfX16csRIu7yEQjxpcMbA== X-IronPort-AV: E=McAfee;i="6700,10204,11175"; a="23213541" X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="23213541" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:07 -0700 X-CSE-ConnectionGUID: 5xbwbSYtRHiL2qgi/ypfKg== X-CSE-MsgGUID: SjDoPthJQdenOtamJXUh6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291318" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:06 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 03/12] drm/i915/dss: Move to struct intel_display Date: Mon, 26 Aug 2024 16:45:17 +0530 Message-ID: <20240826111527.1113622-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use struct intel_display instead of struct drm_i915_private. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_dss.c | 22 +++++++++++----------- drivers/gpu/drm/i915/display/intel_dss.h | 4 ++-- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 28ef6814c56c..de7db5a028db 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -5115,7 +5115,7 @@ void intel_ddi_init(struct intel_display *display, dig_port->hpd_pulse = intel_dp_hpd_pulse; if (dig_port->dp.mso_link_count) - encoder->pipe_mask = intel_dss_splitter_pipe_mask(dev_priv); + encoder->pipe_mask = intel_dss_splitter_pipe_mask(display); } /* diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c index 41ea42d234f9..9cb89fe656cb 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.c +++ b/drivers/gpu/drm/i915/display/intel_dss.c @@ -14,11 +14,11 @@ * Splitter enable for eDP MSO is limited to certain pipes, on certain * platforms. */ -u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915) +u8 intel_dss_splitter_pipe_mask(struct intel_display *display) { - if (DISPLAY_VER(i915) > 20) + if (DISPLAY_VER(display) > 20) return ~0; - else if (IS_ALDERLAKE_P(i915)) + else if (IS_ALDERLAKE_P(to_i915(display->drm))) return BIT(PIPE_A) | BIT(PIPE_B); else return BIT(PIPE_A); @@ -27,28 +27,28 @@ u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915) void intel_dss_get_mso_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { + struct intel_display *display = to_intel_display(pipe_config); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 dss1; - if (!HAS_MSO(i915)) + if (!HAS_MSO(display)) return; - dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); + dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; if (!pipe_config->splitter.enable) return; - if (drm_WARN_ON(&i915->drm, !(intel_dss_splitter_pipe_mask(i915) & BIT(pipe)))) { + if (drm_WARN_ON(crtc->base.dev, !(intel_dss_splitter_pipe_mask(display) & BIT(pipe)))) { pipe_config->splitter.enable = false; return; } switch (dss1 & SPLITTER_CONFIGURATION_MASK) { default: - drm_WARN(&i915->drm, true, + drm_WARN(crtc->base.dev, true, "Invalid splitter configuration, dss1=0x%08x\n", dss1); fallthrough; case SPLITTER_CONFIGURATION_2_SEGMENT: @@ -64,12 +64,12 @@ void intel_dss_get_mso_config(struct intel_encoder *encoder, void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 dss1 = 0; - if (!HAS_MSO(i915)) + if (!HAS_MSO(display)) return; if (crtc_state->splitter.enable) { @@ -81,7 +81,7 @@ void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state) dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; } - intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), + intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | OVERLAP_PIXELS_MASK, dss1); } diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h index 632a00f0ebc1..0571ee2a19f9 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.h +++ b/drivers/gpu/drm/i915/display/intel_dss.h @@ -8,11 +8,11 @@ #include "linux/types.h" -struct drm_i915_private; struct intel_crtc_state; +struct intel_display; struct intel_encoder; -u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915); +u8 intel_dss_splitter_pipe_mask(struct intel_display *display); void intel_dss_get_mso_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config); void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state); From patchwork Mon Aug 26 11:15:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 168C4C5321D for ; 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X-CSE-ConnectionGUID: ABk0jy5pT1mI3cfeAHqhGg== X-CSE-MsgGUID: P5xMgFHySTuuO8k3QSJu7g== X-IronPort-AV: E=McAfee;i="6700,10204,11175"; a="23213546" X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="23213546" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:09 -0700 X-CSE-ConnectionGUID: /Tbq9++zSB69kuoH/yiPNA== X-CSE-MsgGUID: InMCifMDTA6cnmu/8mCbDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291340" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:08 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 04/12] drm/i915/icl_dsi: Move helpers to configure dsi dual link to intel_dss Date: Mon, 26 Aug 2024 16:45:18 +0530 Message-ID: <20240826111527.1113622-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move the function to configure dss_ctl for dual_link dsi to intel_dss files. While at it, use struct intel_display wherever possible. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/icl_dsi.c | 55 ++---------------------- drivers/gpu/drm/i915/display/intel_dss.c | 51 ++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dss.h | 3 ++ 3 files changed, 58 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 5ad5011e1fee..ab59638a8c6c 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -44,7 +44,7 @@ #include "intel_de.h" #include "intel_dsi.h" #include "intel_dsi_vbt.h" -#include "intel_dss_regs.h" +#include "intel_dss.h" #include "intel_panel.h" #include "intel_vdsc.h" #include "skl_scaler.h" @@ -274,55 +274,6 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) } } -static void configure_dual_link_mode(struct intel_encoder *encoder, - const struct intel_crtc_state *pipe_config) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - i915_reg_t dss_ctl1_reg, dss_ctl2_reg; - u32 dss_ctl1; - - /* FIXME: Move all DSS handling to intel_vdsc.c */ - if (DISPLAY_VER(dev_priv) >= 12) { - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - - dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); - dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); - } else { - dss_ctl1_reg = DSS_CTL1; - dss_ctl2_reg = DSS_CTL2; - } - - dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg); - dss_ctl1 |= SPLITTER_ENABLE; - dss_ctl1 &= ~OVERLAP_PIXELS_MASK; - dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); - - if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { - const struct drm_display_mode *adjusted_mode = - &pipe_config->hw.adjusted_mode; - u16 hactive = adjusted_mode->crtc_hdisplay; - u16 dl_buffer_depth; - - dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; - dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; - - if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) - drm_err(&dev_priv->drm, - "DL buffer depth exceed max value\n"); - - dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; - dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); - intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, - RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth)); - } else { - /* Interleave */ - dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; - } - - intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1); -} - /* aka DSI 8X clock */ static int afe_clk(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) @@ -791,7 +742,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, } /* configure stream splitting */ - configure_dual_link_mode(encoder, pipe_config); + intel_dss_configure_dsi_dual_link_mode(encoder, pipe_config, + intel_dsi->dual_link, + intel_dsi->pixel_overlap); } for_each_dsi_port(port, intel_dsi->ports) { diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c index 9cb89fe656cb..f44dcac84aa4 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.c +++ b/drivers/gpu/drm/i915/display/intel_dss.c @@ -7,6 +7,7 @@ #include "i915_reg_defs.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dsi.h" #include "intel_dss.h" #include "intel_dss_regs.h" @@ -85,3 +86,53 @@ void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state) SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | OVERLAP_PIXELS_MASK, dss1); } + +void intel_dss_configure_dsi_dual_link_mode(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config, + u8 dual_link, + u8 pixel_overlap) +{ + struct intel_display *display = to_intel_display(encoder); + i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + u32 dss_ctl1; + + if (DISPLAY_VER(display) >= 12) { + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); + + dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); + dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); + } else { + dss_ctl1_reg = DSS_CTL1; + dss_ctl2_reg = DSS_CTL2; + } + + dss_ctl1 = intel_de_read(display, dss_ctl1_reg); + dss_ctl1 |= SPLITTER_ENABLE; + dss_ctl1 &= ~OVERLAP_PIXELS_MASK; + dss_ctl1 |= OVERLAP_PIXELS(pixel_overlap); + + if (dual_link == DSI_DUAL_LINK_FRONT_BACK) { + struct drm_i915_private *i915 = to_i915(display->drm); + const struct drm_display_mode *adjusted_mode = + &pipe_config->hw.adjusted_mode; + u16 hactive = adjusted_mode->crtc_hdisplay; + u16 dl_buffer_depth; + + dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; + dl_buffer_depth = hactive / 2 + pixel_overlap; + + if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) + drm_err(&i915->drm, + "DL buffer depth exceed max value\n"); + + dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; + dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); + intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, + RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth)); + } else { + /* Interleave */ + dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; + } + + intel_de_write(display, dss_ctl1_reg, dss_ctl1); +} diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h index 0571ee2a19f9..0c5d652d46f5 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.h +++ b/drivers/gpu/drm/i915/display/intel_dss.h @@ -16,6 +16,9 @@ u8 intel_dss_splitter_pipe_mask(struct intel_display *display); void intel_dss_get_mso_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config); void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state); +void intel_dss_configure_dsi_dual_link_mode(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config, + u8 dual_link, u8 pixel_overlap); #endif /* __INTEL_DSS_H__ */ From patchwork Mon Aug 26 11:15:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C40B0C5472E for ; Mon, 26 Aug 2024 11:14:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6AFA710E1CD; Mon, 26 Aug 2024 11:14:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; 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a="23213552" X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="23213552" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:11 -0700 X-CSE-ConnectionGUID: 7j+kNp8fTJ+xhUJslLdcXQ== X-CSE-MsgGUID: rQdd6zUZQ1qMQHs8N/rgdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291358" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:10 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 05/12] drm/i915/vdsc: Rename helper to check if the pipe supports dsc Date: Mon, 26 Aug 2024 16:45:19 +0530 Message-ID: <20240826111527.1113622-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename the helper is_pipe_dsc to intel_dsc_is_pipe_dsc to prepare for its future use across multiple files. This change is a preliminary step towards making the function non-static, enhancing its accessibility and reusability. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 891346f1f09a..6d60b72a9dfb 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -35,7 +35,7 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) return true; } -static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder) +static bool intel_dsc_is_dsc_pipe(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); @@ -366,7 +366,7 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) */ if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) return POWER_DOMAIN_TRANSCODER_VDSC_PW2; - else if (is_pipe_dsc(crtc, cpu_transcoder)) + else if (intel_dsc_is_dsc_pipe(crtc, cpu_transcoder)) return POWER_DOMAIN_PIPE(pipe); else return POWER_DOMAIN_TRANSCODER_VDSC_PW2; @@ -395,7 +395,7 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int enum pipe pipe = crtc->pipe; bool pipe_dsc; - pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder); + pipe_dsc = intel_dsc_is_dsc_pipe(crtc, cpu_transcoder); if (dsc_reg_num >= 3) MISSING_CASE(dsc_reg_num); @@ -538,7 +538,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) rc_buf_thresh_dword[i / 4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] << BITS_PER_BYTE * (i % 4)); - if (!is_pipe_dsc(crtc, cpu_transcoder)) { + if (!intel_dsc_is_dsc_pipe(crtc, cpu_transcoder)) { intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, @@ -592,7 +592,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) RC_MAX_QP_SHIFT) | (vdsc_cfg->rc_range_params[i].range_min_qp << RC_MIN_QP_SHIFT)) << 16 * (i % 2)); - if (!is_pipe_dsc(crtc, cpu_transcoder)) { + if (!intel_dsc_is_dsc_pipe(crtc, cpu_transcoder)) { intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, rc_range_params_dword[0]); intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, @@ -726,13 +726,13 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder, static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { - return is_pipe_dsc(crtc, cpu_transcoder) ? + return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ? ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; } static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { - return is_pipe_dsc(crtc, cpu_transcoder) ? + return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ? ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; } From patchwork Mon Aug 26 11:15:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E444DC54731 for ; Mon, 26 Aug 2024 11:14:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 87F7310E1D2; Mon, 26 Aug 2024 11:14:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="k7jZf5qx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id E924810E1D1; Mon, 26 Aug 2024 11:14:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724670854; x=1756206854; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xVUgr2bCMr3qpsvwtFBUqQ5BdGlv6CQsKwkw8bTjrAg=; b=k7jZf5qxocxC5MBjKXUv1a20S6AmPMXjBvoWpXHnnY/b7LFwdW0rciNu 5sqW6BBt6ChxXZXtkZotbKFut2zvEh+mG4ppLNilpoY6qzDDM5QjL5DKe Y2xxqBOhBlEwuRbcFqBZiCE2Wa+7AJ653jL5FVynlkvenot6ZozZ3frnD S1NGwyHyGQiXcXxZeQ72TH9kBUZtSNWftxR9DoMdVVyOxz11Fhz8fjWss atLVYbTyADvV2+/JakiwPp5bnsib61mCuSkpRNFN7lusSLYNQKu71iE8d Ij+KGiM5pfFP6SxVoQ6Ps7kOAPG8fM+74OoneR2fT5vMc4HgBBBpThRej A==; X-CSE-ConnectionGUID: otoNx5UqTZywdTWpiUG2bA== X-CSE-MsgGUID: ycl/CivPSXaS63p0XU2sgQ== X-IronPort-AV: E=McAfee;i="6700,10204,11175"; a="23213561" X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="23213561" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:14 -0700 X-CSE-ConnectionGUID: yYOj3OnYRx+66N9/BtcCFg== X-CSE-MsgGUID: O8q8KCXpTXe6T7gG2y8YOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291386" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:12 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 06/12] drm/i915/vdsc: Move all dss stuff in dss files Date: Mon, 26 Aug 2024 16:45:20 +0530 Message-ID: <20240826111527.1113622-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move helpers to configure dss for compressed and uncompressed joiner to intel_dss files. While at it, replace struct drm_i915_private to struct intel_display wherever possible. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 3 +- drivers/gpu/drm/i915/display/intel_dss.c | 78 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dss.h | 5 ++ drivers/gpu/drm/i915/display/intel_vdsc.c | 67 ++--------------- drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +- 5 files changed, 92 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 8bce46bb7f3f..05ffd28cc16a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -87,6 +87,7 @@ #include "intel_drrs.h" #include "intel_dsb.h" #include "intel_dsi.h" +#include "intel_dss.h" #include "intel_dss_regs.h" #include "intel_dvo.h" #include "intel_fb.h" @@ -1711,7 +1712,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_dsc_enable(pipe_crtc_state); if (DISPLAY_VER(dev_priv) >= 13) - intel_uncompressed_joiner_enable(pipe_crtc_state); + intel_dss_enable_uncompressed_joiner(pipe_crtc_state); intel_set_pipe_src_size(pipe_crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c index f44dcac84aa4..8b2841689bfb 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.c +++ b/drivers/gpu/drm/i915/display/intel_dss.c @@ -6,10 +6,12 @@ #include "i915_drv.h" #include "i915_reg_defs.h" #include "intel_de.h" +#include "intel_display_limits.h" #include "intel_display_types.h" #include "intel_dsi.h" #include "intel_dss.h" #include "intel_dss_regs.h" +#include "intel_vdsc.h" /* * Splitter enable for eDP MSO is limited to certain pipes, on certain @@ -136,3 +138,79 @@ void intel_dss_configure_dsi_dual_link_mode(struct intel_encoder *encoder, intel_de_write(display, dss_ctl1_reg, dss_ctl1); } + +static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) +{ + return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ? + ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; +} + +static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) +{ + return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ? + ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; +} + +void intel_dss_reset(const struct intel_crtc_state *old_crtc_state) +{ + struct intel_display *display = to_intel_display(old_crtc_state); + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); + + intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); + intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); +} + +void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + u32 dss_ctl1_val = 0; + + if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) { + if (intel_crtc_is_joiner_secondary(crtc_state)) + dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY; + else + dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY; + + intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); + } +} + +void intel_dss_enable_compressed_joiner(const struct intel_crtc_state *crtc_state, + int vdsc_instances_per_pipe) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + u32 dss_ctl1_val = 0; + u32 dss_ctl2_val = 0; + + dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; + if (vdsc_instances_per_pipe > 1) { + dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; + dss_ctl1_val |= JOINER_ENABLE; + } + if (crtc_state->joiner_pipes) { + dss_ctl1_val |= BIG_JOINER_ENABLE; + if (!intel_crtc_is_joiner_secondary(crtc_state)) + dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; + } + intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); + intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); +} + +void intel_dss_get_dsc_config(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + u32 dss_ctl1, dss_ctl2; + + dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder)); + dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder)); + + crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; + if (!crtc_state->dsc.compression_enable) + return; + + crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && + (dss_ctl1 & JOINER_ENABLE); +} diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h index 0c5d652d46f5..2dadbe76cbf9 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.h +++ b/drivers/gpu/drm/i915/display/intel_dss.h @@ -19,6 +19,11 @@ void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state); void intel_dss_configure_dsi_dual_link_mode(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, u8 dual_link, u8 pixel_overlap); +void intel_dss_reset(const struct intel_crtc_state *old_crtc_state); +void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_state); +void intel_dss_enable_compressed_joiner(const struct intel_crtc_state *crtc_state, + int vdsc_instances_per_pipe); +void intel_dss_get_dsc_config(struct intel_crtc_state *crtc_state); #endif /* __INTEL_DSS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 6d60b72a9dfb..c278290dcfb9 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -15,7 +15,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_dsi.h" -#include "intel_dss_regs.h" +#include "intel_dss.h" #include "intel_qp_tables.h" #include "intel_vdsc.h" #include "intel_vdsc_regs.h" @@ -35,7 +35,7 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) return true; } -static bool intel_dsc_is_dsc_pipe(struct intel_crtc *crtc, enum transcoder cpu_transcoder) +bool intel_dsc_is_dsc_pipe(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); @@ -724,72 +724,23 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder, sizeof(dp_dsc_pps_sdp)); } -static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) -{ - return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ? - ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; -} - -static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) -{ - return intel_dsc_is_dsc_pipe(crtc, cpu_transcoder) ? - ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; -} - -void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 dss_ctl1_val = 0; - - if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) { - if (intel_crtc_is_joiner_secondary(crtc_state)) - dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY; - else - dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY; - - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); - } -} - void intel_dsc_enable(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 dss_ctl1_val = 0; - u32 dss_ctl2_val = 0; int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); if (!crtc_state->dsc.compression_enable) return; intel_dsc_pps_configure(crtc_state); - - dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; - if (vdsc_instances_per_pipe > 1) { - dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; - dss_ctl1_val |= JOINER_ENABLE; - } - if (crtc_state->joiner_pipes) { - dss_ctl1_val |= BIG_JOINER_ENABLE; - if (!intel_crtc_is_joiner_secondary(crtc_state)) - dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; - } - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); - intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); + intel_dss_enable_compressed_joiner(crtc_state, vdsc_instances_per_pipe); } void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - /* Disable only if either of them is enabled */ if (old_crtc_state->dsc.compression_enable || - old_crtc_state->joiner_pipes) { - intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); - intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); - } + old_crtc_state->joiner_pipes) + intel_dss_reset(old_crtc_state); } static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, @@ -946,7 +897,6 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; - u32 dss_ctl1, dss_ctl2; if (!intel_dsc_source_support(crtc_state)) return; @@ -957,16 +907,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) if (!wakeref) return; - dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); - dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); + intel_dss_get_dsc_config(crtc_state); - crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; if (!crtc_state->dsc.compression_enable) goto out; - crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && - (dss_ctl1 & JOINER_ENABLE); - intel_dsc_get_pps_config(crtc_state); out: intel_display_power_put(dev_priv, power_domain, wakeref); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index 290b2e9b3482..345956d0c77e 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -16,7 +16,6 @@ struct intel_crtc_state; struct intel_encoder; bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state); -void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state); void intel_dsc_enable(const struct intel_crtc_state *crtc_state); void intel_dsc_disable(const struct intel_crtc_state *crtc_state); int intel_dsc_compute_params(struct intel_crtc_state *pipe_config); @@ -31,5 +30,6 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_vdsc_state_dump(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state); +bool intel_dsc_is_dsc_pipe(struct intel_crtc *crtc, enum transcoder cpu_transcoder); #endif /* __INTEL_VDSC_H__ */ From patchwork Mon Aug 26 11:15:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0886FC5321E for ; Mon, 26 Aug 2024 11:14:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A9C4E10E1D5; Mon, 26 Aug 2024 11:14:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hwqf1w3K"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id F07EC10E1D4; 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26 Aug 2024 04:14:16 -0700 X-CSE-ConnectionGUID: qOizMFU1T8qH5souAK6Gkg== X-CSE-MsgGUID: DxiV/Qu7TFa3Y+XxpK+LmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291404" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:14 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 07/12] drm/i915/display: Move dss stuff in intel_dss files Date: Mon, 26 Aug 2024 16:45:21 +0530 Message-ID: <20240826111527.1113622-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move helper to retrieve the compressed and uncompressed joiner pipes from dss ctl to intel_dss files. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 34 +++----------- drivers/gpu/drm/i915/display/intel_dss.c | 48 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dss.h | 9 ++++ 3 files changed, 64 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 05ffd28cc16a..ab57c2f39cf5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3545,35 +3545,15 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, joiner_pipes(dev_priv)) { - enum intel_display_power_domain power_domain; - enum pipe pipe = crtc->pipe; - intel_wakeref_t wakeref; - - power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); - with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { - u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); - - if (!(tmp & BIG_JOINER_ENABLE)) - continue; + struct intel_display *display = &dev_priv->display; - if (tmp & PRIMARY_BIG_JOINER_ENABLE) - *primary_pipes |= BIT(pipe); - else - *secondary_pipes |= BIT(pipe); - } - - if (DISPLAY_VER(dev_priv) < 13) - continue; - - power_domain = POWER_DOMAIN_PIPE(pipe); - with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { - u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); + intel_dss_get_compressed_joiner_pipes(display, crtc, + primary_pipes, + secondary_pipes); - if (tmp & UNCOMPRESSED_JOINER_PRIMARY) - *primary_pipes |= BIT(pipe); - if (tmp & UNCOMPRESSED_JOINER_SECONDARY) - *secondary_pipes |= BIT(pipe); - } + intel_dss_get_uncompressed_joiner_pipes(display, crtc, + primary_pipes, + secondary_pipes); } /* Joiner pipes should always be consecutive primary and secondary */ diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c index 8b2841689bfb..fadaf1f2674c 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.c +++ b/drivers/gpu/drm/i915/display/intel_dss.c @@ -214,3 +214,51 @@ void intel_dss_get_dsc_config(struct intel_crtc_state *crtc_state) crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && (dss_ctl1 & JOINER_ENABLE); } + +void intel_dss_get_compressed_joiner_pipes(struct intel_display *display, + struct intel_crtc *crtc, + u8 *primary_pipes, + u8 *secondary_pipes) +{ + struct drm_i915_private *i915 = to_i915(display->drm); + enum intel_display_power_domain power_domain; + enum pipe pipe = crtc->pipe; + intel_wakeref_t wakeref; + + power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); + with_intel_display_power_if_enabled(i915, power_domain, wakeref) { + u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); + + if (!(tmp & BIG_JOINER_ENABLE)) + continue; + + if (tmp & PRIMARY_BIG_JOINER_ENABLE) + *primary_pipes |= BIT(pipe); + else + *secondary_pipes |= BIT(pipe); + } +} + +void intel_dss_get_uncompressed_joiner_pipes(struct intel_display *display, + struct intel_crtc *crtc, + u8 *primary_pipes, + u8 *secondary_pipes) +{ + struct drm_i915_private *i915 = to_i915(display->drm); + enum intel_display_power_domain power_domain; + enum pipe pipe = crtc->pipe; + intel_wakeref_t wakeref; + + if (DISPLAY_VER(display) < 13) + return; + + power_domain = POWER_DOMAIN_PIPE(pipe); + with_intel_display_power_if_enabled(i915, power_domain, wakeref) { + u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); + + if (tmp & UNCOMPRESSED_JOINER_PRIMARY) + *primary_pipes |= BIT(pipe); + if (tmp & UNCOMPRESSED_JOINER_SECONDARY) + *secondary_pipes |= BIT(pipe); + } +} diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h index 2dadbe76cbf9..16d2bbc3add8 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.h +++ b/drivers/gpu/drm/i915/display/intel_dss.h @@ -11,6 +11,7 @@ struct intel_crtc_state; struct intel_display; struct intel_encoder; +struct intel_crtc; u8 intel_dss_splitter_pipe_mask(struct intel_display *display); void intel_dss_get_mso_config(struct intel_encoder *encoder, @@ -24,6 +25,14 @@ void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_st void intel_dss_enable_compressed_joiner(const struct intel_crtc_state *crtc_state, int vdsc_instances_per_pipe); void intel_dss_get_dsc_config(struct intel_crtc_state *crtc_state); +void intel_dss_get_compressed_joiner_pipes(struct intel_display *display, + struct intel_crtc *crtc, + u8 *primary_pipes, + u8 *secondary_pipes); +void intel_dss_get_uncompressed_joiner_pipes(struct intel_display *display, + struct intel_crtc *crtc, + u8 *primary_pipes, + u8 *secondary_pipes); #endif /* __INTEL_DSS_H__ */ From patchwork Mon Aug 26 11:15:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6727C5321D for ; Mon, 26 Aug 2024 11:14:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EB3510E1D9; Mon, 26 Aug 2024 11:14:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OpWIraZw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0D28A10E1D8; Mon, 26 Aug 2024 11:14:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724670858; x=1756206858; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oGfAX2zDM3KoDv+cySuV+SqMvBxttUxxO4SSFAJzuU4=; b=OpWIraZwgjEnk+DMkDCp3/nQLknZ5u5nENfjwIqgUxi13XYNUDH4evhD mF/AOB4NvFRxh+JZl15kt01lpix0F0BJ3H/O5QT/KHzVyWHaFUvApgCT+ MtNGD4WgDNNL1jnaM3QjlnFjoKB3gBaqf/xcgS2cOnOO3TZWlsq8wKPjQ jlw+gkykGRNO00roc0Kwtt+YWq9sXfuyV9UxGd6VPmCe8XXZVzO8en0+F xW2f48NEFb76Wrewl/++84mhG/GOyNhAYo/fzAq/iWwB0WfjelYQ27FQt 5P7fYaOFdtpHRw8YbPzU/b0DopgAKBIVLq/cb8UOKPgzDZA6opK78k25e g==; X-CSE-ConnectionGUID: Z/VTChi7SMa9WK58YVCsaQ== X-CSE-MsgGUID: UqRiP6dSTUeSikMe2Y2D8Q== X-IronPort-AV: E=McAfee;i="6700,10204,11175"; a="23213575" X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="23213575" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:18 -0700 X-CSE-ConnectionGUID: eV3bn4TWTjyFtpDXok0aeg== X-CSE-MsgGUID: SLVWq0KbRTKwUs8L60z/LA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291416" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:16 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 08/12] drm/i915/display: Move helper to get joined pipe mask to intel_dss Date: Mon, 26 Aug 2024 16:45:22 +0530 Message-ID: <20240826111527.1113622-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename intel_crtc_joined_pipe_mask with intel_dss_get_joined_pipe_mask and move it to intel_dss files. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++--- drivers/gpu/drm/i915/display/intel_display.c | 35 ++++++++------------ drivers/gpu/drm/i915/display/intel_display.h | 1 - drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 ++-- drivers/gpu/drm/i915/display/intel_dss.c | 7 ++++ drivers/gpu/drm/i915/display/intel_dss.h | 1 + 6 files changed, 30 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index de7db5a028db..9421f0c4d25e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3043,7 +3043,7 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, struct intel_crtc *pipe_crtc; for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + intel_dss_get_joined_pipe_mask(old_crtc_state)) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -3055,7 +3055,7 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, intel_ddi_disable_transcoder_func(old_crtc_state); for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + intel_dss_get_joined_pipe_mask(old_crtc_state)) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -3319,7 +3319,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state, intel_ddi_wait_for_fec_status(encoder, crtc_state, true); for_each_intel_crtc_in_pipe_mask_reverse(&i915->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(crtc_state)) { + intel_dss_get_joined_pipe_mask(crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -3429,7 +3429,7 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state, return; for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(crtc_state)) + intel_dss_get_joined_pipe_mask(crtc_state)) intel_update_active_dpll(state, pipe_crtc, encoder); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ab57c2f39cf5..1c0d297c250b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -283,13 +283,6 @@ static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state) return hweight8(crtc_state->joiner_pipes); } -u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - - return BIT(crtc->pipe) | crtc_state->joiner_pipes; -} - struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); @@ -1688,13 +1681,13 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, return; for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) + intel_dss_get_joined_pipe_mask(new_crtc_state)) intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe); intel_encoders_pre_pll_enable(state, crtc); for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) { + intel_dss_get_joined_pipe_mask(new_crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -1705,7 +1698,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_encoders_pre_enable(state, crtc); for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) { + intel_dss_get_joined_pipe_mask(new_crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -1724,7 +1717,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, hsw_configure_cpu_transcoder(new_crtc_state); for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) { + intel_dss_get_joined_pipe_mask(new_crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -1760,7 +1753,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_encoders_enable(state, crtc); for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) { + intel_dss_get_joined_pipe_mask(new_crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); enum pipe hsw_workaround_pipe; @@ -1855,7 +1848,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, intel_encoders_post_disable(state, crtc); for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + intel_dss_get_joined_pipe_mask(old_crtc_state)) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -1865,7 +1858,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, intel_encoders_post_pll_disable(state, crtc); for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) + intel_dss_get_joined_pipe_mask(old_crtc_state)) intel_dmc_disable_pipe(i915, pipe_crtc->pipe); } @@ -6852,7 +6845,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state, return; for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) { + intel_dss_get_joined_pipe_mask(new_crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -6965,13 +6958,13 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state, * or we race against vblank off. */ for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) + intel_dss_get_joined_pipe_mask(old_crtc_state)) intel_crtc_disable_pipe_crc(pipe_crtc); dev_priv->display.funcs.display->crtc_disable(state, crtc); for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + intel_dss_get_joined_pipe_mask(old_crtc_state)) { const struct intel_crtc_state *new_pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -7036,7 +7029,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) intel_old_crtc_state_disables(state, crtc); - disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); + disable_pipes &= ~intel_dss_get_joined_pipe_mask(old_crtc_state); } /* Disable everything else left on */ @@ -7049,7 +7042,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) intel_old_crtc_state_disables(state, crtc); - disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); + disable_pipes &= ~intel_dss_get_joined_pipe_mask(old_crtc_state); } drm_WARN_ON(&i915->drm, disable_pipes); @@ -7176,7 +7169,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) is_trans_port_sync_master(new_crtc_state)) continue; - modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); + modeset_pipes &= ~intel_dss_get_joined_pipe_mask(new_crtc_state); intel_enable_crtc(state, crtc); } @@ -7194,7 +7187,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if (intel_crtc_is_joiner_secondary(new_crtc_state)) continue; - modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); + modeset_pipes &= ~intel_dss_get_joined_pipe_mask(new_crtc_state); intel_enable_crtc(state, crtc); } diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index b0cf6ca70952..b9316373dad3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -422,7 +422,6 @@ intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915, enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); bool is_trans_port_sync_mode(const struct intel_crtc_state *state); bool is_trans_port_sync_master(const struct intel_crtc_state *state); -u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state); bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state); bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state); u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 45d2230d1801..59da0712b0eb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -45,6 +45,7 @@ #include "intel_dp_tunnel.h" #include "intel_dp_link_training.h" #include "intel_dpio_phy.h" +#include "intel_dss.h" #include "intel_hdcp.h" #include "intel_hotplug.h" #include "intel_link_bw.h" @@ -1009,7 +1010,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, !intel_dp_mst_is_master_trans(old_crtc_state)); for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + intel_dss_get_joined_pipe_mask(old_crtc_state)) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -1034,7 +1035,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, intel_ddi_disable_transcoder_func(old_crtc_state); for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + intel_dss_get_joined_pipe_mask(old_crtc_state)) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -1301,7 +1302,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, intel_enable_transcoder(pipe_config); for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(pipe_config)) { + intel_dss_get_joined_pipe_mask(pipe_config)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c index fadaf1f2674c..89a8c9205a3f 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.c +++ b/drivers/gpu/drm/i915/display/intel_dss.c @@ -262,3 +262,10 @@ void intel_dss_get_uncompressed_joiner_pipes(struct intel_display *display, *secondary_pipes |= BIT(pipe); } } + +u8 intel_dss_get_joined_pipe_mask(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + return BIT(crtc->pipe) | crtc_state->joiner_pipes; +} diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h index 16d2bbc3add8..cf2ee3f028bb 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.h +++ b/drivers/gpu/drm/i915/display/intel_dss.h @@ -33,6 +33,7 @@ void intel_dss_get_uncompressed_joiner_pipes(struct intel_display *display, struct intel_crtc *crtc, u8 *primary_pipes, u8 *secondary_pipes); +u8 intel_dss_get_joined_pipe_mask(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_DSS_H__ */ From patchwork Mon Aug 26 11:15:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1EB82C5321D for ; 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X-CSE-ConnectionGUID: WSyFSv+1Tr6i0dE6jJfHKA== X-CSE-MsgGUID: ZuFiQenzRlSeJTQINz6zLw== X-IronPort-AV: E=McAfee;i="6700,10204,11175"; a="23213578" X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="23213578" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:20 -0700 X-CSE-ConnectionGUID: Dbs/mLPxTeyw201VVMIm9Q== X-CSE-MsgGUID: p1iBbC99QhujjC4vu5n4lg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291422" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:18 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 09/12] drm/i915/display: Move helpers for primary joiner to intel_dss Date: Mon, 26 Aug 2024 16:45:23 +0530 Message-ID: <20240826111527.1113622-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move helpers to get/check primary joiner pipes to intel_dss. Rename them to align with other intel_dss helpers. Signed-off-by: Ankit Nautiyal --- .../drm/i915/display/intel_crtc_state_dump.c | 3 +- drivers/gpu/drm/i915/display/intel_display.c | 33 ++++++------------- drivers/gpu/drm/i915/display/intel_display.h | 1 - drivers/gpu/drm/i915/display/intel_dss.c | 13 ++++++++ drivers/gpu/drm/i915/display/intel_dss.h | 4 +++ 5 files changed, 29 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 705ec5ad385c..f2764f283f9b 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "intel_crtc_state_dump.h" #include "intel_display_types.h" +#include "intel_dss.h" #include "intel_hdmi.h" #include "intel_vdsc.h" #include "intel_vrr.h" @@ -225,7 +226,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, drm_printf(&p, "joiner: %s, pipes: 0x%x\n", intel_crtc_is_joiner_secondary(pipe_config) ? "secondary" : - intel_crtc_is_joiner_primary(pipe_config) ? "primary" : "no", + intel_dss_is_primary_joiner_pipe(pipe_config) ? "primary" : "no", pipe_config->joiner_pipes); drm_printf(&p, "splitter: %s, link count %d, overlap %d\n", diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1c0d297c250b..a7b136689695 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -249,15 +249,10 @@ is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) is_trans_port_sync_slave(crtc_state); } -static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state) -{ - return ffs(crtc_state->joiner_pipes) - 1; -} - u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state) { if (crtc_state->joiner_pipes) - return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state)); + return crtc_state->joiner_pipes & ~BIT(intel_dss_get_primary_joiner_pipe(crtc_state)); else return 0; } @@ -267,15 +262,7 @@ bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); return crtc_state->joiner_pipes && - crtc->pipe != joiner_primary_pipe(crtc_state); -} - -bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - - return crtc_state->joiner_pipes && - crtc->pipe == joiner_primary_pipe(crtc_state); + crtc->pipe != intel_dss_get_primary_joiner_pipe(crtc_state); } static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state) @@ -288,7 +275,7 @@ struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); if (intel_crtc_is_joiner_secondary(crtc_state)) - return intel_crtc_for_pipe(i915, joiner_primary_pipe(crtc_state)); + return intel_crtc_for_pipe(i915, intel_dss_get_primary_joiner_pipe(crtc_state)); else return to_intel_crtc(crtc_state->uapi.crtc); } @@ -2888,7 +2875,7 @@ static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) if (num_pipes < 2) return; - primary_pipe = joiner_primary_pipe(crtc_state); + primary_pipe = intel_dss_get_primary_joiner_pipe(crtc_state); width = drm_rect_width(&crtc_state->pipe_src); drm_rect_translate_to(&crtc_state->pipe_src, @@ -3555,7 +3542,7 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, *primary_pipes, *secondary_pipes); } -static enum pipe get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes) +static enum pipe get_intel_dss_get_primary_joiner_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes) { if ((secondary_pipes & BIT(pipe)) == 0) return pipe; @@ -3571,7 +3558,7 @@ static u8 get_joiner_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 second { enum pipe primary_pipe, next_primary_pipe; - primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes); + primary_pipe = get_intel_dss_get_primary_joiner_pipe(pipe, primary_pipes, secondary_pipes); if ((primary_pipes & BIT(primary_pipe)) == 0) return 0; @@ -3658,7 +3645,7 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) enabled_joiner_pipes(dev_priv, &primary_pipes, &secondary_pipes); if (secondary_pipes & BIT(crtc->pipe)) { cpu_transcoder = (enum transcoder) - get_joiner_primary_pipe(crtc->pipe, primary_pipes, secondary_pipes); + get_intel_dss_get_primary_joiner_pipe(crtc->pipe, primary_pipes, secondary_pipes); if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) enabled_transcoders |= BIT(cpu_transcoder); } @@ -3798,7 +3785,7 @@ static void intel_joiner_get_config(struct intel_crtc_state *crtc_state) return; crtc_state->joiner_pipes = - BIT(get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes)) | + BIT(get_intel_dss_get_primary_joiner_pipe(pipe, primary_pipes, secondary_pipes)) | get_joiner_secondary_pipes(pipe, primary_pipes, secondary_pipes); } @@ -5982,7 +5969,7 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state, /* sanity check */ if (drm_WARN_ON(&i915->drm, - primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))) + primary_crtc->pipe != intel_dss_get_primary_joiner_pipe(primary_crtc_state))) return -EINVAL; if (primary_crtc_state->joiner_pipes & ~joiner_pipes(i915)) { @@ -6380,7 +6367,7 @@ static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state) for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { /* Kill old joiner link, we may re-establish afterwards */ if (intel_crtc_needs_modeset(crtc_state) && - intel_crtc_is_joiner_primary(crtc_state)) + intel_dss_is_primary_joiner_pipe(crtc_state)) kill_joiner_secondaries(state, crtc); } diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index b9316373dad3..0135c959632d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -423,7 +423,6 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); bool is_trans_port_sync_mode(const struct intel_crtc_state *state); bool is_trans_port_sync_master(const struct intel_crtc_state *state); bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state); -bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state); u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state); struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state); bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c index 89a8c9205a3f..1a8bfd8e9247 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.c +++ b/drivers/gpu/drm/i915/display/intel_dss.c @@ -269,3 +269,16 @@ u8 intel_dss_get_joined_pipe_mask(const struct intel_crtc_state *crtc_state) return BIT(crtc->pipe) | crtc_state->joiner_pipes; } + +enum pipe intel_dss_get_primary_joiner_pipe(const struct intel_crtc_state *crtc_state) +{ + return ffs(crtc_state->joiner_pipes) - 1; +} + +bool intel_dss_is_primary_joiner_pipe(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + return crtc_state->joiner_pipes && + crtc->pipe == intel_dss_get_primary_joiner_pipe(crtc_state); +} diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h index cf2ee3f028bb..e627582f6883 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.h +++ b/drivers/gpu/drm/i915/display/intel_dss.h @@ -8,6 +8,8 @@ #include "linux/types.h" +enum pipe; + struct intel_crtc_state; struct intel_display; struct intel_encoder; @@ -34,6 +36,8 @@ void intel_dss_get_uncompressed_joiner_pipes(struct intel_display *display, u8 *primary_pipes, u8 *secondary_pipes); u8 intel_dss_get_joined_pipe_mask(const struct intel_crtc_state *crtc_state); +enum pipe intel_dss_get_primary_joiner_pipe(const struct intel_crtc_state *crtc_state); +bool intel_dss_is_primary_joiner_pipe(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_DSS_H__ */ From patchwork Mon Aug 26 11:15:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BEA6C5321E for ; Mon, 26 Aug 2024 11:14:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F0B7A10E1DA; Mon, 26 Aug 2024 11:14:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UP+cFRj7"; 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d="scan'208";a="23213585" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:22 -0700 X-CSE-ConnectionGUID: VPLW8VP8QSKby1Nr9AOCRA== X-CSE-MsgGUID: rw2ttk+jQdmVZ370pan3Rg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291430" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:20 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 10/12] drm/i915/display: Move helper to check for secondary joiner pipe Date: Mon, 26 Aug 2024 16:45:24 +0530 Message-ID: <20240826111527.1113622-11-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move the helper to check secondary joiner pipes to intel_dss. Signed-off-by: Ankit Nautiyal --- .../gpu/drm/i915/display/intel_atomic_plane.c | 3 +- .../drm/i915/display/intel_crtc_state_dump.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 30 +++++++------------ drivers/gpu/drm/i915/display/intel_display.h | 1 - .../drm/i915/display/intel_display_debugfs.c | 3 +- drivers/gpu/drm/i915/display/intel_drrs.c | 5 ++-- drivers/gpu/drm/i915/display/intel_dss.c | 12 ++++++-- drivers/gpu/drm/i915/display/intel_dss.h | 1 + .../drm/i915/display/intel_modeset_setup.c | 9 +++--- 9 files changed, 35 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index e979786aa5cf..eb9075e4ea3f 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -47,6 +47,7 @@ #include "intel_display_rps.h" #include "intel_display_trace.h" #include "intel_display_types.h" +#include "intel_dss.h" #include "intel_fb.h" #include "intel_fb_pin.h" #include "skl_scaler.h" @@ -722,7 +723,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - if (new_crtc_state && intel_crtc_is_joiner_secondary(new_crtc_state)) { + if (new_crtc_state && intel_dss_is_secondary_joiner_pipe(new_crtc_state)) { struct intel_crtc *primary_crtc = intel_primary_crtc(new_crtc_state); struct intel_plane *primary_crtc_plane = diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index f2764f283f9b..cc1532ec6afc 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -225,7 +225,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, pipe_config->sync_mode_slaves_mask); drm_printf(&p, "joiner: %s, pipes: 0x%x\n", - intel_crtc_is_joiner_secondary(pipe_config) ? "secondary" : + intel_dss_is_secondary_joiner_pipe(pipe_config) ? "secondary" : intel_dss_is_primary_joiner_pipe(pipe_config) ? "primary" : "no", pipe_config->joiner_pipes); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a7b136689695..151cd6ad47f1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -257,14 +257,6 @@ u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state) return 0; } -bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - - return crtc_state->joiner_pipes && - crtc->pipe != intel_dss_get_primary_joiner_pipe(crtc_state); -} - static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state) { return hweight8(crtc_state->joiner_pipes); @@ -274,7 +266,7 @@ struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - if (intel_crtc_is_joiner_secondary(crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(crtc_state)) return intel_crtc_for_pipe(i915, intel_dss_get_primary_joiner_pipe(crtc_state)); else return to_intel_crtc(crtc_state->uapi.crtc); @@ -4453,7 +4445,7 @@ intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); + WARN_ON(intel_dss_is_secondary_joiner_pipe(crtc_state)); drm_property_replace_blob(&crtc_state->hw.degamma_lut, crtc_state->uapi.degamma_lut); @@ -4470,7 +4462,7 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); + WARN_ON(intel_dss_is_secondary_joiner_pipe(crtc_state)); crtc_state->hw.enable = crtc_state->uapi.enable; crtc_state->hw.active = crtc_state->uapi.active; @@ -6396,14 +6388,14 @@ static int intel_atomic_check_config(struct intel_atomic_state *state, for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { if (!intel_crtc_needs_modeset(new_crtc_state)) { - if (intel_crtc_is_joiner_secondary(new_crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(new_crtc_state)) copy_joiner_crtc_state_nomodeset(state, crtc); else intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); continue; } - if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) + if (drm_WARN_ON(&i915->drm, intel_dss_is_secondary_joiner_pipe(new_crtc_state))) continue; ret = intel_crtc_prepare_cleared_state(state, crtc); @@ -6422,7 +6414,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state, if (!intel_crtc_needs_modeset(new_crtc_state)) continue; - if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) + if (drm_WARN_ON(&i915->drm, intel_dss_is_secondary_joiner_pipe(new_crtc_state))) continue; if (!new_crtc_state->hw.enable) @@ -6533,7 +6525,7 @@ int intel_atomic_check(struct drm_device *dev, if (!intel_crtc_needs_modeset(new_crtc_state)) continue; - if (intel_crtc_is_joiner_secondary(new_crtc_state)) { + if (intel_dss_is_secondary_joiner_pipe(new_crtc_state)) { drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); continue; } @@ -7002,7 +6994,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) if ((disable_pipes & BIT(crtc->pipe)) == 0) continue; - if (intel_crtc_is_joiner_secondary(old_crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(old_crtc_state)) continue; /* In case of Transcoder port Sync master slave CRTCs can be @@ -7024,7 +7016,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) if ((disable_pipes & BIT(crtc->pipe)) == 0) continue; - if (intel_crtc_is_joiner_secondary(old_crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(old_crtc_state)) continue; intel_old_crtc_state_disables(state, crtc); @@ -7149,7 +7141,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((modeset_pipes & BIT(pipe)) == 0) continue; - if (intel_crtc_is_joiner_secondary(new_crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(new_crtc_state)) continue; if (intel_dp_mst_is_slave_trans(new_crtc_state) || @@ -7171,7 +7163,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((modeset_pipes & BIT(pipe)) == 0) continue; - if (intel_crtc_is_joiner_secondary(new_crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(new_crtc_state)) continue; modeset_pipes &= ~intel_dss_get_joined_pipe_mask(new_crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 0135c959632d..7bb44cec2015 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -422,7 +422,6 @@ intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915, enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); bool is_trans_port_sync_mode(const struct intel_crtc_state *state); bool is_trans_port_sync_master(const struct intel_crtc_state *state); -bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state); u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state); struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state); bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 0cf0b4223513..ba4d9d23a887 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -27,6 +27,7 @@ #include "intel_dp_link_training.h" #include "intel_dp_mst.h" #include "intel_drrs.h" +#include "intel_dss.h" #include "intel_fbc.h" #include "intel_fbdev.h" #include "intel_hdcp.h" @@ -581,7 +582,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) if (crtc_state->joiner_pipes) seq_printf(m, "\tLinked to 0x%x pipes as a %s\n", crtc_state->joiner_pipes, - intel_crtc_is_joiner_secondary(crtc_state) ? "slave" : "master"); + intel_dss_is_secondary_joiner_pipe(crtc_state) ? "slave" : "master"); intel_vdsc_state_dump(&p, 1, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c index 3ca29afa5422..2b566c07d6fa 100644 --- a/drivers/gpu/drm/i915/display/intel_drrs.c +++ b/drivers/gpu/drm/i915/display/intel_drrs.c @@ -9,6 +9,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_drrs.h" +#include "intel_dss.h" #include "intel_frontbuffer.h" #include "intel_panel.h" @@ -157,7 +158,7 @@ void intel_drrs_activate(const struct intel_crtc_state *crtc_state) if (!crtc_state->hw.active) return; - if (intel_crtc_is_joiner_secondary(crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(crtc_state)) return; mutex_lock(&crtc->drrs.mutex); @@ -189,7 +190,7 @@ void intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->hw.active) return; - if (intel_crtc_is_joiner_secondary(old_crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(old_crtc_state)) return; mutex_lock(&crtc->drrs.mutex); diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c index 1a8bfd8e9247..3f53963ccb6e 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.c +++ b/drivers/gpu/drm/i915/display/intel_dss.c @@ -167,7 +167,7 @@ void intel_dss_enable_uncompressed_joiner(const struct intel_crtc_state *crtc_st u32 dss_ctl1_val = 0; if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) { - if (intel_crtc_is_joiner_secondary(crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(crtc_state)) dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY; else dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY; @@ -191,7 +191,7 @@ void intel_dss_enable_compressed_joiner(const struct intel_crtc_state *crtc_stat } if (crtc_state->joiner_pipes) { dss_ctl1_val |= BIG_JOINER_ENABLE; - if (!intel_crtc_is_joiner_secondary(crtc_state)) + if (!intel_dss_is_secondary_joiner_pipe(crtc_state)) dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; } intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); @@ -282,3 +282,11 @@ bool intel_dss_is_primary_joiner_pipe(const struct intel_crtc_state *crtc_state) return crtc_state->joiner_pipes && crtc->pipe == intel_dss_get_primary_joiner_pipe(crtc_state); } + +bool intel_dss_is_secondary_joiner_pipe(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + return crtc_state->joiner_pipes && + crtc->pipe != intel_dss_get_primary_joiner_pipe(crtc_state); +} diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h index e627582f6883..345e6544db05 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.h +++ b/drivers/gpu/drm/i915/display/intel_dss.h @@ -38,6 +38,7 @@ void intel_dss_get_uncompressed_joiner_pipes(struct intel_display *display, u8 intel_dss_get_joined_pipe_mask(const struct intel_crtc_state *crtc_state); enum pipe intel_dss_get_primary_joiner_pipe(const struct intel_crtc_state *crtc_state); bool intel_dss_is_primary_joiner_pipe(const struct intel_crtc_state *crtc_state); +bool intel_dss_is_secondary_joiner_pipe(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_DSS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 6f85f5352455..bf9a7ae5baa0 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -23,6 +23,7 @@ #include "intel_display_power.h" #include "intel_display_types.h" #include "intel_dmc.h" +#include "intel_dss.h" #include "intel_fifo_underrun.h" #include "intel_modeset_setup.h" #include "intel_pch_display.h" @@ -204,7 +205,7 @@ static u8 get_transcoder_pipes(struct drm_i915_private *i915, if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER) continue; - if (intel_crtc_is_joiner_secondary(temp_crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(temp_crtc_state)) continue; if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder)) @@ -326,7 +327,7 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) { - if (intel_crtc_is_joiner_secondary(crtc_state)) + if (intel_dss_is_secondary_joiner_pipe(crtc_state)) return; crtc_state->uapi.enable = crtc_state->hw.enable; @@ -474,7 +475,7 @@ static bool intel_sanitize_crtc(struct intel_crtc *crtc, } if (!crtc_state->hw.active || - intel_crtc_is_joiner_secondary(crtc_state)) + intel_dss_is_secondary_joiner_pipe(crtc_state)) return false; needs_link_reset = intel_crtc_needs_link_reset(crtc); @@ -733,7 +734,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) struct intel_crtc *secondary_crtc; /* encoder should read be linked to joiner primary */ - WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); + WARN_ON(intel_dss_is_secondary_joiner_pipe(crtc_state)); for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, intel_crtc_joiner_secondary_pipes(crtc_state)) { From patchwork Mon Aug 26 11:15:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B615CC5472E for ; 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X-CSE-ConnectionGUID: pQKPwMt5Rlm8MyCMgq1VIw== X-CSE-MsgGUID: U8rFR4/rTfKN+EwRUBAH6g== X-IronPort-AV: E=McAfee;i="6700,10204,11175"; a="23213591" X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="23213591" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:24 -0700 X-CSE-ConnectionGUID: uusYAX8oTpW+ML6gY3f0Ew== X-CSE-MsgGUID: xQiun1TFRp2UOvgnVtJ0Vg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291438" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:22 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 11/12] drm/i915/display: Move helper to get all secondary pipes Date: Mon, 26 Aug 2024 16:45:25 +0530 Message-ID: <20240826111527.1113622-12-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move the helper to get secondary joiner pipes to intel_dss. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 12 ++---------- drivers/gpu/drm/i915/display/intel_display.h | 1 - drivers/gpu/drm/i915/display/intel_dss.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_dss.h | 1 + drivers/gpu/drm/i915/display/intel_modeset_setup.c | 6 +++--- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 151cd6ad47f1..432d39415689 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -249,14 +249,6 @@ is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) is_trans_port_sync_slave(crtc_state); } -u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state) -{ - if (crtc_state->joiner_pipes) - return crtc_state->joiner_pipes & ~BIT(intel_dss_get_primary_joiner_pipe(crtc_state)); - else - return 0; -} - static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state) { return hweight8(crtc_state->joiner_pipes); @@ -5974,7 +5966,7 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state, } for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, - intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { + intel_dss_get_secondary_joiner_pipes(primary_crtc_state)) { struct intel_crtc_state *secondary_crtc_state; int ret; @@ -6028,7 +6020,7 @@ static void kill_joiner_secondaries(struct intel_atomic_state *state, struct intel_crtc *secondary_crtc; for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, - intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { + intel_dss_get_secondary_joiner_pipes(primary_crtc_state)) { struct intel_crtc_state *secondary_crtc_state = intel_atomic_get_new_crtc_state(state, secondary_crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 7bb44cec2015..dbd56f3bbbba 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -422,7 +422,6 @@ intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915, enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); bool is_trans_port_sync_mode(const struct intel_crtc_state *state); bool is_trans_port_sync_master(const struct intel_crtc_state *state); -u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state); struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state); bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c index 3f53963ccb6e..976fdcac4b55 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.c +++ b/drivers/gpu/drm/i915/display/intel_dss.c @@ -290,3 +290,11 @@ bool intel_dss_is_secondary_joiner_pipe(const struct intel_crtc_state *crtc_stat return crtc_state->joiner_pipes && crtc->pipe != intel_dss_get_primary_joiner_pipe(crtc_state); } + +u8 intel_dss_get_secondary_joiner_pipes(const struct intel_crtc_state *crtc_state) +{ + if (crtc_state->joiner_pipes) + return crtc_state->joiner_pipes & ~BIT(intel_dss_get_primary_joiner_pipe(crtc_state)); + else + return 0; +} diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h index 345e6544db05..ff9195b8fd92 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.h +++ b/drivers/gpu/drm/i915/display/intel_dss.h @@ -39,6 +39,7 @@ u8 intel_dss_get_joined_pipe_mask(const struct intel_crtc_state *crtc_state); enum pipe intel_dss_get_primary_joiner_pipe(const struct intel_crtc_state *crtc_state); bool intel_dss_is_primary_joiner_pipe(const struct intel_crtc_state *crtc_state); bool intel_dss_is_secondary_joiner_pipe(const struct intel_crtc_state *crtc_state); +u8 intel_dss_get_secondary_joiner_pipes(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_DSS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index bf9a7ae5baa0..b6df5fe77be6 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -69,7 +69,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, /* Everything's already locked, -EDEADLK can't happen. */ for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, BIT(pipe) | - intel_crtc_joiner_secondary_pipes(crtc_state)) { + intel_dss_get_secondary_joiner_pipes(crtc_state)) { struct intel_crtc_state *temp_crtc_state = intel_atomic_get_crtc_state(state, temp_crtc); int ret; @@ -258,7 +258,7 @@ static u8 get_joiner_secondary_pipes(struct drm_i915_private *i915, u8 primary_p struct intel_crtc_state *primary_crtc_state = to_intel_crtc_state(primary_crtc->base.state); - pipes |= intel_crtc_joiner_secondary_pipes(primary_crtc_state); + pipes |= intel_dss_get_secondary_joiner_pipes(primary_crtc_state); } return pipes; @@ -737,7 +737,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) WARN_ON(intel_dss_is_secondary_joiner_pipe(crtc_state)); for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, - intel_crtc_joiner_secondary_pipes(crtc_state)) { + intel_dss_get_secondary_joiner_pipes(crtc_state)) { struct intel_crtc_state *secondary_crtc_state; secondary_crtc_state = to_intel_crtc_state(secondary_crtc->base.state); From patchwork Mon Aug 26 11:15:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13777672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EC77C54731 for ; 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X-CSE-ConnectionGUID: OAttTHFiQu+orzFAMTz4DQ== X-CSE-MsgGUID: ef2yDBVkSRuNO1Ys0CGclQ== X-IronPort-AV: E=McAfee;i="6700,10204,11175"; a="23213595" X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="23213595" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:26 -0700 X-CSE-ConnectionGUID: TeaMyZ6+SbmAfkL2fW8r3w== X-CSE-MsgGUID: vOApMv9lRqSpRgPTl6aI0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,177,1719903600"; d="scan'208";a="67291453" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2024 04:14:25 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, suraj.kandpal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 12/12] drm/i915/display: Move intel_joiner_num_pipes to intel dss Date: Mon, 26 Aug 2024 16:45:26 +0530 Message-ID: <20240826111527.1113622-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> References: <20240826111527.1113622-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In line with other joiner helpers, move the function to get the number of joined pipes to intel_dss. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 13 ++++--------- drivers/gpu/drm/i915/display/intel_dss.c | 5 +++++ drivers/gpu/drm/i915/display/intel_dss.h | 1 + 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 432d39415689..51090190bc17 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -249,11 +249,6 @@ is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) is_trans_port_sync_slave(crtc_state); } -static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state) -{ - return hweight8(crtc_state->joiner_pipes); -} - struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); @@ -2308,7 +2303,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state, struct drm_display_mode *mode) { - int num_pipes = intel_joiner_num_pipes(crtc_state); + int num_pipes = intel_dss_get_num_joiner_pipes(crtc_state); if (num_pipes < 2) return; @@ -2372,7 +2367,7 @@ static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state drm_mode_copy(mode, pipe_mode); intel_mode_from_crtc_timings(mode, mode); mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * - (intel_joiner_num_pipes(crtc_state) ?: 1); + (intel_dss_get_num_joiner_pipes(crtc_state) ?: 1); mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); /* Derive per-pipe timings in case joiner is used */ @@ -2392,7 +2387,7 @@ void intel_encoder_get_config(struct intel_encoder *encoder, static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) { - int num_pipes = intel_joiner_num_pipes(crtc_state); + int num_pipes = intel_dss_get_num_joiner_pipes(crtc_state); int width, height; if (num_pipes < 2) @@ -2852,7 +2847,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - int num_pipes = intel_joiner_num_pipes(crtc_state); + int num_pipes = intel_dss_get_num_joiner_pipes(crtc_state); enum pipe primary_pipe, pipe = crtc->pipe; int width; diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c index 976fdcac4b55..cdab6ec5f7a0 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.c +++ b/drivers/gpu/drm/i915/display/intel_dss.c @@ -298,3 +298,8 @@ u8 intel_dss_get_secondary_joiner_pipes(const struct intel_crtc_state *crtc_stat else return 0; } + +int intel_dss_get_num_joiner_pipes(const struct intel_crtc_state *crtc_state) +{ + return hweight8(crtc_state->joiner_pipes); +} diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h index ff9195b8fd92..49fd9d8829ec 100644 --- a/drivers/gpu/drm/i915/display/intel_dss.h +++ b/drivers/gpu/drm/i915/display/intel_dss.h @@ -40,6 +40,7 @@ enum pipe intel_dss_get_primary_joiner_pipe(const struct intel_crtc_state *crtc_ bool intel_dss_is_primary_joiner_pipe(const struct intel_crtc_state *crtc_state); bool intel_dss_is_secondary_joiner_pipe(const struct intel_crtc_state *crtc_state); u8 intel_dss_get_secondary_joiner_pipes(const struct intel_crtc_state *crtc_state); +int intel_dss_get_num_joiner_pipes(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_DSS_H__ */