From patchwork Mon Aug 26 17:22:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Brattlof X-Patchwork-Id: 13778281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6C87C5321D for ; Mon, 26 Aug 2024 17:26:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Mon, 26 Aug 2024 12:22:13 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 26 Aug 2024 12:22:11 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 26 Aug 2024 12:22:11 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47QHMBvb123209; Mon, 26 Aug 2024 12:22:11 -0500 From: Bryan Brattlof Date: Mon, 26 Aug 2024 12:22:07 -0500 Subject: [PATCH v3 1/4] arm64: dts: ti: k3-am62a: add opp frequencies MIME-Version: 1.0 Message-ID: <20240826-opp-v3-1-0934f8309e13@ti.com> References: <20240826-opp-v3-0-0934f8309e13@ti.com> In-Reply-To: <20240826-opp-v3-0-0934f8309e13@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3672; i=bb@ti.com; h=from:subject:message-id; bh=/EX+DTBukK08UXUkfiuLtOXmX5lBgrF3Wye1Fu8yH+s=; b=owNCWmg5MUFZJlNZDbLrxwAAZv///rb7v/U8n0fet/v1d9tnpfry/f3MW273f98u7t7Pv2ewA RsYGKDQGgBo0AGgAAAGQHqA9QDT1NNAAAADQAAPSAD1D1B6Qaaeppp6IH6FDoAABoaaNNBkNDQb U0ZAAbU00B6g9QD1BoDT1AYgPSNqaNqAGag0ZGQZAAaaNCGTIGgNDBNNNDRkBoyaMmEAGQxGRk0 A0yZMmEGTCNAaaYgGQAAGjRpk0AAYN1HHIpPRi6iLk5mSC0VT8DoyzGhLkMFiOcArxqCVdjK3RF tv3wAHnQ4iNO8BerqcM1wzbsdMN5+z0zCAdeMsYC7/lEhIAKJYhzAwEQaLpxO8maE/I/r3Dg9kK ArmOROPCmVrgQhT4rVIR4B95rWBS/wzbPe4Kxxpn93nA4bJPO8WwbPCsVBbNQlCVFHnA3IRrRv2 zJpG9u0D8DF8ghqI5V8Z0olIM3xPcW+m8hlyMG5i4TdBZyG6y+DerIJkSB9shj31zV5JM19dfNK VBI+3uJL2DOi0ErK0MkajHb0w1AK0biwIQXknI8Jn8TgIisZAzQphS0vgXenGrWrP1PMyy6edFG cEohiyzRWCYwOdOUsA2JqH7sb1CrLBbgDBUJ16+H7LpK+HstIRJ7AfwI7YhzQDv2rrqUQYxpqo4 +XPJVf4u5IpwoSAbZdeOA== X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_182225_190867_4C373C18 X-CRM114-Status: GOOD ( 11.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org One power management technique available to the Cortex-A53s is their ability to dynamically scale their frequency across the device's Operating Performance Points (OPP) The OPPs available for the Cortex-A53s on the AM62Ax can vary based on the silicon variant used. The SoC variant is encoded into the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit to only OPP entries the variant supports. A table of all these variants can be found in it's data sheet[0] for the AM62Ax family. Add the OPP table into the SoC's fdti file along with the syscon node to describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect the SoC variant. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 51 +++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index f5ac101a04dfa..0b1dd5390cd3f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -17,6 +17,11 @@ chipid: chipid@14 { reg = <0x14 0x4>; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi index f86a23404e6dd..6c99221beb6bd 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -48,6 +48,8 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; }; cpu1: cpu@1 { @@ -62,6 +64,8 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; }; cpu2: cpu@2 { @@ -76,6 +80,8 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; }; cpu3: cpu@3 { @@ -90,6 +96,51 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; }; }; From patchwork Mon Aug 26 17:22:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Brattlof X-Patchwork-Id: 13778279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29BB3C5472D for ; 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Mon, 26 Aug 2024 12:22:11 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 26 Aug 2024 12:22:11 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47QHMBc3123045; Mon, 26 Aug 2024 12:22:11 -0500 From: Bryan Brattlof Date: Mon, 26 Aug 2024 12:22:08 -0500 Subject: [PATCH v3 2/4] arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry MIME-Version: 1.0 Message-ID: <20240826-opp-v3-2-0934f8309e13@ti.com> References: <20240826-opp-v3-0-0934f8309e13@ti.com> In-Reply-To: <20240826-opp-v3-0-0934f8309e13@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1079; i=bb@ti.com; h=from:subject:message-id; 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Append the 1.4Ghz entry to the OPP table to enable this OPP [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 67faf46d7a35a..a6f0d87a50d8a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -68,6 +68,15 @@ wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + vmain_pd: regulator-0 { /* TPS25750 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; From patchwork Mon Aug 26 17:22:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Brattlof X-Patchwork-Id: 13778277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F188AC5472D for ; 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Mon, 26 Aug 2024 12:22:11 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 26 Aug 2024 12:22:11 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47QHMBrb123048; Mon, 26 Aug 2024 12:22:11 -0500 From: Bryan Brattlof Date: Mon, 26 Aug 2024 12:22:09 -0500 Subject: [PATCH v3 3/4] arm64: dts: ti: k3-am62p: add opp frequencies MIME-Version: 1.0 Message-ID: <20240826-opp-v3-3-0934f8309e13@ti.com> References: <20240826-opp-v3-0-0934f8309e13@ti.com> In-Reply-To: <20240826-opp-v3-0-0934f8309e13@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3884; i=bb@ti.com; h=from:subject:message-id; bh=+t2QsUzWlxD2p+UigAU7JUTDwR8Z1hz/lp225aXq0a8=; b=owNCWmg5MUFZJlNZUhgbKgAAav///7/7/+f/rTbtn5+r2Wcz1d/+xR9tf9/9/w/8qvb83d+wA RmYjNUAGgAAaAAAA0NGgDQ0ABoNAAAyAANANAAyAaGmh6Q9QyDYTU8UQANNDRkMmg0A0GTTJkGm gaGhoAA00MmEDQAaD1GmmmQaGQ9QaDQ0PIjQ0BiBoODKZPUDIeoaNAyBhA9TENAaDTQAYQGmgB6 hoA0eoMgANNGjQ0DQNAAANAAANcKiBEWCgoC3hFu2GGgWdFGeCPIxO6VLNBjD4OBZqw2w/AWwc6 vZHcU4n62ITgMMCPbS2VSCxkUXEDRMvtJtU2WZ9OpgwSR7yd/eNo3V7iFzq0XvediFUQBjiSHnR mX4LViGB4kBbJhj3gHGvkD0+o8EacbX4hP+ETK/Isysp3F8QSqiqfvQzK/G4rjoD2QE6sB2NWqQ 0dDWjC8Ys1N3F18c9e7g9ROMFQIVy+hH2KnDAhg8jhmFWur5BYApKOmIXoXj3MHOK5ygUUV4n/a Oe7/FapxNUSndCwTsq0jqTiHZDC/tbLPpiFvnDDBBniyYJOskUowbz1BLBL+4b7Y6aC+AnJAUiF EMJYAL/F5uyrAPTr5GpAlRisxAxaoMDE72h1AuXCsPQwk2VfSfgZCoiiibs+YDe2+tt/KNjezUa 3/F3JFOFCQUhgbKgA== X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_102217_211676_B6F8F21C X-CRM114-Status: GOOD ( 12.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org One power management technique available to the Cortex-A53s is their ability to dynamically scale their frequency across the device's Operating Performance Points (OPP) The OPPs available for the Cortex-A53s on the AM62Px can vary based on the silicon variant used. The SoC variant is encoded into the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit the OPP entries the SoC supports. A table of all these variants can be found in its data sheet[0] for the AM62Px processor family. Add the OPP table into the SoC's fdti file along with the syscon node to describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect the SoC variant. [0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf Signed-off-by: Bryan Brattlof --- Changes from v2: - Miscellaneous spelling fixes in commit body - Link: https://lore.kernel.org/r/20240823-opp-v2-0-e2f67b37c299@ti.com --- .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 ++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 315d0092e7366..6f32135f00a55 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -20,6 +20,11 @@ chipid: chipid@14 { bootph-all; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi index 41f479dca4555..140587d02e88e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -47,6 +47,7 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 135 0>; }; @@ -62,6 +63,7 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 136 0>; }; @@ -77,6 +79,7 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 137 0>; }; @@ -92,10 +95,54 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 138 0>; }; }; + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; + l2_0: l2-cache0 { compatible = "cache"; cache-unified; From patchwork Mon Aug 26 17:22:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Brattlof X-Patchwork-Id: 13778280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4503C5472D for ; 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Mon, 26 Aug 2024 12:22:11 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47QHMB0i123213; Mon, 26 Aug 2024 12:22:11 -0500 From: Bryan Brattlof Date: Mon, 26 Aug 2024 12:22:10 -0500 Subject: [PATCH v3 4/4] arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry MIME-Version: 1.0 Message-ID: <20240826-opp-v3-4-0934f8309e13@ti.com> References: <20240826-opp-v3-0-0934f8309e13@ti.com> In-Reply-To: <20240826-opp-v3-0-0934f8309e13@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1016; i=bb@ti.com; h=from:subject:message-id; bh=bpOlassBoRg3W4gbLK1G5G0YGPD63Zsyvt4g9z263Eo=; b=owNCWmg5MUFZJlNZxCdgMgAAaH///37/vj//3Tf3z1fsdS33z6pvaN/+Odvv149/jB3cwc6wA RtlB2oAekA0BpoNGjR6QGQANNDQBpoDR6gDQANGhkNGj0gaBoND0mINBtCY0xQ5AGg0GQZDQNMI A0yNomJoMmmjIGmjQyBkMhiNGBNAANBow1AMTIaaZGIhkyYgaGgNAaPUYmTEGRkNNGhiBiaYQaY gDIABtCBkGRpiaZA0MIAZBgOHcyiHXlROfJTC5KLGLrAAS4PSIOPLAz0zIdySGdgBNh6UckgAtR 7+gTLmnZcTCu74R9Sy840F6XeALnybi9+ENp5t79cRMsnHrbcy3IcwRum9rN/UB0LKtASJGRwUL UMrRumkyuB0pNNxFXVnMVLNRovrt8dRn4dcR2sCqEg03GQNT6ryYnIaOHkUCSs216AvUBfQqJ2X 3GjPZC3vMWPEUAiHuhQhw2mfBlc4q0apZD07AH76EPDtvqvYjyUfiWKX/Aig04KXR8X1ISHbMU+ dG9p37c48IETmnG7QCXCkdXci4S8OCKce8oTa25JZGbDJCjDDlKudF2zxYQ26+F+/E8me8RgQ+8 tIPDGbg2lfsX6GjVgJnFsTRDAK5abRJTJ0A4OmcglWbGlWDtXWZyhJxXb0F6kLEPiDYBMITJN/b GK/xdyRThQkMQnYDIA= X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_182225_199388_A5FBFA0A X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The AM62Px reference board is capable of supplying 0v85 to the VDD_CORE which allows the Cortex-A53s to operate at 1.4GHz according to chapter 6.6 of the SoC's data sheet[0] . Append the 1.4Ghz entry to the OPP table to enable this frequency [0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index ff65955551a32..ab5d7a5fc6118 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -128,6 +128,15 @@ led-0 { }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + tlv320_mclk: clk-0 { #clock-cells = <0>; compatible = "fixed-clock";