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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a86e548781csm446566b.28.2024.08.26.10.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 10:31:21 -0700 (PDT) From: Claudiu Beznea To: nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 1/3] dt-bindings: clk: at91: Add clock IDs for the slow clock controller Date: Mon, 26 Aug 2024 20:31:14 +0300 Message-Id: <20240826173116.3628337-2-claudiu.beznea@tuxon.dev> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240826173116.3628337-1-claudiu.beznea@tuxon.dev> References: <20240826173116.3628337-1-claudiu.beznea@tuxon.dev> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_103124_484821_C89977DF X-CRM114-Status: GOOD ( 10.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add clock IDs for the slow clock controller. Previously, raw numbers were used (0 or 1) for clocks generated by the slow clock controller. This leads to confusion and wrong IDs were used on few device trees. To avoid this add macros. Signed-off-by: Claudiu Beznea Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/at91.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index 6ede88c3992d..99f4767ff6bb 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -55,4 +55,8 @@ #define AT91_PMC_GCKRDY 24 /* Generated Clocks */ #endif +/* Slow clock. */ +#define SCKC_MD_SLCK 0 +#define SCKC_TD_SLCK 1 + #endif From patchwork Mon Aug 26 17:31:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13778298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4AA8C5472D for ; Mon, 26 Aug 2024 17:34:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=T6d3SxVVUntGvoi8mj5sPmGncnkMXFV/48WyNCD8DSU=; b=nCD2OAuV6Vic5qchKBFqZXnWNr IlpDRQz/9rv+3xg5PcUfPy/T64FocumQFXODNofS9vUaOrz/q91yg7GTn2In53o7h+e6u/kuZOIk4 p8sP3wfg6jhE76tq0zH1TThFAbFjBjm7/19zddIaacl6XB9/0kaf/WMHgVrdphognt3QVYDjds8Rt cD3/+4v1hLmrcI8i4EP3RSq2wEgDcyG5KAf2g3CmmDDNecv8KdFnQ3p/u+H/5/W6fHlKLYSM1Mn2Y OYnQE1DStuoCoiQQtAC7PxU0Q1gupAdEyVnrJ+ZUyjArgAV462Bm/BM5A7KPGBFakd0ARA7q78p27 v5ZzNPGA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sidbg-00000008FCV-3Boo; Mon, 26 Aug 2024 17:34:20 +0000 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sidYt-00000008EE9-0R2a for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2024 17:31:28 +0000 Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-5bf009cf4c0so4840100a12.1 for ; Mon, 26 Aug 2024 10:31:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724693485; x=1725298285; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T6d3SxVVUntGvoi8mj5sPmGncnkMXFV/48WyNCD8DSU=; b=ILAvFMNup/9Ym55E49njl/pQ+CAfWjazv/QERbT+vMjwbdkiMvch4bT6lz7vAysc3l CKFVWkwfkFWyd+UbfpHt2PgZ2GLqwgj82d/OMo4U9lG3tAIiuusI/UyxqUsf+gr0gSMf wIunki5l43H0HarxUQYSS/SPiEztPr8aSUxLMkn6vkNHgeSVIe2YgKcielV1OWiO1xRe d2YUAM9f9LiKPznOzWRJeUaUJvapos6P5sjyukRJHzABZc4e98zUexX/579nIRRKKq6u 4VycKTsEpv0tG+7DQV+kyRHWhICbHT1FEztAm/N5pZDfO7tUBJAyZiEKu9qRhxLCfqV3 tmbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724693485; x=1725298285; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T6d3SxVVUntGvoi8mj5sPmGncnkMXFV/48WyNCD8DSU=; b=H9OeHqsDIsJUu016G6F+TzIFiXhuGVr7OkI5CloTDWaVolN32j9QEOtyhrVY3+skDx Wets/OBsmtSLDxCLQdpSdrayb0FKZCTZZHFYkIsQYclOBeAd9iAv/cH2Qt/NtVHJQvdA iCtlHzeZtl+iHx2V80DH1R86RiBP20rPQK4vGaRWURotvec2tji8naZ0SLQcvLoCIBc+ 0bckxAvsA9ggn7d9pqtlSFqqACvXDfxiZ3SMIqmTRCUmufJ2w6BTjjxfhMSya2+lswQo su/51VjHkQtmkxhL3qkh5DiVaGnE2ZlXf18bUGMCQwjwp3vJeh+DktOX7BHPzx0laymB Oh7w== X-Gm-Message-State: AOJu0Yzz2CbDsJgWcq4Gindhb9c0eWrmkWIcgEF5cCV1QsMvm/idCRXN nRBPYKH+wbWnpxoQKl8me0x3wmxvLb74lGbHqZVpbuP+/4QzkOWQy5gtz1qYdyY= X-Google-Smtp-Source: AGHT+IHiI9MK7LwJswgkZ/FL0mpPIWeqZWfzXau9hCH4FnmMjNmUY2ZaDEh3Ipy7eVyECcjBOCqahA== X-Received: by 2002:a17:907:940b:b0:a86:8368:860a with SMTP id a640c23a62f3a-a86e3a4b1d1mr13656666b.35.1724693484699; Mon, 26 Aug 2024 10:31:24 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a86e548781csm446566b.28.2024.08.26.10.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 10:31:24 -0700 (PDT) From: Claudiu Beznea To: nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 2/3] clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks Date: Mon, 26 Aug 2024 20:31:15 +0300 Message-Id: <20240826173116.3628337-3-claudiu.beznea@tuxon.dev> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240826173116.3628337-1-claudiu.beznea@tuxon.dev> References: <20240826173116.3628337-1-claudiu.beznea@tuxon.dev> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_103127_163883_BB11DC84 X-CRM114-Status: GOOD ( 14.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use the newly introduced macros instead of raw numbers. With this the code is a bit easier to understand. Signed-off-by: Claudiu Beznea Reviewed-by: Alexander Dahl --- drivers/clk/at91/sckc.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 7741d8f3dbee..021d1b412af4 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -12,6 +12,8 @@ #include #include +#include + #define SLOW_CLOCK_FREQ 32768 #define SLOWCK_SW_CYCLES 5 #define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \ @@ -470,7 +472,7 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np) { void __iomem *regbase = of_iomap(np, 0); struct clk_hw_onecell_data *clk_data; - struct clk_hw *slow_rc, *slow_osc; + struct clk_hw *slow_rc, *slow_osc, *hw; const char *xtal_name; const struct clk_hw *parent_hws[2]; static struct clk_parent_data parent_data = { @@ -506,19 +508,19 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np) /* MD_SLCK and TD_SLCK. */ clk_data->num = 2; - clk_data->hws[0] = clk_hw_register_fixed_rate_parent_hw(NULL, "md_slck", - slow_rc, - 0, 32768); - if (IS_ERR(clk_data->hws[0])) + hw = clk_hw_register_fixed_rate_parent_hw(NULL, "md_slck", slow_rc, + 0, 32768); + if (IS_ERR(hw)) goto clk_data_free; + clk_data->hws[SCKC_MD_SLCK] = hw; parent_hws[0] = slow_rc; parent_hws[1] = slow_osc; - clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck", - parent_hws, 2, - &at91sam9x60_bits); - if (IS_ERR(clk_data->hws[1])) + hw = at91_clk_register_sam9x5_slow(regbase, "td_slck", parent_hws, + 2, &at91sam9x60_bits); + if (IS_ERR(hw)) goto unregister_md_slck; + clk_data->hws[SCKC_TD_SLCK] = hw; ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); if (WARN_ON(ret)) @@ -527,9 +529,9 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np) return; unregister_td_slck: - at91_clk_unregister_sam9x5_slow(clk_data->hws[1]); + at91_clk_unregister_sam9x5_slow(clk_data->hws[SCKC_TD_SLCK]); unregister_md_slck: - clk_hw_unregister(clk_data->hws[0]); + clk_hw_unregister(clk_data->hws[SCKC_MD_SLCK]); clk_data_free: kfree(clk_data); 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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a86e548781csm446566b.28.2024.08.26.10.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 10:31:26 -0700 (PDT) From: Claudiu Beznea To: nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 3/3] ARM: dts: microchip: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks Date: Mon, 26 Aug 2024 20:31:16 +0300 Message-Id: <20240826173116.3628337-4-claudiu.beznea@tuxon.dev> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240826173116.3628337-1-claudiu.beznea@tuxon.dev> References: <20240826173116.3628337-1-claudiu.beznea@tuxon.dev> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_103128_939812_6993BB6C X-CRM114-Status: GOOD ( 11.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use the newly introduced macros instead of raw number. With this device tree code is a bit easier to understand. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sam9x60.dtsi | 18 +++++++++--------- arch/arm/boot/dts/microchip/sama7g5.dtsi | 16 ++++++++-------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi index 04a6d716ecaf..eeda277e684f 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -560,7 +560,7 @@ tcb0: timer@f8008000 { #size-cells = <0>; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k SCKC_MD_SLCK>; clock-names = "t0_clk", "slow_clk"; }; @@ -570,7 +570,7 @@ tcb1: timer@f800c000 { #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k SCKC_MD_SLCK>; clock-names = "t0_clk", "slow_clk"; }; @@ -1038,7 +1038,7 @@ hlcdc: hlcdc@f8038000 { compatible = "microchip,sam9x60-hlcdc"; reg = <0xf8038000 0x4000>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k SCKC_TD_SLCK>; clock-names = "periph_clk","sys_clk", "slow_clk"; assigned-clocks = <&pmc PMC_TYPE_GCK 25>; assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; @@ -1313,20 +1313,20 @@ pmc: clock-controller@fffffc00 { reg = <0xfffffc00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; #clock-cells = <2>; - clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clocks = <&clk32k SCKC_TD_SLCK>, <&clk32k SCKC_MD_SLCK>, <&main_xtal>; clock-names = "td_slck", "md_slck", "main_xtal"; }; reset_controller: reset-controller@fffffe00 { compatible = "microchip,sam9x60-rstc"; reg = <0xfffffe00 0x10>; - clocks = <&clk32k 0>; + clocks = <&clk32k SCKC_MD_SLCK>; }; shutdown_controller: poweroff@fffffe10 { compatible = "microchip,sam9x60-shdwc"; reg = <0xfffffe10 0x10>; - clocks = <&clk32k 0>; + clocks = <&clk32k SCKC_MD_SLCK>; #address-cells = <1>; #size-cells = <0>; atmel,wakeup-rtc-timer; @@ -1338,7 +1338,7 @@ rtt: rtc@fffffe20 { compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; reg = <0xfffffe20 0x20>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k 1>; + clocks = <&clk32k SCKC_TD_SLCK>; }; pit: timer@fffffe40 { @@ -1364,14 +1364,14 @@ rtc: rtc@fffffea8 { compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; reg = <0xfffffea8 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k 1>; + clocks = <&clk32k SCKC_TD_SLCK>; }; watchdog: watchdog@ffffff80 { compatible = "microchip,sam9x60-wdt"; reg = <0xffffff80 0x24>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k 0>; + clocks = <&clk32k SCKC_MD_SLCK>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index 17bcdcf0cf4a..2efca9838d69 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -246,7 +246,7 @@ pmc: clock-controller@e0018000 { reg = <0xe0018000 0x200>; interrupts = ; #clock-cells = <2>; - clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clocks = <&clk32k SCKC_TD_SLCK>, <&clk32k SCKC_MD_SLCK>, <&main_xtal>; clock-names = "td_slck", "md_slck", "main_xtal"; }; @@ -254,13 +254,13 @@ reset_controller: reset-controller@e001d000 { compatible = "microchip,sama7g5-rstc"; reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; #reset-cells = <1>; - clocks = <&clk32k 0>; + clocks = <&clk32k SCKC_MD_SLCK>; }; shdwc: poweroff@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; - clocks = <&clk32k 0>; + clocks = <&clk32k SCKC_MD_SLCK>; #address-cells = <1>; #size-cells = <0>; atmel,wakeup-rtc-timer; @@ -272,7 +272,7 @@ rtt: rtc@e001d020 { compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; reg = <0xe001d020 0x30>; interrupts = ; - clocks = <&clk32k 1>; + clocks = <&clk32k SCKC_TD_SLCK>; }; clk32k: clock-controller@e001d050 { @@ -291,14 +291,14 @@ rtc: rtc@e001d0a8 { compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; reg = <0xe001d0a8 0x30>; interrupts = ; - clocks = <&clk32k 1>; + clocks = <&clk32k SCKC_TD_SLCK>; }; ps_wdt: watchdog@e001d180 { compatible = "microchip,sama7g5-wdt"; reg = <0xe001d180 0x24>; interrupts = ; - clocks = <&clk32k 0>; + clocks = <&clk32k SCKC_MD_SLCK>; }; chipid@e0020000 { @@ -312,7 +312,7 @@ tcb1: timer@e0800000 { #size-cells = <0>; reg = <0xe0800000 0x100>; interrupts = , , ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k SCKC_TD_SLCK>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -906,7 +906,7 @@ tcb0: timer@e2814000 { #size-cells = <0>; reg = <0xe2814000 0x100>; interrupts = , , ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k SCKC_TD_SLCK>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; };