From patchwork Tue Aug 27 18:17:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13780003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFC16C5472F for ; Tue, 27 Aug 2024 18:17:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 606F910E3F8; Tue, 27 Aug 2024 18:17:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WvTtHTMk"; dkim-atps=neutral Received: from mail-il1-f178.google.com (mail-il1-f178.google.com [209.85.166.178]) by gabe.freedesktop.org (Postfix) with ESMTPS id A343D10E3F8; Tue, 27 Aug 2024 18:17:34 +0000 (UTC) Received: by mail-il1-f178.google.com with SMTP id e9e14a558f8ab-39d20c4be31so21429925ab.1; Tue, 27 Aug 2024 11:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724782654; x=1725387454; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cgk9ZwZd91vOVt90fIiETgBR9DeXKbUMnWSmPau0W5M=; b=WvTtHTMk69JNtbOmwdF2nmDUGR6KUPOmm1wNZ6SXlJvzrAWMhrM/G24ldiy9k5L+lG 77s3tsRAOuk+0ui5gfMY2e7gn6x8eBNL8T9MKmYRTsy46uWWFak+vsKbyfNyhl7rl2cU ptdblzCXbnOZia47H8Z5a2zJbF0E6a1Cj9nY4nEHwVzbtFMjNfqQL9KfCNUpydS2J+vL e7a6vMPA9Lexnnx899Dm2jpXHMmlurpJUFp7x9lVJ2xhQkE8faMrU/C8llU+IxnWQWIS sv6UcIwGrOhO142iFz3MDACAL2a5eViG2ALv1zt4YgrrDmjj4/pH4Gh4zUvbmQ2www8w gtBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724782654; x=1725387454; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cgk9ZwZd91vOVt90fIiETgBR9DeXKbUMnWSmPau0W5M=; b=WO9MK0it4FO6IGMvHwGVoCLmvJMqHM5ak3ylZ74YfBvuGz2CD8lak57eBZ1SZYXcFI zrM8JUxMdC8CPxHc5tGqjEKNyNdG99VZz3dvf9tMLNB9kGS4g0bNRtxjhkykuDBjmNuB P7HbV+CkTxLuOrQ5ppvfdtirtaIhgP+Hl4i9lPwVqvbY0m8Kj3vnXz5fEMSnNZYG/Zux W1NxNBwTbhp81/6AgBVuTGi7BXODiuNmkUD4pgMjOAwNtGhPfmwd4lc2bpnGU7Sph6TD CbDJibmlfiLRWD4i8noZ9t7bgfS/aKL/FuKQU7+8QW58YJjp1lbNc6eS5alnHYlwfrPV RvrQ== X-Forwarded-Encrypted: i=1; AJvYcCUX4ZO85PNz9xr77TcndeRSP6mOkgcno4/oN9ImpmfTakXFOHiOsWCOjTs2p2Q01I+WavpADSEvKpU=@lists.freedesktop.org, AJvYcCW8QcLTf5eOKM8pmzIwmHca2UPWuMe1O3m55aqKtIAYlbccdzU7h4a/cRqXgD9sjNInwaMjK6slvlng@lists.freedesktop.org X-Gm-Message-State: AOJu0Yzli+XzP/OEtzRgZm0+4Q5s+VloOXeHVBL4WjoSAKllWApFWEbK Pe7w0+IaqwmzqQFRU+gF6WB9VzIewqETlnAIRLZkgM0uCDCFfvzJ X-Google-Smtp-Source: AGHT+IGAgUs1zObwyhF7fTbdtha65n0BhLE2VwyP+bd4hlIhZyKR5Y1ftLH0i1qZ8R2IN6fgpq/FGA== X-Received: by 2002:a05:6e02:1d9b:b0:397:351b:2c0c with SMTP id e9e14a558f8ab-39e3c9c06dfmr170767125ab.17.1724782653624; Tue, 27 Aug 2024 11:17:33 -0700 (PDT) Received: from localhost ([2a00:79e1:2e00:1301:12e9:d196:a1e9:ab67]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9ad6e8e9sm8321211a12.86.2024.08.27.11.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Aug 2024 11:17:32 -0700 (PDT) From: Rob Clark To: iommu@lists.linux.dev Cc: Will Deacon , Robin Murphy , Rob Clark , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER for Qualcomm Adreno GPUs), dri-devel@lists.freedesktop.org (open list:DRM DRIVER for Qualcomm Adreno GPUs), freedreno@lists.freedesktop.org (open list:DRM DRIVER for Qualcomm Adreno GPUs), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v9 4/4] drm/msm: Extend gpu devcore dumps with pgtbl info Date: Tue, 27 Aug 2024 11:17:12 -0700 Message-ID: <20240827181717.187245-5-robdclark@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240827181717.187245-1-robdclark@gmail.com> References: <20240827181717.187245-1-robdclark@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rob Clark In the case of iova fault triggered devcore dumps, include additional debug information based on what we think is the current page tables, including the TTBR0 value (which should match what we have in adreno_smmu_fault_info unless things have gone horribly wrong), and the pagetable entries traversed in the process of resolving the faulting iova. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 ++++++++++ drivers/gpu/drm/msm/msm_gpu.c | 9 +++++++++ drivers/gpu/drm/msm/msm_gpu.h | 8 ++++++++ drivers/gpu/drm/msm/msm_iommu.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/msm/msm_mmu.h | 3 ++- 5 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 1c6626747b98..3848b5a64351 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -864,6 +864,16 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ"); drm_printf(p, " - type=%s\n", info->type); drm_printf(p, " - source=%s\n", info->block); + + /* Information extracted from what we think are the current + * pgtables. Hopefully the TTBR0 matches what we've extracted + * from the SMMU registers in smmu_info! + */ + drm_puts(p, "pgtable-fault-info:\n"); + drm_printf(p, " - ttbr0: %.16llx\n", (u64)info->pgtbl_ttbr0); + drm_printf(p, " - asid: %d\n", info->asid); + drm_printf(p, " - ptes: %.16llx %.16llx %.16llx %.16llx\n", + info->ptes[0], info->ptes[1], info->ptes[2], info->ptes[3]); } drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 3666b42b4ecd..bf2f8b2a7ccc 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -281,6 +281,15 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, if (submit) { int i; + if (state->fault_info.ttbr0) { + struct msm_gpu_fault_info *info = &state->fault_info; + struct msm_mmu *mmu = submit->aspace->mmu; + + msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0, + &info->asid); + msm_iommu_pagetable_walk(mmu, info->iova, info->ptes); + } + state->bos = kcalloc(submit->nr_bos, sizeof(struct msm_gpu_state_bo), GFP_KERNEL); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 1f02bb9956be..82e838ba8c80 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -101,6 +101,14 @@ struct msm_gpu_fault_info { int flags; const char *type; const char *block; + + /* Information about what we think/expect is the current SMMU state, + * for example expected_ttbr0 should match smmu_info.ttbr0 which + * was read back from SMMU registers. + */ + phys_addr_t pgtbl_ttbr0; + u64 ptes[4]; + int asid; }; /** diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 2a94e82316f9..3e692818ba1f 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -195,6 +195,28 @@ struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu) return &iommu->domain->geometry; } +int +msm_iommu_pagetable_walk(struct msm_mmu *mmu, unsigned long iova, uint64_t ptes[4]) +{ + struct msm_iommu_pagetable *pagetable; + struct arm_lpae_io_pgtable_walk_data wd = {}; + + if (mmu->type != MSM_MMU_IOMMU_PAGETABLE) + return -EINVAL; + + pagetable = to_pagetable(mmu); + + if (!pagetable->pgtbl_ops->pgtable_walk) + return -EINVAL; + + pagetable->pgtbl_ops->pgtable_walk(pagetable->pgtbl_ops, iova, &wd); + + for (int i = 0; i < ARRAY_SIZE(wd.ptes); i++) + ptes[i] = wd.ptes[i]; + + return 0; +} + static const struct msm_mmu_funcs pagetable_funcs = { .map = msm_iommu_pagetable_map, .unmap = msm_iommu_pagetable_unmap, diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index 88af4f490881..96e509bd96a6 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -53,7 +53,8 @@ static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent); int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr, - int *asid); + int *asid); +int msm_iommu_pagetable_walk(struct msm_mmu *mmu, unsigned long iova, uint64_t ptes[4]); struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu); #endif /* __MSM_MMU_H__ */