From patchwork Wed Aug 28 06:55:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bo Gan X-Patchwork-Id: 13780774 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B26871448E6; Wed, 28 Aug 2024 06:55:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724828124; cv=none; b=eq8DJ3FLos9BeRrcIIMVjC/ClUhtqdfe+VMgBHkrBFCJTJlEsRnbAec/DR+iKtqbnRqOk2mieeoQRQ3a0S5anBjeQg26WDJ1RJIPPOEHnafsEAP+bLBDw5LlgTlkfp1AMauN4IdITyrfrv03xCzG1OPbrVsLhQHe4jhVIAGevwM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724828124; c=relaxed/simple; bh=lFi2UpPJvbtKNqXqipYQyNiuOvlu0Ij1SrfqooWu3fA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uF4E1+8KFKtmS5CR6wnqSa3+Zg7ZDkp1MKEVJj0CqAc2IAHX7o+k9Z7DyOFJWYtak5RMTN9cLnGQOkqWRSzuQlGbBslXX0KrVCCJYSP1U0vQc7qqrVYvmIOTk36aUYJjza+iFRuDrFYl1Vi94SluKNXBrcOfICU437kH53JCDx0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=W54WTXpj; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="W54WTXpj" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-1fec34f94abso65984635ad.2; Tue, 27 Aug 2024 23:55:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724828122; x=1725432922; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6ROqg56FyItnNUDdC6ELchQJJpYcKYxLCDK9KVx4Stg=; b=W54WTXpjQerjPiKTyAq5ipxrw4vHt2fbmXULzPqHOa22DNhTAoSu2X5IRYvwNqQ65E wo3E42fI0DzYAxqSTi1ifne5Q+Zu1GuuJWxYSRHXOZLh+rlN96O36SYJ2rg06zLUIGSg bBgHJ/iOmHSg5L8UtWPcXXV94mtOZ3VLSDJWNJuGYg3cZvC+CRl+V/0DdNg1GRgd4wSy /m1X5FaXKQOaQXItR2O71kKQWkcnIY2U1DDcAs82W9si3p8e4y69T+XYTerwr+IoHsDt h3lVuHOAi4kQyPWSF+PiNaQZSbwD+sOEzjjt//43RgUyngWWThcG+hLtgOfpwGxAJxNd DGwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724828122; x=1725432922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6ROqg56FyItnNUDdC6ELchQJJpYcKYxLCDK9KVx4Stg=; b=p5wMb243JPz8FJ6TUHtvaF+erqFmnl7u183tbHLhyLYKK66QwYgs+toUxj3ViwNNth qHEoKd2QxvAON0qYdXnO3+9Wnz+EGg8/ojCkeZRRtwWyfn7DeMcHXSj+dmQRwKti/0Re 31u3bAWiTvXKOzjJFteZlWR8qgc5QqFR2syOhjxpl2/0O8yE6j5L8skTKcU9uZ/Kpnrx 2HUkksklCfZNNW3jyPBrmd9jmlzn5kDZc5iaK4yEo+SWTy6S2C1Ktoc59tJWT06eddlB Yrk9C5feIN3Pyck+4NecpKUJ4J6yTpYo0ri4WpmX7WIoeUpGA6JPg5sO5Ni1hydjvopI VO6g== X-Forwarded-Encrypted: i=1; AJvYcCUceKBO1sijdHIEtNOWa1XookknjTtVCQnfdBb+4wux1LmSKNUYmwtxHxVQJySHVKdq9ylxyOHKhMAJAZHg@vger.kernel.org, AJvYcCX+oCF7IFDdFkzDnIxnUom78uEOXkd9JZDBA+VrQcnIql5xYbAaDYajWUh/w2jnDj58T4tLjD57SgM=@vger.kernel.org X-Gm-Message-State: AOJu0YwN+pc8rfhcDSNbRTr8EhRQE9chombxrfJYVkoPjLWCIFniiewY FK+cV+vD/tIgw1jzBSRZEbx8jILbJT+C7JpveM7Zg4wdyeeitpLo X-Google-Smtp-Source: AGHT+IHyK9Bwbr9j/dan60lKEiq/HvBRavSYzYIR//sllCCG1mgrUDVgkeTETlOetRIPEotRmP5cOA== X-Received: by 2002:a17:902:aa04:b0:202:4b99:fd27 with SMTP id d9443c01a7336-2039e4ef20amr113649585ad.51.1724828121819; Tue, 27 Aug 2024 23:55:21 -0700 (PDT) Received: from m91p.airy.home ([172.92.174.232]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20385607f94sm92816005ad.182.2024.08.27.23.55.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Aug 2024 23:55:21 -0700 (PDT) From: Bo Gan To: zong.li@sifive.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Pragnesh.patel@sifive.com, aou@eecs.berkeley.edu, erik.danie@sifive.com, hes@sifive.com, mturquette@baylibre.com, palmer@dabbelt.com, palmerdabbelt@google.com, paul.walmsley@sifive.com, pragnesh.patel@openfive.com, sboyd@kernel.org, schwab@linux-m68k.org, yash.shah@sifive.com Subject: [PATCH 1/3] dt-bindings: reset: sifive: add fu540/fu740 reset indexes Date: Tue, 27 Aug 2024 23:55:18 -0700 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add bindings for FU540/FU740 clock/reset controller. The header is taken from the same path in U-Boot with macros renamed to have FU540/740 prefix. Signed-off-by: Bo Gan --- include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++ include/dt-bindings/reset/sifive-fu740-prci.h | 19 +++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h new file mode 100644 index 000000000000..dbaf602262d2 --- /dev/null +++ b/include/dt-bindings/reset/sifive-fu540-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Sifive, Inc. + * Author: Sagar Kadam + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define FU540_PRCI_RST_DDR_CTRL_N 0 +#define FU540_PRCI_RST_DDR_AXI_N 1 +#define FU540_PRCI_RST_DDR_AHB_N 2 +#define FU540_PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define FU540_PRCI_RST_RSVD_N 4 +#define FU540_PRCI_RST_GEMGXL_N 5 + +#endif diff --git a/include/dt-bindings/reset/sifive-fu740-prci.h b/include/dt-bindings/reset/sifive-fu740-prci.h new file mode 100644 index 000000000000..74d60ca9f1df --- /dev/null +++ b/include/dt-bindings/reset/sifive-fu740-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2020-2021 Sifive, Inc. + * Author: Pragnesh Patel + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define FU740_PRCI_RST_DDR_CTRL_N 0 +#define FU740_PRCI_RST_DDR_AXI_N 1 +#define FU740_PRCI_RST_DDR_AHB_N 2 +#define FU740_PRCI_RST_DDR_PHY_N 3 +#define FU740_PRCI_RST_PCIE_POWER_UP_N 4 +#define FU740_PRCI_RST_GEMGXL_N 5 +#define FU740_PRCI_RST_CLTX_N 6 + +#endif From patchwork Wed Aug 28 06:55:19 2024 Content-Type: text/plain; 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Signed-off-by: Bo Gan --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 6150f3397bff..a2c09033a9ed 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -4,6 +4,7 @@ /dts-v1/; #include +#include / { #address-cells = <2>; @@ -358,7 +359,7 @@ pcie@e00000000 { clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; pwren-gpios = <&gpio 5 0>; reset-gpios = <&gpio 8 0>; - resets = <&prci 4>; + resets = <&prci FU740_PRCI_RST_PCIE_POWER_UP_N>; status = "okay"; }; }; From patchwork Wed Aug 28 06:55:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bo Gan X-Patchwork-Id: 13780776 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0854B158A33; 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Tue, 27 Aug 2024 23:55:25 -0700 (PDT) Received: from m91p.airy.home ([172.92.174.232]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20385607f94sm92816005ad.182.2024.08.27.23.55.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Aug 2024 23:55:24 -0700 (PDT) From: Bo Gan To: zong.li@sifive.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Pragnesh.patel@sifive.com, aou@eecs.berkeley.edu, erik.danie@sifive.com, hes@sifive.com, mturquette@baylibre.com, palmer@dabbelt.com, palmerdabbelt@google.com, paul.walmsley@sifive.com, pragnesh.patel@openfive.com, sboyd@kernel.org, schwab@linux-m68k.org, yash.shah@sifive.com Subject: [PATCH 3/3] clk: sifive: prci: Add release_reset hooks for gemgxlpll/cltxpll Date: Tue, 27 Aug 2024 23:55:20 -0700 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This patch adds the release_reset hook interface to __prci_wrpll_data. During clock enablement, the function (if present) will be called after PLL registers are configured. It aligns the logic to the driver in u-boot. When there's a previous bootloader stage, such as u-boot, it usually enables the gemgxlpll clock when trying to PXE/network boot. The kernel boots fine, but we should not depend on it being our previous stage, and the logic within: a. We (linux) can get directly invoked by firmware (OpenSBI). b. U-boot doesn't necessarily have to initialize ethernet and enable the clock (when not enabled in CONFIG). When the kernel is the first to initialize gemgxlpll, it must also release the corresponding reset. Otherwise the chip will just hang during macb initialization, and even external JTAG debugger will lose control over the risc-v debug module. (Observed with my Sifive Unmatched Rev.B board) The patch took the dt-bindings and logics directly from u-boot with some additional modifications: - Use __prci_writel after __prci_readl to have barrier semantic. U-boot has the strong version of readl/writel, but linux has the relaxed ones. - Use pd->reset.rcdev.ops to access the reset regs. - Split reset bindings for FU540/FU740 and use them directly, instead of looking it up through reset-names. Signed-off-by: Bo Gan --- drivers/clk/sifive/fu540-prci.h | 16 ++++++++++++++++ drivers/clk/sifive/fu740-prci.h | 31 +++++++++++++++++++++++++++++++ drivers/clk/sifive/sifive-prci.c | 23 +++++++++++++++++++++++ drivers/clk/sifive/sifive-prci.h | 8 ++++++++ 4 files changed, 78 insertions(+) diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h index e0173324f3c5..9d2ca18f47a4 100644 --- a/drivers/clk/sifive/fu540-prci.h +++ b/drivers/clk/sifive/fu540-prci.h @@ -23,9 +23,24 @@ #include #include +#include #include "sifive-prci.h" +/** + * sifive_fu540_prci_ethernet_release_reset() - Release ethernet reset + * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg + * + */ +static void sifive_fu540_prci_ethernet_release_reset(struct __prci_data *pd) +{ + /* Release GEMGXL reset */ + pd->reset.rcdev.ops->deassert(&pd->reset.rcdev, FU540_PRCI_RST_GEMGXL_N); + + /* Procmon => core clock */ + sifive_prci_set_procmoncfg(pd, PRCI_PROCMONCFG_CORE_CLOCK_MASK); +} + /* PRCI integration data for each WRPLL instance */ static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = { @@ -43,6 +58,7 @@ static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = { static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = { .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, + .release_reset = sifive_fu540_prci_ethernet_release_reset, }; /* Linux clock framework integration */ diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h index f31cd30fc395..dd0f54277a99 100644 --- a/drivers/clk/sifive/fu740-prci.h +++ b/drivers/clk/sifive/fu740-prci.h @@ -10,9 +10,38 @@ #include #include +#include #include "sifive-prci.h" +/** + * sifive_fu740_prci_ethernet_release_reset() - Release ethernet reset + * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg + * + */ +static void sifive_fu740_prci_ethernet_release_reset(struct __prci_data *pd) +{ + /* Release GEMGXL reset */ + pd->reset.rcdev.ops->deassert(&pd->reset.rcdev, FU740_PRCI_RST_GEMGXL_N); + + /* Procmon => core clock */ + sifive_prci_set_procmoncfg(pd, PRCI_PROCMONCFG_CORE_CLOCK_MASK); + + /* Release Chiplink reset */ + pd->reset.rcdev.ops->deassert(&pd->reset.rcdev, FU740_PRCI_RST_CLTX_N); +} + +/** + * sifive_fu740_prci_cltx_release_reset() - Release cltx reset + * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg + * + */ +static void sifive_fu740_prci_cltx_release_reset(struct __prci_data *pd) +{ + /* Release CLTX reset */ + pd->reset.rcdev.ops->deassert(&pd->reset.rcdev, FU740_PRCI_RST_CLTX_N); +} + /* PRCI integration data for each WRPLL instance */ static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = { @@ -30,6 +59,7 @@ static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = { static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = { .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, + .release_reset = sifive_fu740_prci_ethernet_release_reset, }; static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = { @@ -49,6 +79,7 @@ static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = { static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = { .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, + .release_reset = sifive_fu740_prci_cltx_release_reset, }; /* Linux clock framework integration */ diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index caba0400f8a2..ae8055a84466 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -249,6 +249,9 @@ int sifive_prci_clock_enable(struct clk_hw *hw) if (pwd->disable_bypass) pwd->disable_bypass(pd); + if (pwd->release_reset) + pwd->release_reset(pd); + return 0; } @@ -448,6 +451,26 @@ void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd) r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ } +/* + * PROCMONCFG + */ + +/** + * sifive_prci_set_procmoncfg() - set PROCMONCFG + * @pd: struct __prci_data * PRCI context + * @val: u32 value to write to PROCMONCFG register + * + * Set the PROCMONCFG register to @val + * + * Context: Any context. Caller must prevent concurrent changes to the + * PROCMONCFG_OFFSET register. + */ +void sifive_prci_set_procmoncfg(struct __prci_data *pd, u32 val) +{ + __prci_writel(val, PRCI_PROCMONCFG_OFFSET, pd); + __prci_readl(pd, PRCI_PROCMONCFG_OFFSET); /* barrier */ +} + /* PCIE AUX clock APIs for enable, disable. */ int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw) { diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 91658a88af4e..825a0aef9fd5 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -210,6 +210,9 @@ /* PROCMONCFG */ #define PRCI_PROCMONCFG_OFFSET 0xf0 +#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24 +#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \ + (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT) /* * Private structures @@ -235,6 +238,7 @@ struct __prci_data { * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address + * @release_reset: fn ptr to code to release clock reset * * @enable_bypass and @disable_bypass are used for WRPLL instances * that contain a separate external glitchless clock mux downstream @@ -246,6 +250,7 @@ struct __prci_wrpll_data { void (*disable_bypass)(struct __prci_data *pd); u8 cfg0_offs; u8 cfg1_offs; + void (*release_reset)(struct __prci_data *pd); }; /** @@ -290,6 +295,9 @@ void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd); void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd); void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd); +/* PROCMONCFG */ +void sifive_prci_set_procmoncfg(struct __prci_data *pd, u32 val); + /* Linux clock framework integration */ long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate);