From patchwork Wed Aug 28 15:46:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781530 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85C241A2572; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859984; cv=none; b=UB1mMpnbm66qwejxZK0uqetg8+w4DuQZsnnAjJLeUrXqXokXeCYmXNqXBKsszu3ea3i7eIlujKzdJvVRsvC6oKOBoOunDaMtvhVQrDNZpXjn8jBBpySZY1EsmuQrOazqpU/+wml3Wz4OLkDE21oiD2/Q4CpfUMo6me8HDjGSsdI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859984; c=relaxed/simple; bh=wkgVf0vCUGHv6W2n+sOka0AmnpoDk4tVlRsVgJuMb+Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hppK+GXIutGVJzfEVvBzXW7kSJ6D44GXUNXvr29ocfEnXeXCpdH2KhCn5xtvqIlHTc1f3hV2Otg3fgLKa1aQIvo1+YZlyDmCeJhkI8Zx6BxyL0gs6z8StBBXsceKMmCcIG15XZvFBFwtFkNyS0j6WTmxWrTikht8fgKkiNVQu8k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TGx2A7iH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TGx2A7iH" Received: by smtp.kernel.org (Postfix) with ESMTPS id 27AE5C4CECC; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724859984; bh=wkgVf0vCUGHv6W2n+sOka0AmnpoDk4tVlRsVgJuMb+Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TGx2A7iH7c0OnzQ0oG7vvsDvZro0UT2830+BsoOysgJef9cQFwDY+8RZCNA2e70oa 0BIhtmMPqc4rUvCK/bQlyBYvieirqQlZiIFp5a8VwzZvrIZcTSFw1Wq/uAcCoclvkH H2Y2GWf9Vft+zo8zDGjEACOSgcHCuWZc5lfttCTZKpNUukALlgLmTqB4ks/3nmgmC+ 566stUL/tacvtZqQQ6hG6gbb/EH/0wJPt6DGZTPF3TNm6qglIfUO+7FAknYv1eHqft N1Drc3+dJf1DqyazGsm554w7QOop1j6AtJ4Zn5rxpIw86fLUWNFuBpEDcHOByGVzy9 nliiCPAAliJ9g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13708C5B55E; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 28 Aug 2024 21:16:11 +0530 Subject: [PATCH v4 01/12] PCI: qcom-ep: Drop the redundant masking of global IRQ events Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-pci-qcom-hotplug-v4-1-263a385fbbcb@linaro.org> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1288; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=dIwxxT9MwJPav4RVeIZrg0i1F93yyMgBj6gEWSQjRyU=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZKTql9/9UmlcG+Npy4IRg4LA68vHTpVm2b0 w8p9An1P6mJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GSgAKCRBVnxHm/pHO 9b3mB/9sX+pg62jn7h5KxdyPMuPEU+Ut3hxhl94VOzC5toY93fuBpVtHvcMpMA5ZNa2cb19bMu7 hu8fmadaUbbw5pZZsbcELIzNHLV43sKlxdW21EIWnVFBg1QCN2ri4S9zl+nKb7QdVyY3xPiTsHM Lf3K9p6wDZ+oR5Dlea+vnRrmF8tk3j0EUqYWoxMrzXNHNkw9+I/uMsuvTLQIp4W9mJoL38gR0Bq kSkdLDivlXUmnFhxHI+6n9qTHHuVhswjpl/+5DZe2kVcz/830JDPmL96x38aw2GE/mvdRYtHEXP RaPCocE5msPu6L9J+oUja0z7O2OSu2niy/ebgpRhccP3ZUJN X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Once the events are disabled in PARF_INT_ALL_MASK register, only the enabled events will generate global IRQ. So there is no need to do the masking again in the IRQ handler, drop it. If there are any spurious IRQs getting generated, they will be reported using the existing dev_err() in the handler. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 236229f66c80..972a90eba494 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -647,11 +647,9 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) struct dw_pcie *pci = &pcie_ep->pci; struct device *dev = pci->dev; u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); - u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); u32 dstate, val; writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); - status &= mask; if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { dev_dbg(dev, "Received Linkdown event\n"); From patchwork Wed Aug 28 15:46:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781529 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85BBE83A18; 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a=openpgp-sha256; l=1256; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=B8RUdvVv9QEg4h2fDtSWIh3luhRVOKTDULQMHpO/Rk0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZLNt9QNPKv9NKAKbZ5eVVEDlJxVPTsCl4yZ H4jVagxg8KJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GSwAKCRBVnxHm/pHO 9cEpB/4hP+YKCmtIoOu2Hobc2nRJn8ozN5UY9byuFg1YQ5A1UEpxS1qIj/AsDmQdV9VTq5uHzGM 328jQY5jYgixBeIhqP4j1hMIWYRj1u/IsKn0n+dIuIU3dG6LE/YZ7nEKXToBSR72kQDRqO59alz WzXQTeR8g87j1LgD4ZjW61UaFEEWMFrDZFHezITn8NV9Oy0lbwJRaV7QDzlVgpuIWPkP2a7Kzhl dc2+VD7cLBgch/22b8vPvycHUyVl+UzorHJhFDRkSBx8eu7jpX78UD738y9xO7ESP5/Z9JwJNKC ucR+cweFjvWOdffPpzPYLz3GBumFwjJcJEGsVOy2gwP8c/UG X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Current error message just prints the contents of PARF_INT_ALL_STATUS register as if like the IRQ event number. It could mislead the users. Reword it to make it clear that the error message is actually showing the interrupt status register to help debug spurious IRQ events. While at it, let's also switch over to dev_WARN_ONCE() so that any IRQ storm won't flood the kernel log buffer. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 972a90eba494..0bb0a056dd8f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -679,7 +679,8 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) dw_pcie_ep_linkup(&pci->ep); pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; } else { - dev_err(dev, "Received unknown event: %d\n", status); + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", + status); } return IRQ_HANDLED; From patchwork Wed Aug 28 15:46:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781533 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EDC81A2C20; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859984; cv=none; b=AQBs+JqsdwNaiSVEpgx27RTju6cmXnx9/a5bK1wcKAcuk2am7i2c2qekeQB3OXax/qDFzOpFZwLXulzZzEyP6YDQAQS/6BdtCKWtoBhtA6d8Vh2rW7CqBH7F6Jk5b/bao+x8z08ZfEoD6imiBp6OqijLDp0OJ3CYVB2WI5f2KH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859984; c=relaxed/simple; bh=Dynz9QHhPHZXKKO8GD6i2AnmK4GVgprdx9YpUpdCd88=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I55X1T8b/h+GIbFnrzBzFOxJmxw/gsi42Ee7wHxpTifP1L5y1b8bW774PEevXHuRaprT1fOOxHPWL42uI7J98+9qunIZ6M9ELWVXQ3AlhO8uWuXKQW608UCN/tKOdSoBkvjq+GAExPkGz9g1WxouYHXPTJg8aYw3/ASKd37f+7s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F4Z4rbfF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F4Z4rbfF" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4DB6AC4CECE; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724859984; bh=Dynz9QHhPHZXKKO8GD6i2AnmK4GVgprdx9YpUpdCd88=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=F4Z4rbfFbsYLAEqCjFwS63fu1HWvCe5kXa1Ylq2xDV1rbs92LDmR/3+Uk2A9SePNl NwHmWsdNIPGQioyz2NrocKh3Myc6dF+MeovRBlXg/sHyACGGiBZngZSzyd9Hz4Y98i zTHqSmQ3qjvOQSlyKNT9xDQQkR+cutf2oKnB2maHxmJBh95ubA4OmlP439SCrkbN/J lZaW1J23nAEMsNHEYyFN4o41kxtWWXzQrT5PINQt+Eg2tDou+MG4W9GHLTk0UrEy+V 2UAZVqsDIXKuIEt5Uk4JUisaUGAz0ZXNYoYZvN1chNE6YJ+1IG8RiVC+XcJQpHrxTe 26L6z+75OYPJQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 374A6C61DB8; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 28 Aug 2024 21:16:13 +0530 Subject: [PATCH v4 03/12] dt-bindings: PCI: pci-ep: Update Maintainers Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-pci-qcom-hotplug-v4-3-263a385fbbcb@linaro.org> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1035; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=5QyilnsJ9fmtdU7GTZXO3WdPGs0Omyndpvk9fplsO9U=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZL9jhf9luAKQ8qfWImj9qozgYiGeIAlxwGL prt2m7x4peJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GSwAKCRBVnxHm/pHO 9T1+CACHbI2AivhKTRkze2MUArBxKQMu0jB/2dJ5a9eEid1AW1bg1voHlMvfKVnfrBW/PkvFf+1 bd6g/ZBNzp1wu1vLZKCMmZU/jhNBOdb1ANYCE0hYmHd4VvBBO2tbPpPcjBcbicni6Jkf78JqcH9 ssFKzRDcMViCUF/0Afu02ovq4o9PQTptUGVYksvd/pzlPLQlE1ndFgIvWvnzxua8xuz5ix29ceA giFSwuEkggtV0xcbedZUKkZmhO74SihSSYVRA4ElnStGan9MiZX4kl5BJj/Vq6jFvSfh5Gk8mR7 DAei/rpgIHWqKfTpNlBNV517jJakADUbRc+D2XOn/HPgwI4g X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Kishon's TI email ID is not active anymore, so use his korg ID. Also, since I've been maintaining the PCI endpoint framework, I'm willing to maintain the DT binding as well. So add myself as the Co-maintainer. Acked-by: Rob Herring (Arm) Signed-off-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index d1eef4825207..0b5456ee21eb 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -10,7 +10,8 @@ description: | Common properties for PCI Endpoint Controller Nodes. maintainers: - - Kishon Vijay Abraham I + - Kishon Vijay Abraham I + - Manivannan Sadhasivam properties: $nodename: From patchwork Wed Aug 28 15:46:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781532 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ED7C1A2C02; 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a=openpgp-sha256; l=2076; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=gFM57NfjI22HI5zO2G4ZyvVdTIrBmxWoCkDYpg/zh4Q=; b=owGbwMvMwMUYOl/w2b+J574ynlZLYkg77+b9qPD0zoTmjt55705zP/3VGWERKqNUMP9ExrVHd Z3c/vNOdzIaszAwcjHIiimypC911mr0OH1jSYT6dJhBrEwgUxi4OAVgIimZHAzdekYzIpiikz8X 1a5cw84yuXSRRtFuo1gOe/6+g1/OqoXs9f9b9rHRWT0skqXteknqmp/KSg2dDzPCeGt5wtl+FCw Ij27vi9kns9r2jopQk/ySEPmZHrs/2n/745YR2quQ8+924sx9u6+4fv/0qHB+MfPPFX8tctrNrl Wl+/R2T+H7W6OX98Bs9nzj1lOvbhk35IqX9B4or3XurmLfnbH+75VQV69Gsa1aqRbOm9JPbf6z/ ajTD86pW2vly2xKpvHIH+MPPXbTPuB3sm+g0cO/8Uovp+0M7tI5K13IzFv4y931IKu993S/D8dt 7739za4aKdAwrWLjglJeeWYVZt3HScs+hkie1pRbft0FAA== X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Devicetrees can specify the domain number based on the actual hardware instance of the PCI endpoint controllers in the SoC. Reviewed-by: Rob Herring (Arm) Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 11 +++++++++++ Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 1 + 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index 0b5456ee21eb..f75000e3093d 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -42,6 +42,17 @@ properties: default: 1 maximum: 16 + linux,pci-domain: + description: + If present this property assigns a fixed PCI domain number to a PCI + Endpoint Controller, otherwise an unstable (across boots) unique number + will be assigned. It is required to either not set this property at all + or set it for all PCI endpoint controllers in the system, otherwise + potentially conflicting domain numbers may be assigned to endpoint + controllers. The domain number for each endpoint controller in the system + must be unique. + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 46802f7d9482..1226ee5d08d1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -280,4 +280,5 @@ examples: phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; }; From patchwork Wed Aug 28 15:46:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781536 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D61841A38FC; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V+gTKry5" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6C1CEC4CEDB; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724859984; bh=xZou4yYTmrNODLhCzXW2Q/Fu7bpHNuL+kgj7Jhe8ZXU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=V+gTKry5Ve807aOn5WR479TpGgrA1NSOdZgvx4Vi0r90t5+1Umnrsi+oiipHsaZBQ U0FbAHnEBM3KsoQQDApFhBnze8OrzkBNyGoVrU08xgcFqEcLZQe3lApLUw9xqcZowt 247Y2azLLa8jLY3v+95JVRsxRAWXCn+Dbd75cw2WRMUOaxBNfSZjpQR109htP371Uj uoeA12h5pILt3UP3xD5cPxqPsTw2tJPnOzws8ag0yossyiGKxFeVhaJ+jCMu6TEc4n JuPWyYewxta6PkC0qMAjWCgQWxFGZVw09f0SxQxGg0W340dq+v1BEHygc5r1KShRZo avRUtCTjB3wVA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61936C63685; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 28 Aug 2024 21:16:15 +0530 Subject: [PATCH v4 05/12] PCI: endpoint: Assign PCI domain number for endpoint controllers Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-pci-qcom-hotplug-v4-5-263a385fbbcb@linaro.org> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3110; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=5oeMGhfukDvga7v0phuNZcmCcF8YceRyJh0rWzD+y8Y=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZLMf4c60sIeK74cdHIg0yL5hYSc4llzQR4Y atcIdalTDuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GSwAKCRBVnxHm/pHO 9ZNRB/9Nmlg/e7/yWhzNE70DQZ3sD6X3ZNNWNXP3QiZI3eTyxL3sL52VAr8qBP7dYF6gIMvDt+j ZxL/EmnrHNI2IU7/TM4AiL0lwBdf8v8/e1+wX5+eFgdNOy1MuIreVI96czTDDgKC/1XcilPzs1A REas1z53pYxuDsgyOdyiPpNBWgMyNhykp7Xbdy7/noruzAqiZwgu0+cmTp0nQctuMcUbPe6Ke3Q e/IiItuCxWHQz2zy6dkJs7NEsJ3NfgJRTctBK08Eh74STgTM4PTTW0reqkk/haPvpZZn26+gnHV R2zGO1hI06vFFAzao2IbKNm4yQLgJoREtlSnltxo2G9qoDrC X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Right now, PCI endpoint subsystem doesn't assign PCI domain number for the PCI endpoint controllers. But this domain number could be useful to the EPC drivers to uniquely identify each controller based on the hardware instance when there are multiple ones present in an SoC (even multiple RC/EP). So let's make use of the existing pci_bus_find_domain_nr() API to allocate domain numbers based on either Devicetree (linux,pci-domain) property or dynamic domain number allocation scheme. It should be noted that the domain number allocated by this API will be based on both RC and EP controllers in a SoC. If the 'linux,pci-domain' DT property is present, then the domain number represents the actual hardware instance of the PCI endpoint controller. If not, then the domain number will be allocated based on the PCI EP/RC controller probe order. If the architecture doesn't support CONFIG_PCI_DOMAINS_GENERIC (rare), then currently a warning is thrown to indicate that the architecture specific implementation is needed. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/endpoint/pci-epc-core.c | 14 ++++++++++++++ include/linux/pci-epc.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 84309dfe0c68..085a2de8b923 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -838,6 +838,10 @@ void pci_epc_destroy(struct pci_epc *epc) { pci_ep_cfs_remove_epc_group(epc->group); device_unregister(&epc->dev); + +#ifdef CONFIG_PCI_DOMAINS_GENERIC + pci_bus_release_domain_nr(NULL, &epc->dev); +#endif } EXPORT_SYMBOL_GPL(pci_epc_destroy); @@ -900,6 +904,16 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, epc->dev.release = pci_epc_release; epc->ops = ops; +#ifdef CONFIG_PCI_DOMAINS_GENERIC + epc->domain_nr = pci_bus_find_domain_nr(NULL, dev); +#else + /* + * TODO: If the architecture doesn't support generic PCI + * domains, then a custom implementation has to be used. + */ + WARN_ONCE(1, "This architecture doesn't support generic PCI domains\n"); +#endif + ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); if (ret) goto put_dev; diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 85bdf2adb760..8e3dcac55dcd 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -128,6 +128,7 @@ struct pci_epc_mem { * @group: configfs group representing the PCI EPC device * @lock: mutex to protect pci_epc ops * @function_num_map: bitmap to manage physical function number + * @domain_nr: PCI domain number of the endpoint controller * @init_complete: flag to indicate whether the EPC initialization is complete * or not */ @@ -145,6 +146,7 @@ struct pci_epc { /* mutex to protect against concurrent access of EP controller */ struct mutex lock; unsigned long function_num_map; + int domain_nr; bool init_complete; }; From patchwork Wed Aug 28 15:46:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781534 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D49511A38FA; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pn6VBCOZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7EA0BC4CEE2; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724859984; bh=Q0K9d834m1CQs7L6nrAh8i7+sVcfqEywtcVG4UQJkH8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pn6VBCOZbu5cvk64b9UxCl77GJUpXrd5dXmyg25JH+vole0CDMrFBTr4MxfyoOTo1 FxsiFXr4V9QzVlSlGZkJXNWtNLt8esspRkEE/EcZm8FFQTRYKJw+oVJ69yMqbE1CCR L5DSHotG4lp0X8BsG7ghBkEEr+NvPbIr0JuwbKo2xPZ+QDsBoEH0ojzR7yE5Cpg0N/ CZfVcNngJgJSQ6zv0295v8wysEFC5DmxmdoZkbZPEQj9BN3iXSm+DqWGXx+QiFmHLU 6gSyxnZ+Dj4TVR7vNFUnCc3I/qikGtZJHI811N0ty63lcDdYMrzH6JNBbk/mYwsPV5 fkNgH08J2xCkQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74EB2C61DB8; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 28 Aug 2024 21:16:16 +0530 Subject: [PATCH v4 06/12] PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-pci-qcom-hotplug-v4-6-263a385fbbcb@linaro.org> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2506; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=XIcVOnjgniiauSeztC2lx8OOqKBgQWPfU4mlz79I8zw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZMJeRwBKZl9ti5NFbMzFzxx2sLFKYLKVjgX KFkM1P+Yw2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GTAAKCRBVnxHm/pHO 9REAB/sEt58nq25RLnw0HfIv6PjsjV3e48I2L8y+h1KA3Exi5n4IWe+dT2UpnzEYRXAD2ElAAJm /GLyqMRvavA3M+hMAJN+K16Kn2lg2Br5Xa528Kghp51WZIe9nbasUwkQwSGXWyVjlQFFVzitb4M H3c3CbAvSC1ooH7fhhVuu0LLaKXZ+0DwD4f2gHmayoqcGXIGVpgdrNpMQ91llb1NbtCzlsNzoQx i4NLLnDWo53+8rG5LkFRJjTOLrQKGXGi9m7mQz68cnkgXE6EbaLNOXhb5sDRzHn5F4a1R9dU5lE Nfc0uRJt3LI21V+XFwDEtKuylGQMvUIFznOMbv0dLB8QBhe2 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Currently, the IRQ device name for both of these IRQs doesn't have Qcom specific prefix and PCIe domain number. This causes 2 issues: 1. Pollutes the global IRQ namespace since 'global' is a common name. 2. When more than one EP controller instance is present in the SoC, naming conflict will occur. Hence, add 'qcom_pcie_ep_' prefix and PCIe domain number suffix to the IRQ names to uniquely identify the IRQs and also to fix the above mentioned issues. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 0bb0a056dd8f..d0a27fa6fdc8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -711,8 +711,15 @@ static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, struct qcom_pcie_ep *pcie_ep) { + struct device *dev = pcie_ep->pci.dev; + char *name; int ret; + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d", + pcie_ep->pci.ep.epc->domain_nr); + if (!name) + return -ENOMEM; + pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); if (pcie_ep->global_irq < 0) return pcie_ep->global_irq; @@ -720,18 +727,23 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, qcom_pcie_ep_global_irq_thread, IRQF_ONESHOT, - "global_irq", pcie_ep); + name, pcie_ep); if (ret) { dev_err(&pdev->dev, "Failed to request Global IRQ\n"); return ret; } + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d", + pcie_ep->pci.ep.epc->domain_nr); + if (!name) + return -ENOMEM; + pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, qcom_pcie_ep_perst_irq_thread, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "perst_irq", pcie_ep); + name, pcie_ep); if (ret) { dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); disable_irq(pcie_ep->global_irq); From patchwork Wed Aug 28 15:46:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781537 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E97CB1A3BCE; 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a=openpgp-sha256; l=986; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=+Lb2vcF7RPFdOyct+N0+V3AMTmLDYS+SRQY7Fw3HIuE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZM83Z35engVsqec9Qy5XqLnwNrE3yue0oFr R5aI0n2kJ2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GTAAKCRBVnxHm/pHO 9ZQpB/4urQR2QZAmwGp5/dqgmYbmQpFMcVLNKBSE5clsO6sHL7t11dfZG4AGzvrMULZXnV6717K qs9cNsufZRyYLTxFB55wWkQtv71t9YRVEPxcF+LvPaA1v7yDqzcxKTouj5ns2A4/3J1ZQNS7TVG ApV1piB+JCX4nHLpRMBohk9FLJuxiYcxYMFmxeb44g/6McxFxxPMDCjVIq7SHf9hz54oTDvNfzi bjQ2DChgd3UxwTO65qM9FoS5LRvtQDVGIxhy94lHrq8QdizvRwFdxh0kSTD5KGr2d5wfVBVzqwi ZxV6yzDbVtJ7SFIJEgXiLKwVgmH3C0OlqVcez+LACnod1wl9 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX55 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 68fa5859d263..d0f6120b665d 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -437,6 +437,7 @@ pcie_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Wed Aug 28 15:46:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781535 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB9791A3BB8; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DUgvdM3R" Received: by smtp.kernel.org (Postfix) with ESMTPS id B522AC4CEC7; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724859984; bh=I2wSRHaYDVrxwX11GGk6+ukp4VyqQ6OrIa6J7s/t3jQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DUgvdM3Rl5ZbxCGaaOIoONbnLXZrtxo8G+QfwMGpEDp1+hmQPFZ+W3FUEzFjPp/ds U60XHDdKiS20393XTKdHE0WEy/05GzzBCL6RDzRy9O4BVDK7pgQGljzb1Ym4ctrLhr AB/aubhVA2jAkuKr+WzCJ7QvXN29sbsgw59AA1CmaeWQSqt/ncsrxJ+EXJ/cHScMjF X7lh+EVTGpA02MAuiWUmGSD9/wZzq/3SggBktiscynLVsXzbGTHsbfrVq+YyOyjblr ocGqSMHL8poaJJP9S1rV4N6BeuqDwEPpHKUh+t5rkJDEP1gw71gTOtY8e04hsCvCmi hTu8ep/dvzq3w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADCE7C61DB8; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 28 Aug 2024 21:16:18 +0530 Subject: [PATCH v4 08/12] ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-pci-qcom-hotplug-v4-8-263a385fbbcb@linaro.org> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=961; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=4ksb8gQi6XxtqZHvRIfOuO8m7D/GXep6HzglfrtwSCA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZMcCAWuNfIslxrX4tmDNzHiHcwDPbSkkENj sUmCBTArPyJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GTAAKCRBVnxHm/pHO 9bL6B/9rkFj8vlPARTFTa3DZ4FFTrCkpbDbqJHbBLKdXwQzG6jGQIpJ6pzV9klmkPXc9cnN76Wg G4IgIamHddxgW+nfOLgdfuSmTRipWuFz6FUm/xNEVfCE6rqMmrPDCy9rav9eX7wFgZSjwtqdQlL 9g4iOJkPVwrR8GPS1wkQvkIWCiioGJjAkVfs4dtxDsQW+KON2cdEIVIIo5V6MHFGTXzojYGNOwp +/k7/liaYzED6Vp3fPQMgtsCLMhcMWry/Skisr50qTDYafouyj7G+i3VIbFGo9ZdOZotlyy0Se2 cjDdAgN2KXzyZ3ijdfHc4SjqL3dP3HJVpdSTKlFxKm08Ju5L X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX65 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index a949454212e9..fcfec4228670 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -345,6 +345,7 @@ pcie_ep: pcie-ep@1c00000 { max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Wed Aug 28 15:46:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781540 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 356701A4F25; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859985; cv=none; b=phZrqBbQog3CPogQmpcX5lP+mjLH1kL1zeUaWRxNdjyqQloTLdoZeYRQrnMooP/aicSuHJmoWa9G2BZo8uVvHI7Cn9Xv1ddd3yRNOMO73G3ptgOOKu7/72WlFyWmrOvH9+ClwDGHi9rnlgmlmLKxgs8ovS3HkBePSYtTwvoe6MY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859985; c=relaxed/simple; bh=9SpPkeVArnB3rJ4nPZ0WPdvcC8ctAG/YXTHNpaqeYTk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o8ogyt3uuArazzn6n0c4gjRnrAVzX/ejLHBOXOclUXh+3Zl+gMe76k3HppeIY22F6oJyucP+iK+KcuEZMDtO23+6S42TvaNn9/EdcV9LozLkKAfZuR51/wV+x7MbrbfsE6H58UtMu7ANAEKHSAlu0uDGv7mlBqhselkQthSkxbA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iNZpItaS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iNZpItaS" Received: by smtp.kernel.org (Postfix) with ESMTPS id C9ADDC4CEF2; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724859984; bh=9SpPkeVArnB3rJ4nPZ0WPdvcC8ctAG/YXTHNpaqeYTk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=iNZpItaSw5EVogZD9jBh5ya2aq1nbydFMEuY2E3LKtyjjAyFQBCXa8H/w32bwq8w6 vtXF3KC8IgfK3hVA7kBnzKIPaH2H+9Bwu5WR2C/UmN5SvVZnt4XHOp3Jh2l9NheqEt F6Zw67JqWQdkFS3XOZLnrg0X2OFWABM4/psN2W1VLkR1WfofvNCUUNbpZZcBoyKkpZ E8U65LkyCTZeszLb0miy/pspPc0XFeyEYw7ztDmCvoexKGn09DMZgvK48ZipnpuZ3W Rf5S7DeZHQmDvxtBFtRf6MIBMWuhTDx5mWfNYCGeJcZOE3m/UzzEeod2TmzHJMgYM5 KPsAjSNcCYX9A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C088CC63685; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 28 Aug 2024 21:16:19 +0530 Subject: [PATCH v4 09/12] arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-pci-qcom-hotplug-v4-9-263a385fbbcb@linaro.org> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1289; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=YKSy5vPklQvLJA99UbdPy4mFyoiPQChYvArhByAGkpA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZMziJrsXic02yVCJv/8NFMTgDi+58XUKWXX KH3CGTMQB6JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GTAAKCRBVnxHm/pHO 9VDsB/4sVDxMnvqbnlA73pjYq88mhGwkv1J3VCb9j/EKZHqMl10jBYx5MOYbJSW3y25GYwIxIMU qmjz9rqsQWRqRAkhyAkAqNhEEU8xyOdzIGO3gXHngFEVPCi2IgGpZUMDP3bMzDlUOML97HRuQHg kv5M/olxW+ZTsVkVca08HU8zmt7ggk7WUYgpnYRMCpfj0EVg0fspx9BD1yys1RfB+n+JqVqfuM8 M5vzw0E7NHX82HgvT2k4RSBMTfrW4s6hJ2zFWbGm1diGiNdwqYvCUAqoI4LAw+52+zWlxKcSfL+ Ko1Kqu+MadWR11YDjc04z8HXhrzlUEKHgsfwmeVFpEiOjZFz X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SA8775P SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..198b39abde97 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4618,6 +4618,7 @@ pcie0_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; @@ -4775,6 +4776,7 @@ pcie1_ep: pcie-ep@1c10000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <4>; + linux,pci-domain = <1>; status = "disabled"; }; From patchwork Wed Aug 28 15:46:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781541 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 570961AAE1C; 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a=openpgp-sha256; l=2750; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=DyBVQRLO1Cvv6lhUcJR+pkpUwb9nrOEo4mxqLaOumRw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZN73vihZy1iEXaEcTGQKkDZREqQZS/aQCIQ Tp/HiXFbxiJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GTQAKCRBVnxHm/pHO 9f0+B/wK7H1XmDJUhCBbN/HOdnPxMEI0TodYU5qwzRf3wBq/v5DsKb0wHx7u5Rb4FogLmE+qbjI nU77ZbDUQezrMrbsl4V3lbw6d/rG0n9cbTCvUOnD+8IGa2XsCe0YcfO7jGIl8kh1qZiDGOnF2l5 YJuOVQCwPabpmmjZNiQkiNxz9ZqRjquNgxOWb7uziTlelaMEyAf2HPvVJ7HpsklfoHB9UKAIIc7 PGZajtULee1PLbSn3M6FdsGnWLtYiPRQFR6r1dGnj0afaDRjCKf9AjZK45Se79yVqCnEN9MxOkx EtB/ypOK7rC3vrpDjrb1Z0lDviYTaFxx73w5P0LVuqjrMKPL X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPU. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, document it in the binding along with the existing MSI interrupts. Though adding a new interrupt will break the ABI, it is required to accurately describe the hardware. Reviewed-by: Rob Herring (Arm) Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++-- Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 10 ++++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 0a39bbfcb28b..704c0f58eea5 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -21,11 +21,11 @@ properties: interrupts: minItems: 1 - maxItems: 8 + maxItems: 9 interrupt-names: minItems: 1 - maxItems: 8 + maxItems: 9 iommu-map: minItems: 1 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index d8c0afaa4b19..46bd59eefadb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -55,8 +55,8 @@ properties: - const: aggre1 # Aggre NoC PCIe1 AXI clock interrupts: - minItems: 8 - maxItems: 8 + minItems: 9 + maxItems: 9 interrupt-names: items: @@ -68,6 +68,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global operating-points-v2: true opp-table: @@ -149,9 +150,10 @@ examples: , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ From patchwork Wed Aug 28 15:46:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781538 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14EED1A4B81; Wed, 28 Aug 2024 15:46:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859985; cv=none; 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a=openpgp-sha256; l=4505; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=rrwYXBkV1hJCf8Vji/wBdBUFZOTu6YfGKfdoZ3owUQ0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZNFRtuaJhLbwo4ClWO55fuMNfp+WINh0ciI Rvu5i/65eiJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GTQAKCRBVnxHm/pHO 9dRBB/9GM+kkTUeJz/ZOAk6j5LmvLrQkYiEvjbE/9YtkxmUXKFXv557klotlGhVi3Bygc3gfXmm oeDVNTP0ChIxqwhdqkTG4evbHAJ1z5trp9PTl7dyxJluSVETXJqcZ3H6HvMM18qyC0f4ylwHxSh KFbMEPMJZCIF+pWp3/QTGWmubuWH/MWPnMq+4mibpi56jRzqc5jVzsgQuJbB3P1w/EHBx/+wFOW 3teV1EKw+6VIsddGi7GVmyAhY32pqH69wUFP74FVWMyqtUq7kqSA+XaKK1HEQj9FBo49nfJSOtR J5ZALPAoA7rcuZb2tAUPLqn+y4dgtcmue1cG51JYlSMt4HH0 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Historically, Qcom PCIe RC controllers lacked standard hotplug support. So when an endpoint is attached to the SoC, users have to rescan the bus manually to enumerate the device. But this can be avoided by using the Link up event exposed by the Qcom specific 'global_irq' interrupt. Qcom PCIe RC controllers are capable of generating the 'global' SPI interrupt to the host CPUs. The device driver can use this interrupt to identify events such as PCIe link specific events, safety events etc... One such event is the PCIe Link up event generated when an endpoint is detected on the bus and the Link is 'up'. This event can be used to enumerate the PCIe endpoint devices without user intervention. So add support for capturing the PCIe Link up event using the 'global' interrupt in the driver. Once the Link up event is received, the bus underneath the host bridge is scanned to enumerate PCIe endpoint devices. All of the Qcom SoCs have only one rootport per controller instance. So only a single 'Link up' event is generated for the PCIe controller. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 55 +++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 0180edf3310e..a1d678fe7fa5 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -50,6 +50,9 @@ #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 #define PARF_Q2A_FLUSH 0x1ac #define PARF_LTSSM 0x1b0 +#define PARF_INT_ALL_STATUS 0x224 +#define PARF_INT_ALL_CLEAR 0x228 +#define PARF_INT_ALL_MASK 0x22c #define PARF_SID_OFFSET 0x234 #define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_SLV_ADDR_SPACE_SIZE 0x358 @@ -121,6 +124,9 @@ /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ +#define PARF_INT_ALL_LINK_UP BIT(13) + /* PARF_NO_SNOOP_OVERIDE register fields */ #define WR_NO_SNOOP_OVERIDE_EN BIT(1) #define RD_NO_SNOOP_OVERIDE_EN BIT(3) @@ -1488,6 +1494,29 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) qcom_pcie_link_transition_count); } +static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) +{ + struct qcom_pcie *pcie = data; + struct dw_pcie_rp *pp = &pcie->pci->pp; + struct device *dev = pcie->pci->dev; + u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); + + writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); + + if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { + dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); + /* Rescan the bus to enumerate endpoint devices */ + pci_lock_rescan_remove(); + pci_rescan_bus(pp->bridge->bus); + pci_unlock_rescan_remove(); + } else { + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", + status); + } + + return IRQ_HANDLED; +} + static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; @@ -1498,7 +1527,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct dw_pcie_rp *pp; struct resource *res; struct dw_pcie *pci; - int ret; + int ret, irq; + char *name; pcie_cfg = of_device_get_match_data(dev); if (!pcie_cfg || !pcie_cfg->ops) { @@ -1617,6 +1647,27 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d", + pci_domain_nr(pp->bridge->bus)); + if (!name) { + ret = -ENOMEM; + goto err_host_deinit; + } + + irq = platform_get_irq_byname_optional(pdev, "global"); + if (irq > 0) { + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, + qcom_pcie_global_irq_thread, + IRQF_ONESHOT, name, pcie); + if (ret) { + dev_err_probe(&pdev->dev, ret, + "Failed to request Global IRQ\n"); + goto err_host_deinit; + } + + writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); + } + qcom_pcie_icc_opp_update(pcie); if (pcie->mhi) @@ -1624,6 +1675,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) return 0; +err_host_deinit: + dw_pcie_host_deinit(pp); err_phy_exit: phy_exit(pcie->phy); err_pm_runtime_put: From patchwork Wed Aug 28 15:46:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13781539 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29D671A4F10; Wed, 28 Aug 2024 15:46:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859985; cv=none; b=ed4o0fvq0wjC+gPzrDaOS2FU/Ua8VLfmw03rMhtlWnH4iOWyK8a44D+p7/64vJ0cemJiH5V/8lYUtICYsHftVZaykGt2QDQZJnqng6Sbg/LMSVOY/P82ZcfWy0oJ/EFyIYzhO+FTufubIpK4YYhfqmY3KfkSeNM9EGQ4tfNSbGg= ARC-Message-Signature: i=1; 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a=openpgp-sha256; l=2085; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=VT44obotCPUBbxvMUSiK7oaxSibx2Iio+dz6SHI7KhE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZNBNEoQ6DDVkJpBpWEeTqtGnAT1t6acgVxO fhtJqbI0YSJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GTQAKCRBVnxHm/pHO 9ctxCACdpEZvp66AumYcDrmPBiFVKFQOJonvGKpRxJYoNv7ls/TRuhgqFUep1DT3szRCzS0gubk uXfm/jYLELujibLiWaQeu59MZiGPSe57TDrS5pODkUjd9g3/C5gMCvodV6+178X6JB5XDTeNHlt sQIPRitYy/G75mlZ47EF5P55eqsdPVBGeIHa64xxg2bjuKIGHQM3xY2fCsGgpQCfeUIpnPqLcP3 GJrUDvQlV1VED8gF52EeSBZ+2lp0bd3WWrOD+jURXLBZj8NGsMw5sYfIVMDs13F7qz4qAcY4NAx xIWDYCzYmBFKcbhDsVqkyjv2+qHH5kM0xCDkrqqnfzIvTTbv X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPUs. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, add it to the PCIe RC node along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9bafb3b350ff..564b071eb77c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1787,7 +1787,8 @@ pcie0: pcie@1c00000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1795,7 +1796,8 @@ pcie0: pcie@1c00000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1949,7 +1951,8 @@ pcie1: pcie@1c08000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1957,7 +1960,8 @@ pcie1: pcie@1c08000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */