From patchwork Wed Aug 28 16:22:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13781590 Received: from out-186.mta0.migadu.com (out-186.mta0.migadu.com [91.218.175.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B70611A3BA0 for ; Wed, 28 Aug 2024 16:22:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.186 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724862131; cv=none; b=im1Q8BYd2ZtfBB5j322T+hMPLuy82IJQmWy+w1E8tLJXwQwuh+bYL/ueswbfvNBqkEGPu9KR24r5IdqLPL7GfIKRuGv77PpyEmOPWW/O5bbbAOwh7iT1Nw4fYTInYe6GH+ZRHUfGbLFE6TdlAzrpjm/XnOF22KnND/D2R+SNFt4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724862131; c=relaxed/simple; bh=fuoEwOpVumRo8h+UC3R1unaQWJs7YIQYRjDaAgU3tK4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KJmKbWPGdJi8rio3hIGACkFBqH3i72J1fsUGPvyAPe0/NCCJTJCLqeZaBiz/OQgSXgfTCulE3mrRGPt+ZsJSIRiF0A2tdshrhASER/yjmpEfcQP9AL9AkmNN+WKgQOQ62IdH/K4Ox0kfULp6xxXwXr2Vgd+3bIi0t/kUf+yV8WA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=UXhT3XsJ; arc=none smtp.client-ip=91.218.175.186 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="UXhT3XsJ" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1724862126; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8p/IIk0B7Z3/xGeHNl/FhStqLK9xsXc/qtKenXWl9uU=; b=UXhT3XsJTaw2cuprhvneey5UKwSRaeaoSpkgxP0e1QTLcYNp3xqan6/zW0APTi15K48Rpw 1kNZ7DIxMHdsE9lyoahiX1gPoZOXwUg3RjKwk1cnfS6U5IJ8DClVqQKNzBDw7DDbMm6ZHU 5HmLHCRgxQSlAvMnbi8jZICvAwG5gZQ= From: Andrew Jones To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: atishp@rivosinc.com, cade.richard@berkeley.edu, jamestiotio@gmail.com Subject: [kvm-unit-tests PATCH 1/3] riscv: Introduce local_timer_init Date: Wed, 28 Aug 2024 18:22:02 +0200 Message-ID: <20240828162200.1384696-6-andrew.jones@linux.dev> In-Reply-To: <20240828162200.1384696-5-andrew.jones@linux.dev> References: <20240828162200.1384696-5-andrew.jones@linux.dev> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT When Sstc is available make sure that even if we enable timer interrupts nothing will happen. This is necessary for cases where the unit tests actually intend to use the SBI TIME extension and aren't thinking about Sstc at all, like the SBI TIME test in riscv/sbi where we can now remove the initialization. Signed-off-by: Andrew Jones --- lib/riscv/asm/timer.h | 1 + lib/riscv/setup.c | 2 ++ lib/riscv/smp.c | 2 ++ lib/riscv/timer.c | 13 +++++++++++++ riscv/sbi.c | 5 ----- 5 files changed, 18 insertions(+), 5 deletions(-) diff --git a/lib/riscv/asm/timer.h b/lib/riscv/asm/timer.h index b3514d3f6a78..fd12251a3a6b 100644 --- a/lib/riscv/asm/timer.h +++ b/lib/riscv/asm/timer.h @@ -5,6 +5,7 @@ #include extern void timer_get_frequency(void); +extern void local_timer_init(void); static inline uint64_t timer_get_cycles(void) { diff --git a/lib/riscv/setup.c b/lib/riscv/setup.c index 9a16f00093d7..7c4321b1c30f 100644 --- a/lib/riscv/setup.c +++ b/lib/riscv/setup.c @@ -210,6 +210,7 @@ void setup(const void *fdt, phys_addr_t freemem_start) cpu_init(); timer_get_frequency(); thread_info_init(); + local_timer_init(); io_init(); ret = dt_get_bootargs(&bootargs); @@ -276,6 +277,7 @@ efi_status_t setup_efi(efi_bootinfo_t *efi_bootinfo) cpu_init(); timer_get_frequency(); thread_info_init(); + local_timer_init(); io_init(); initrd_setup(); diff --git a/lib/riscv/smp.c b/lib/riscv/smp.c index 4d373e0a29a8..18d0393c0cc2 100644 --- a/lib/riscv/smp.c +++ b/lib/riscv/smp.c @@ -14,6 +14,7 @@ #include #include #include +#include cpumask_t cpu_present_mask; cpumask_t cpu_online_mask; @@ -27,6 +28,7 @@ secondary_func_t secondary_cinit(struct secondary_data *data) __mmu_enable(data->satp); thread_info_init(); + local_timer_init(); info = current_thread_info(); set_cpu_online(info->cpu, true); smp_send_event(); diff --git a/lib/riscv/timer.c b/lib/riscv/timer.c index d78d254c8eca..92826d6ec3fe 100644 --- a/lib/riscv/timer.c +++ b/lib/riscv/timer.c @@ -4,7 +4,11 @@ */ #include #include +#include +#include +#include #include +#include #include void timer_get_frequency(void) @@ -26,3 +30,12 @@ void timer_get_frequency(void) data = (u32 *)prop->data; timebase_frequency = fdt32_to_cpu(*data); } + +void local_timer_init(void) +{ + if (cpu_has_extension(smp_processor_id(), ISA_SSTC)) { + csr_write(CSR_STIMECMP, ULONG_MAX); + if (__riscv_xlen == 32) + csr_write(CSR_STIMECMPH, ULONG_MAX); + } +} diff --git a/riscv/sbi.c b/riscv/sbi.c index 01697aed3457..e8598fe721a6 100644 --- a/riscv/sbi.c +++ b/riscv/sbi.c @@ -258,11 +258,6 @@ static void check_time(void) install_irq_handler(IRQ_S_TIMER, timer_irq_handler); local_irq_enable(); - if (cpu_has_extension(smp_processor_id(), ISA_SSTC)) { - csr_write(CSR_STIMECMP, ULONG_MAX); - if (__riscv_xlen == 32) - csr_write(CSR_STIMECMPH, ULONG_MAX); - } timer_irq_enable(); timer_check_set_timer(false); From patchwork Wed Aug 28 16:22:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13781591 Received: from out-187.mta1.migadu.com (out-187.mta1.migadu.com [95.215.58.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5E9F1A4B70 for ; Wed, 28 Aug 2024 16:22:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724862134; cv=none; b=MKJkoZNQPtpzCle2v7SLEthITmxtg2+bpjaP2t9sep5naaV+Gc36b862tkxAL4iil2Hfd7kcQlElO1RE/P+hRU6ka+uiaHXWPJXPP3PwgFx93Rl2S3tJFDfCIkl4nkSvJfhK2UXl7mK4uQnfLjh+ii3jp0tbN+StGIttPdmy2O4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724862134; c=relaxed/simple; bh=F2DpSpMD1QNHoM5DzFDACUVb55Fqil98VN1tTLFGdNQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q8Tei24uAm8NaRIVCxa94eWNhq8Dc0rQkr1agEWScroF9j1WjndxLM1VaRY7OIvvHaQpMf6lchaU0d9a9Jh395OTPefWbnQ5z6JmZenn4JfxxUbr2vvUYyW4xf3bCtZYSjZ90KFZzsUMcXp0RhoBKDWP9gdWIurWXiIKtjoQMfk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=BYHqWJjT; arc=none smtp.client-ip=95.215.58.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="BYHqWJjT" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1724862129; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NeWC5wTVvl+NXpTbEp9Dir3lwfIZxO0SfLsx56bqwIs=; b=BYHqWJjT1Z28//jQa7QbGLaWAGT6mFDS/wCOE7G13ScAJ1oM0ujtcZK+duQF6vVT09B5QM HXH1uokT/Q8KGuFGFpZ8k2JpaczKcPvag6/+xtATXAulxVpwAsllY17yWSz6py76Puq3Il s/rQ2dH5G1TDpI186kPeMiru9hWYjFM= From: Andrew Jones To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: atishp@rivosinc.com, cade.richard@berkeley.edu, jamestiotio@gmail.com Subject: [kvm-unit-tests PATCH 2/3] riscv: Share sbi_time_ecall with framework Date: Wed, 28 Aug 2024 18:22:03 +0200 Message-ID: <20240828162200.1384696-7-andrew.jones@linux.dev> In-Reply-To: <20240828162200.1384696-5-andrew.jones@linux.dev> References: <20240828162200.1384696-5-andrew.jones@linux.dev> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT Setting timers is a useful thing to do for all types of tests. Not every platform will have Sstc so make the SBI TIME extension available as well. Signed-off-by: Andrew Jones --- lib/riscv/asm/sbi.h | 1 + lib/riscv/sbi.c | 5 +++++ riscv/sbi.c | 13 ++++--------- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h index a864e268437b..4a35cf38da70 100644 --- a/lib/riscv/asm/sbi.h +++ b/lib/riscv/asm/sbi.h @@ -67,6 +67,7 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, void sbi_shutdown(void); struct sbiret sbi_hart_start(unsigned long hartid, unsigned long entry, unsigned long sp); struct sbiret sbi_send_ipi(unsigned long hart_mask, unsigned long hart_mask_base); +struct sbiret sbi_set_timer(unsigned long stime_value); long sbi_probe(int ext); #endif /* !__ASSEMBLY__ */ diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c index 19d58ab73593..07660e422cbb 100644 --- a/lib/riscv/sbi.c +++ b/lib/riscv/sbi.c @@ -44,6 +44,11 @@ struct sbiret sbi_send_ipi(unsigned long hart_mask, unsigned long hart_mask_base return sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, hart_mask, hart_mask_base, 0, 0, 0, 0); } +struct sbiret sbi_set_timer(unsigned long stime_value) +{ + return sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0); +} + long sbi_probe(int ext) { struct sbiret ret; diff --git a/riscv/sbi.c b/riscv/sbi.c index e8598fe721a6..85cb7e589bdc 100644 --- a/riscv/sbi.c +++ b/riscv/sbi.c @@ -35,11 +35,6 @@ static struct sbiret __base_sbi_ecall(int fid, unsigned long arg0) return sbi_ecall(SBI_EXT_BASE, fid, arg0, 0, 0, 0, 0, 0); } -static struct sbiret __time_sbi_ecall(unsigned long stime_value) -{ - return sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0); -} - static struct sbiret __dbcn_sbi_ecall(int fid, unsigned long arg0, unsigned long arg1, unsigned long arg2) { return sbi_ecall(SBI_EXT_DBCN, fid, arg0, arg1, arg2, 0, 0, 0); @@ -198,7 +193,7 @@ static void timer_irq_handler(struct pt_regs *regs) if (timer_info.mask_timer_irq) timer_irq_disable(); else - __time_sbi_ecall(ULONG_MAX); + sbi_set_timer(ULONG_MAX); if (!timer_irq_pending()) timer_info.timer_irq_cleared = true; @@ -217,7 +212,7 @@ static void timer_check_set_timer(bool mask_timer_irq) timer_info = (struct timer_info){ .mask_timer_irq = mask_timer_irq }; begin = timer_get_cycles(); - ret = __time_sbi_ecall(begin + d); + ret = sbi_set_timer(begin + d); report(!ret.error, "set timer%s", mask_test_str); if (ret.error) @@ -268,10 +263,10 @@ static void check_time(void) report_skip("timer irq enable bit is not writable, skipping mask irq test"); timer_irq_disable(); - __time_sbi_ecall(0); + sbi_set_timer(0); pending = timer_irq_pending(); report(pending, "timer immediately pending by setting timer to 0"); - __time_sbi_ecall(ULONG_MAX); + sbi_set_timer(ULONG_MAX); if (pending) report(!timer_irq_pending(), "pending timer cleared while masked"); else From patchwork Wed Aug 28 16:22:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13781592 Received: from out-177.mta0.migadu.com (out-177.mta0.migadu.com [91.218.175.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9861F1A3BA0 for ; Wed, 28 Aug 2024 16:22:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724862135; cv=none; b=ZnvMG9hLb3kLTtIyzM87S5o68+LxzDVWnnuFtkTgMlpi3VFCUht7N4woe8FYoQUp9jUR04Jbs6Genod9JXbYZ4d7qBRL8jcyFbuLEZbjnK2S33tuSHGBjXbiVZmdEi7DuyyERvIlDEpUUilsLhFqYasXj6xMpjovn6HnAWLrbg4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724862135; c=relaxed/simple; bh=+eqc5rKCxMwQx/83edrPN/kBuQx0Y97/SDXlDMV2dVk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QiukeE6ugjTCcLPACy7PMvuaNwmmjBs3kJNgrgDFZWete7q+btYg23zRR1aAsQcOsFnPsbzktm2TEQtENe859jilGRxudXORqiVjGQjhcZDN0ldx+ls9WKly2QjLJCc2EB2AxquD/W6crkyPxrhPJ25lpIaYJxqyL3Gug5NgxiE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=H4yDbrMg; arc=none smtp.client-ip=91.218.175.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="H4yDbrMg" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1724862131; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=e++uBn8BLrdi0jP9yB3jWjkyW9E9kfTvv2nMDoQy5Wo=; b=H4yDbrMgC+l/SUK5t5e+3dg7hwe6qoKCcmy8lrMc9vJZjJNSZNs3CcWlBBY4rh0pX9+wTf 0qicxm/USNOgoxvKXiKeLIPrRkYr+45P9Qtqj8InERgfHOXO7XzMu0WKL6o/S8HndZ57rp CE6yMLv6ffRhdqYa3k4qN6+/J4ikn7s= From: Andrew Jones To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: atishp@rivosinc.com, cade.richard@berkeley.edu, jamestiotio@gmail.com Subject: [kvm-unit-tests PATCH 3/3] riscv: Provide timer_start and timer_stop Date: Wed, 28 Aug 2024 18:22:04 +0200 Message-ID: <20240828162200.1384696-8-andrew.jones@linux.dev> In-Reply-To: <20240828162200.1384696-5-andrew.jones@linux.dev> References: <20240828162200.1384696-5-andrew.jones@linux.dev> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT For unit tests that need a timer but don't care if they use Sstc or SBI TIME, provide timer_start and timer_stop which will try Sstc first and fallback to SBI TIME. Signed-off-by: Andrew Jones --- lib/riscv/asm/timer.h | 2 ++ lib/riscv/timer.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/lib/riscv/asm/timer.h b/lib/riscv/asm/timer.h index fd12251a3a6b..9e790a97bd24 100644 --- a/lib/riscv/asm/timer.h +++ b/lib/riscv/asm/timer.h @@ -6,6 +6,8 @@ extern void timer_get_frequency(void); extern void local_timer_init(void); +extern void timer_start(unsigned long duration_us); +extern void timer_stop(void); static inline uint64_t timer_get_cycles(void) { diff --git a/lib/riscv/timer.c b/lib/riscv/timer.c index 92826d6ec3fe..67fd031ab95f 100644 --- a/lib/riscv/timer.c +++ b/lib/riscv/timer.c @@ -6,7 +6,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -39,3 +41,34 @@ void local_timer_init(void) csr_write(CSR_STIMECMPH, ULONG_MAX); } } + +void timer_start(unsigned long duration_us) +{ + uint64_t next = timer_get_cycles() + usec_to_cycles((uint64_t)duration_us); + + if (cpu_has_extension(smp_processor_id(), ISA_SSTC)) { + csr_write(CSR_STIMECMP, (unsigned long)next); + if (__riscv_xlen == 32) + csr_write(CSR_STIMECMPH, (unsigned long)(next >> 32)); + } else if (sbi_probe(SBI_EXT_TIME)) { + struct sbiret ret = sbi_set_timer(next); + assert(ret.error == SBI_SUCCESS); + assert(!(next >> 32)); + } else { + assert_msg(false, "No timer to start!"); + } +} + +void timer_stop(void) +{ + if (cpu_has_extension(smp_processor_id(), ISA_SSTC)) { + csr_write(CSR_STIMECMP, ULONG_MAX); + if (__riscv_xlen == 32) + csr_write(CSR_STIMECMPH, ULONG_MAX); + } else if (sbi_probe(SBI_EXT_TIME)) { + struct sbiret ret = sbi_set_timer(ULONG_MAX); + assert(ret.error == SBI_SUCCESS); + } else { + assert_msg(false, "No timer to stop!"); + } +} From patchwork Wed Aug 28 17:18:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13781609 Received: from out-170.mta1.migadu.com (out-170.mta1.migadu.com [95.215.58.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BD1B1A4AA4 for ; Wed, 28 Aug 2024 17:18:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724865520; cv=none; b=dChUgajKL1igCWU+NLQ8gaHPRFA9RbFdyUJLnNE0nWb29NrdV6NuOK5tIGCCoGZl/WgS9r9ABFlqmo1V2skyK1x0ITERaGB2+T9N7zxYxPTfOt51haFKvf1uxCDqXZUI4g38UX3jUpAOhd4LNTmUQqhy8hkBWGFsFq9hze1NMXU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724865520; c=relaxed/simple; bh=u9OWERKTgU0H7S4aQmt520YASXs6yoLIoWVB8AHqDmI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FxkinL/JnWVayqN1HUzx2safdvi2D1P+Z8ve5KgjlhMjmjLTk5XYYEjYhFM/8TiYoSPszHZrYAV04bu0hdZlUZs7OborI893JpFXI5xjvJtJYcmIEP912FC4bNoGbo/I410YvdlznVpCbJRI2Y8qNzGG8wks3gf+4Mcsjs4fzc4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=cW1ErWRi; arc=none smtp.client-ip=95.215.58.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="cW1ErWRi" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1724865514; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tspsh3WEVuEOw9onfJfHYvO1bxNsbjpgCwGyMt1FjK4=; b=cW1ErWRirqfcY2OZh2Ssusbmc4Hl3pYDxfdqAvBfueAyjyevPVLqMZ7MvkdeTQ3WkjZwD+ 7vucHkryCJ5iTG22m7siImapjQlwc8feMgNhW2nfAcyv9Io7LIw7ng0bQEQvHsXgVjCWg+ xPTbPJfr3D1FZm/qoYPc+cPx5QjMuqE= From: Andrew Jones To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: atishp@rivosinc.com, cade.richard@berkeley.edu, jamestiotio@gmail.com Subject: [kvm-unit-tests PATCH 4/3] riscv: QEMU Sstc timer stop workaround Date: Wed, 28 Aug 2024 19:18:28 +0200 Message-ID: <20240828171827.1401255-2-andrew.jones@linux.dev> In-Reply-To: <20240828162200.1384696-5-andrew.jones@linux.dev> References: <20240828162200.1384696-5-andrew.jones@linux.dev> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT QEMU doesn't stop a pending timer when UINT64_MAX is written to stimecmp, see QEMU commit ae0edf2188b3 ("target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX"). We should probably change that in QEMU, but we need a solution in kvm-unit-tests anyway in order to support older QEMU versions. A bit of an ugly workaround is to simply subtract one from UINT64_MAX, which is still a really big number, but not the exact number QEMU is using to decide it should skip the timer update. Signed-off-by: Andrew Jones --- lib/riscv/timer.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/lib/riscv/timer.c b/lib/riscv/timer.c index 67fd031ab95f..28e1626607f7 100644 --- a/lib/riscv/timer.c +++ b/lib/riscv/timer.c @@ -62,9 +62,16 @@ void timer_start(unsigned long duration_us) void timer_stop(void) { if (cpu_has_extension(smp_processor_id(), ISA_SSTC)) { - csr_write(CSR_STIMECMP, ULONG_MAX); + /* + * Subtract one from ULONG_MAX to workaround QEMU using that + * exact number to decide *not* to update the timer. IOW, if + * we used ULONG_MAX, then we wouldn't stop the timer at all, + * but one less is still a big number ("infinity") and it gets + * QEMU to do what we want. + */ + csr_write(CSR_STIMECMP, ULONG_MAX - 1); if (__riscv_xlen == 32) - csr_write(CSR_STIMECMPH, ULONG_MAX); + csr_write(CSR_STIMECMPH, ULONG_MAX - 1); } else if (sbi_probe(SBI_EXT_TIME)) { struct sbiret ret = sbi_set_timer(ULONG_MAX); assert(ret.error == SBI_SUCCESS);