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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B071.mail.protection.outlook.com (10.167.243.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 29 Aug 2024 22:32:39 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 29 Aug 2024 17:32:37 -0500 From: Yazen Ghannam To: CC: , , , , , , Yazen Ghannam Subject: [RFC PATCH v2 1/2] x86/mce: Set a more accurate value for mce_num_banks Date: Thu, 29 Aug 2024 17:32:24 -0500 Message-ID: <20240829223225.223639-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240829223225.223639-1-yazen.ghannam@amd.com> References: <20240829223225.223639-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|BL3PR12MB6402:EE_ X-MS-Office365-Filtering-Correlation-Id: e6599003-d6cd-4d48-1d96-08dcc87a7d53 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 22:32:39.1744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6599003-d6cd-4d48-1d96-08dcc87a7d53 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6402 Some systems advertise more MCA banks than are actually used. For example, MCG_CAP[Count] gives 64 banks, but banks 32-63 are not used, i.e. Read-as-Zero/Writes-Ignored. This causes more time spent checking, or trying to setup, banks that are not used. Currently, valid banks are already checked for during initialization. Extend this to keep track of the last valid bank found and update mce_num_banks to reflect this. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/core.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 2a938f429c4d..33893b5c8b0c 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1866,8 +1866,8 @@ static void __mcheck_cpu_init_clear_banks(void) static void __mcheck_cpu_check_banks(void) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + int i, last_bank; u64 msrval; - int i; for (i = 0; i < this_cpu_read(mce_num_banks); i++) { struct mce_bank *b = &mce_banks[i]; @@ -1877,7 +1877,12 @@ static void __mcheck_cpu_check_banks(void) rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); b->init = !!msrval; + + if (b->init) + last_bank = i; } + + this_cpu_write(mce_num_banks, last_bank + 1); } /* Add per CPU specific workarounds here */ From patchwork Thu Aug 29 22:32:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13783989 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2066.outbound.protection.outlook.com [40.107.92.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C73718A931; 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Thu, 29 Aug 2024 17:32:38 -0500 From: Yazen Ghannam To: CC: , , , , , , Yazen Ghannam Subject: [RFC PATCH v2 2/2] x86/mce: Prevent CPU offline for SMCA CPUs with non-core banks Date: Thu, 29 Aug 2024 17:32:25 -0500 Message-ID: <20240829223225.223639-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240829223225.223639-1-yazen.ghannam@amd.com> References: <20240829223225.223639-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|LV2PR12MB5967:EE_ X-MS-Office365-Filtering-Correlation-Id: b20b7ca9-7b81-4b79-9004-08dcc87a7da6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: hkrFyovlGxOi54aoD8IwVwZZe0yx5EaL3LZ4D3Y9uQxWxoqFVHgbF4/XFyzg9ExLHqzmKpFgoHOpVRjZKqEpdca6Mr+ZbMcVi6KWBl4p5CPVLQXyfUhq8xOc86K7+c6fA+U2D7hUgB2mQus0PULGI9SnlSlmjvz6B2twR60ddMGkSgglJ/RAoFd7rdl/17FtNjGLxotXTeHU/ijyf68tq1yQjH3zpkLZWkPpPTpVO1ftFm5TQxfvrIacWvr0v9vDo4Ss2PAeZYcX7id3QE3beQi/hZbe4A39oK4xo9eMT9Wes/mwZcKnFxVlsBLeARUbeMdUwlKT8c/tImMj+XaRcirvnLAdq/K2w2WKBkN8ESCg4LKOA0+GZtMxU1Hv75/g2rg2nbwVzda9ZCwaAa3sAo5bkDT4z6T5cTeA3lBiVnrJCDogsU7Lc2xQCY3tP4pNPlP006/FLC62xRAigFvWUePjArUjVZkikAQmFDgeWJ+L4RCzy+ryqIP+WB9YPsJwOoAtd6NboWucsKCsqryJVqwUXDx+AUvb2MpG1pUbEyP+Kx8uA4WNwYngTg8YF4siObYgHKi3fu91vgOvw4+51iBnD8elKcOpvhS9s2s4Boez20AmL+GttvBJWU1ZBQ6A+sf2k3uDf6D6MG6DHGhuDnCId9d83X73OoXf/DI6n/3J5ySBSoWblEjr2tGSaD1SJpljgnoWGlg3U/qBMZnpNgwXfanHC2wSF5T0bCTErFHTpEocaeYdZDy55UwGsiWc0YBGxDsJr8iKbqGbvPNn9znVB8ZAkF3OOHEKMm60Poo7lr/KfPXwke7YxNqC1XlQben5Sl/gzgRMk1Ar2YNZ2XTefAgnue03nzh8fHLj4HhjdqdcIaTqz/6hkHw51Vz5zOQbGHEhs5mpR9ZOBhSXxMoba7+sph6EoZ4kWBparz8Q1REvil1ofJim7zP+q/lrq8mD24s3B+hQw2x/AoC0J17rALmjCdirgBGD5r+OSCMntVd42A4xoD8NsSM6UC25dYJZzxo3hAHhpu5a1+UmaURfX3hEdRALx7WI3wLprIZnyjOj5DTiHUrqcIpltdms3IdTS6/efZCQzvRMOPxHJaWS8JEnoPmjs79TAtGQA6BQaRcmZ4qa5ZafrV9fcfZPHuta0Gj8HMFN4SvpTsowrXTy39MzS8/pxDkz82GZzV5pAsqSe+yOkDr7/LtPYCdI2uUeqjH4SUbRNAv1uaqprQOrVVXfRXDdiweo7CW7mD3F9UCmf9rpfrzZonNHsDDA5Ph8I7aFf/1hVMRT9C6Ewra2jxZqN52sOFBiUHoQaWaahoSVKV9J/xAMipLPI4pFnh5xFVybzJkyRbnGlrgs/xis3WHMsnIwSJrQnVhGqo/VAxEYpubdjV/5nQJYMwUvfqoVlTDPYLp4fOFI0GHsXMZVX91nvEw8IuDinqvVVIM0Us2rwpqaQn2oGkQgNMqa X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 22:32:39.7369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b20b7ca9-7b81-4b79-9004-08dcc87a7da6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5967 Logical CPUs in AMD Scalable MCA (SMCA) systems can manage non-core banks. Each of these banks represents unique and separate hardware located within the system. Each bank is managed by a single logical CPU; they are not shared. Furthermore, the "CPU to MCA bank" assignment cannot be modified at run time. The MCE subsystem supports run time CPU hotplug. Many vendors have non-core MCA banks, so MCA settings are not cleared when a CPU is offlined for these vendors. Even though the non-core MCA banks remain enabled, MCA errors will not be handled (reported, cleared, etc.) on SMCA systems when the managing CPU is offline. Mark a CPU as not hotpluggable if it manages non-core MCA banks. This prevents the CPU from being marked offline from sysfs. Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/mce/core.c | 15 +++++++++++++++ arch/x86/kernel/setup.c | 2 +- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 3b9970117a0f..bd9ac102ba49 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -213,12 +213,14 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c); void mcheck_cpu_clear(struct cpuinfo_x86 *c); int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id); +bool mce_cpu_is_hotpluggable(unsigned int cpu); #else static inline int mcheck_init(void) { return 0; } static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {} static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) { return -EINVAL; } +static inline bool mce_cpu_is_hotpluggable(unsigned int cpu) { return true; } #endif void mce_prep_record(struct mce *m); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 33893b5c8b0c..2f4a04092dd0 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2775,6 +2775,21 @@ static int mce_cpu_online(unsigned int cpu) return 0; } +bool mce_cpu_is_hotpluggable(unsigned int cpu) +{ + if (!mce_flags.smca) + return true; + + /* + * SMCA systems use banks 0-6 for core units. Banks 7 and later are + * used for non-core units. + * + * Logical CPUs with 7 or fewer banks can be offlined, since they are not + * managing any non-core units. + */ + return per_cpu(mce_num_banks, cpu) <= 7; +} + static int mce_cpu_pre_down(unsigned int cpu) { struct timer_list *t = this_cpu_ptr(&mce_timer); diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 5d34cad9b7b1..754089334591 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1222,6 +1222,6 @@ __initcall(register_kernel_offset_dumper); #ifdef CONFIG_HOTPLUG_CPU bool arch_cpu_is_hotpluggable(int cpu) { - return cpu > 0; + return cpu > 0 && mce_cpu_is_hotpluggable(cpu); } #endif /* CONFIG_HOTPLUG_CPU */